CN113782637A - Solar cell manufacturing method and solar cell - Google Patents
Solar cell manufacturing method and solar cell Download PDFInfo
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- CN113782637A CN113782637A CN202110975092.5A CN202110975092A CN113782637A CN 113782637 A CN113782637 A CN 113782637A CN 202110975092 A CN202110975092 A CN 202110975092A CN 113782637 A CN113782637 A CN 113782637A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 88
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 88
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 238000005245 sintering Methods 0.000 claims abstract description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 24
- 239000010703 silicon Substances 0.000 claims abstract description 24
- 239000002002 slurry Substances 0.000 claims abstract description 24
- 238000007639 printing Methods 0.000 claims abstract description 15
- 239000000725 suspension Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 27
- 239000002202 Polyethylene glycol Substances 0.000 claims description 9
- 229920001223 polyethylene glycol Polymers 0.000 claims description 9
- 229920000036 polyvinylpyrrolidone Polymers 0.000 claims description 9
- 235000013855 polyvinylpyrrolidone Nutrition 0.000 claims description 9
- 239000001267 polyvinylpyrrolidone Substances 0.000 claims description 9
- 239000000843 powder Substances 0.000 claims description 9
- 238000005507 spraying Methods 0.000 claims description 3
- 238000005215 recombination Methods 0.000 abstract description 8
- 230000006798 recombination Effects 0.000 abstract description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 6
- 239000010931 gold Substances 0.000 abstract description 6
- 229910052737 gold Inorganic materials 0.000 abstract description 6
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 206010067484 Adverse reaction Diseases 0.000 description 1
- 101001073212 Arabidopsis thaliana Peroxidase 33 Proteins 0.000 description 1
- 101001123325 Homo sapiens Peroxisome proliferator-activated receptor gamma coactivator 1-beta Proteins 0.000 description 1
- 102100028961 Peroxisome proliferator-activated receptor gamma coactivator 1-beta Human genes 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000006838 adverse reaction Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
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Abstract
The application is applicable to the technical field of solar cells, and provides a manufacturing method of a solar cell and the solar cell. The manufacturing method of the solar cell comprises the following steps: manufacturing a silicon wafer into a battery substrate of a circuit to be manufactured, wherein the battery substrate comprises a plurality of spaced first areas and a plurality of spaced second areas, and the first areas are crossed with the second areas; preparing a silicon nitride layer in the first region; printing a first slurry on the silicon nitride layer; printing a second paste in a second area; and sintering the battery substrate printed with the first slurry and the second slurry to enable the main grid sintered by the first slurry to be embedded into the silicon nitride layer, and enable the auxiliary grid sintered by the second slurry to form a gold half contact with the silicon wafer, wherein the auxiliary grid is overlapped with the main grid. Thus, the main grid has better weldability, and the recombination loss under the main grid is less.
Description
Technical Field
The application belongs to the technical field of solar cells, and particularly relates to a solar cell manufacturing method and a solar cell.
Background
In the related art, in the case of preparing a battery printing paste of a silicon nitride film, the paste burns through the silicon nitride film during sintering to form a gold half contact with a silicon substrate, thereby forming a conductive channel. The secondary grid collects the current in the silicon substrate and collects the current to the main grid, and the current in the main grid flows to an external circuit through a welding belt welded on the main grid. However, too large a gold half contact area and embedding depth may result in increased recombination losses, and too small a gold half contact area and embedding depth may result in poor solderability of the main grid. Therefore, how to manufacture the solar cell so as to enable the recombination loss to be low and the main grid to be good in weldability becomes a problem to be solved urgently.
Disclosure of Invention
The application provides a solar cell manufacturing method and a solar cell, and aims to solve the problems that how to manufacture the solar cell so that recombination loss is low and main grid weldability is good.
In a first aspect, the present application provides a method for manufacturing a solar cell, including:
manufacturing a silicon wafer into a battery substrate of a circuit to be manufactured, wherein the battery substrate comprises a plurality of spaced first areas and a plurality of spaced second areas, and the first areas and the second areas are crossed;
preparing a silicon nitride layer in the first region;
printing a first slurry on the silicon nitride layer;
printing a second paste on the second area;
and sintering the battery substrate printed with the first paste and the second paste, so that a main grid sintered by the first paste is embedded into the silicon nitride layer, and a secondary grid sintered by the second paste is in half-contact with the silicon wafer, and the secondary grid is overlapped with the main grid.
Optionally, preparing a silicon nitride layer in the first region includes:
preparing a silicon nitride suspension;
attaching the suspension to the first region;
baking the battery substrate attached with the suspension;
and sintering the baked battery substrate.
Optionally, preparing a suspension of silicon nitride, comprising:
silicon nitride powder, polyethylene glycol and polyvinylpyrrolidone were mixed to prepare the suspension.
Optionally, attaching the suspension to the first region includes:
and attaching the suspension to the first area by adopting a printing process or a spraying process.
Optionally, in the step of baking the battery substrate attached with the suspension, the baking temperature ranges from 100 ℃ to 600 ℃, and/or the baking time is 10min to 30 min.
Optionally, in the step of sintering the baked battery substrate, the sintering temperature ranges from 700 ℃ to 800 ℃, and/or the sintering time duration ranges from 1min to 5 min.
Optionally, the silicon nitride layer has a thickness in a range of 0.3 μm to 5 μm.
In a second aspect, the solar cell provided by the present application is manufactured by any one of the above methods.
In a third aspect, the present application provides a solar cell, comprising: the solar cell comprises a cell substrate, a silicon nitride layer, a main grid and an auxiliary grid, wherein the cell substrate is made of a silicon wafer, the cell substrate comprises a plurality of spaced first regions and a plurality of spaced second regions, the first regions are crossed with the second regions, the silicon nitride layer is positioned in the first regions, the main grid is formed by sintering first slurry printed on the silicon nitride layer, the main grid is embedded into the silicon nitride layer, the auxiliary grid is formed by sintering second slurry printed on the second regions, the auxiliary grid is in half-contact with the silicon wafer, and the auxiliary grid is in lap joint with the main grid.
Optionally, the silicon nitride layer has a thickness in a range of 0.3 μm to 5 μm.
According to the manufacturing method of the solar cell and the solar cell, the silicon nitride layer is arranged in the first area of the silicon wafer, so that the first slurry printed on the silicon nitride layer is embedded into the silicon nitride layer during sintering, the main grid formed by sintering the first slurry has high tensile force, and the main grid has good weldability. Meanwhile, the main grid and the silicon wafer are not in direct contact, and current carriers cannot reach a metal interface, so that the recombination loss under the main grid is less. And the auxiliary grid and the silicon wafer form a gold-half contact and are lapped with the main grid, so that the collected current can be transmitted to the main grid, and the normal work of the battery is ensured.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a solar cell according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a solar cell according to an embodiment of the present application;
fig. 3 is a schematic flow chart of a method for manufacturing a solar cell according to an embodiment of the present disclosure;
fig. 4 is a schematic flow chart of a method for manufacturing a solar cell according to an embodiment of the present disclosure;
fig. 5 is a schematic flow chart of a method for manufacturing a solar cell according to an embodiment of the present application.
Description of the main element symbols:
the solar cell comprises a solar cell 10, a cell substrate 11, a silicon nitride layer 12, a front silicon nitride layer 121, a back silicon nitride layer 122, a main grid 13, a front main grid 131, a back main grid 132 and an auxiliary grid 14.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Referring to fig. 1 and fig. 2, a method for manufacturing a solar cell 10 according to an embodiment of the present disclosure includes:
step S11: manufacturing a silicon wafer into a battery substrate 11 of a circuit to be manufactured, wherein the battery substrate 11 comprises a plurality of spaced first areas and a plurality of spaced second areas, and the first areas are crossed with the second areas;
step S12: preparing a silicon nitride layer 12 in the first region;
step S13: printing a first paste on the silicon nitride layer 12;
step S14: printing a second paste in a second area;
step S15: the cell substrate 11 printed with the first paste and the second paste is sintered so that the main grid 13 sintered from the first paste is embedded in the silicon nitride layer 12, and the sub-grid 14 sintered from the second paste is brought into gold half contact with the silicon wafer, the main grid 13 being overlapped with the sub-grid 14.
The solar cell 10 of the embodiment of the present application includes: the battery comprises a battery substrate 11, a silicon nitride layer 12, a main grid 13 and an auxiliary grid 14, wherein the battery substrate 11 is made of a silicon wafer, the battery substrate 11 comprises a plurality of spaced first regions and a plurality of spaced second regions, the first regions are crossed with the second regions, the silicon nitride layer 12 is located in the first regions, the main grid 13 is formed by sintering first slurry printed on the silicon nitride layer 12, the main grid 13 is embedded into the silicon nitride layer 12, the auxiliary grid 14 is formed by sintering second slurry printed on the second regions, and the auxiliary grid 14 is in gold half contact with the silicon wafer.
In the method for manufacturing the solar cell 10 according to the embodiment of the application, the silicon nitride layer 12 is disposed in the first region of the silicon wafer, so that the first paste printed on the silicon nitride layer 12 is embedded into the silicon nitride layer 12 during sintering, and thus the main grid 13 formed by sintering the first paste has a high tensile force, and the main grid 13 has good weldability. Meanwhile, the main grid 13 is not in direct contact with the silicon wafer, and current carriers cannot reach a metal interface, so that recombination loss under the main grid 13 is less. And the auxiliary grid 14 is in half-contact with the silicon wafer and is overlapped with the main grid 13, so that the collected current can be transmitted to the main grid 13, and the normal operation of the battery is ensured.
Specifically, the first region is a region corresponding to the main gate 13. In the present embodiment, one first region corresponds to one main gate 13. Each main grid 13 is located in a corresponding one of the first regions in an orthogonal projection of the cell substrate 11.
It is understood that in other embodiments, one first region may correspond to a plurality of main gates 13. The orthogonal projections of the plurality of main grids 13 on the battery substrate 11 are located in a corresponding one of the first regions.
Specifically, the second region is a region corresponding to the sub-gate 14. In the present embodiment, one second region corresponds to one sub-gate 14. Each of the sub-grids 14 is located in a corresponding one of the second regions in the orthogonal projection of the cell substrate 11.
In this embodiment, the extending directions of the plurality of first regions are parallel to each other, the extending directions of the plurality of second regions are parallel to each other, and the extending direction of the first region is perpendicular to the extending direction of the second region. Therefore, the auxiliary grid 14 and the main grid 13 are vertically lapped regularly, and the production efficiency is improved.
In the present embodiment, the silicon nitride layer 12 includes a front silicon nitride layer 121 and a back silicon nitride layer 122, the main gate 13 includes a front main gate 131 and a back main gate 132, and the sub-gate includes a front sub-gate and a back sub-gate. The first region includes a front first region and a back first region. The second region includes a front second region and a rear second region. The front side silicon nitride layer 121 is located in the front side first region, and the front side main gate 131 is located on a side of the front side silicon nitride layer 121 facing away from the cell substrate 11. The front side sub-grid is positioned in the front side second area. The front main barrier 131 overlaps the front sub-barrier. The back side silicon nitride layer 122 is located in the back side first region, and the back side main gate 132 is located on a side of the back side silicon nitride layer 122 facing away from the cell substrate 11.
In the present embodiment, the front silicon nitride layer 121, the front main grid 131, and the front sub-grid are fabricated on the front surface of the cell substrate 11 using steps S12 through S15, and the back silicon nitride layer 122, the back main grid 132, and the back sub-grid are fabricated on the back surface of the cell substrate 11 using steps S12 through S15.
It is understood that in other embodiments, the front side silicon nitride layer 121, the front side main gate 131 and the front side sub-gate may be formed only on the front side of the cell substrate 11 by steps S12-S15; the back silicon nitride layer 122, the back main gate 132, and the back sub-gate may also be fabricated only on the back surface of the cell substrate 11 using steps S12 through S15.
In this embodiment, the first paste and the second paste are silver pastes. Thus, the main gate 13 and the sub-gate 14 are made to be conductive.
It is understood that in other embodiments, the first paste may be an aluminum paste, a copper paste, or other paste. The second slurry may be an aluminum slurry, a copper slurry, or other slurry. The first slurry and the second slurry may be different.
Specifically, in step S11, the silicon wafer may be subjected to texturing, diffusion, laser SE, etching, annealing, PERC, PECVD, etc., to form the cell substrate 11.
Specifically, in the present embodiment, the burn-through capability of the second slurry is smaller than that of the first slurry.
In this way, the main grid 13 sintered from the first paste is embedded deeper in the silicon nitride layer 12, so that the main grid 13 has higher tensile force and weldability. Meanwhile, the auxiliary grid 14 sintered by the second slurry is embedded shallowly in the battery substrate 11, so that PN junction burning-through can be avoided, and the recombination loss can be reduced.
Optionally, the silicon nitride layer 12 has a thickness in the range of 0.3 μm to 5 μm. For example, 0.3. mu.m, 0.32. mu.m, 0.5. mu.m, 0.8. mu.m, 1. mu.m, 1.2. mu.m, 1.5. mu.m, 1.8. mu.m, 2. mu.m, 2.5. mu.m, 3. mu.m, 3.7. mu.m, 4. mu.m, 4.8. mu.m, 5. mu.m. Therefore, the thickness of the silicon nitride layer 12 is in a proper range, the main gate 13 penetrating through the silicon nitride layer 12 and contacting with a silicon wafer caused by the over-small thickness of the silicon nitride layer 12 can be avoided, the recombination loss under the main gate 13 is reduced, and the raw material waste caused by the over-large thickness of the silicon nitride layer 12 can also be avoided.
Referring to fig. 3, optionally, step S12 includes:
step S121: preparing a silicon nitride suspension;
step S122: attaching the suspension to the first region;
step S123: baking the battery substrate 11 to which the suspension is attached;
step S124: and sintering the baked battery substrate 11.
In this way, by baking and sintering the cell substrate 11 to which the suspension is attached in the first region, the silicon nitride layer 12 is formed in the first region, and the efficiency is high.
It is understood that in other embodiments, the silicon nitride layer 12 may be deposited in the first region using a coating apparatus.
Further, covering a preset mask on the battery substrate 11, placing the battery substrate covered with the mask into a coating device, exposing the first region of the battery substrate 11 from the mask, and covering the region of the battery substrate 11 except the first region with the mask; introducing SiH into coating equipment4And NH3To deposit a silicon nitride layer 12 in the first region.
Further, the coating apparatus may be a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus. Thus, the deposition rate is fast, and the quality of the silicon nitride layer 12 is good.
Further, a mask may be prepared in the region of the battery substrate 11 other than the first region before step S12. After step S12, the mask may be removed for subsequent fabrication. Thus, the gap between the mask and the cell substrate 11 is made small, and gas is prevented from entering the region other than the first region through the gap between the mask and the cell substrate 11 during vapor deposition.
Referring to fig. 4, optionally, step S121 includes:
step S1211: silicon nitride powder, polyethylene glycol and polyvinylpyrrolidone were mixed to prepare a suspension.
Therefore, the suspension of the silicon nitride can be prepared, and the efficiency is high.
Specifically, the silicon nitride powder, the polyethylene glycol and the polyvinylpyrrolidone may be placed in the accommodating groove, and the silicon nitride powder, the polyethylene glycol and the polyvinylpyrrolidone placed in the accommodating groove may be stirred. Thus, the silicon nitride powder, the polyethylene glycol and the polyvinylpyrrolidone can be sufficiently mixed.
Further, silicon nitride powder, polyethylene glycol and polyvinylpyrrolidone can be simultaneously placed in the accommodating groove; the silicon nitride powder, the polyethylene glycol and the polyvinylpyrrolidone can also be placed in the containing groove in different orders. The order of putting the three components is not limited herein.
Specifically, the weight ratio of the silicon nitride powder, the polyethylene glycol and the polyvinylpyrrolidone can be 1 (0.1-0.5) to 0.1-0.5. For example, 1:0.1:0.1, 1:0.1:0.2, 1:0.1:0.3, 1:0.1:0.4, 1:0.1:0.5, 1:0.2:0.1, 1:0.3:0.1, 1:0.4:0.1, 1:0.5:0.1, 1:0.4:0.3, 1:0.2: 0.3.
Referring to fig. 5, optionally, step S122 includes:
step S1221: and (4) attaching the suspension to the first area by adopting a printing process or a spraying process.
Therefore, the suspension can be efficiently and accurately attached to the first region, which is beneficial to improving the production efficiency and ensuring that the silicon nitride layer 12 is positioned in the first region.
In particular, the printing process may be screen printing.
Specifically, a preset shielding member may be covered on the battery substrate 11 before step S122, so that the first region is exposed from the shielding member, and so that the region of the battery substrate 11 other than the first region is shielded by the shielding member. In this way, it is possible to prevent the suspension from entering the region of the battery substrate 11 other than the first region by mistake in the process of attaching the suspension to the first region, and it is possible to ensure that the silicon nitride layer 12 is located in the first region.
Specifically, a mask may be prepared on the battery substrate 11 except for the first region, such that the first region is exposed from the mask, and such that the region of the battery substrate 11 except for the first region is covered by the mask, before step S122. After step S124, the mask may be removed for subsequent fabrication. In this way, the suspension can be prevented from entering the region of the battery substrate 11 other than the first region by mistake in the process of attaching the suspension to the first region, and the suspension can be prevented from entering the region other than the first region through the gap between the mask and the battery substrate 11, so that the silicon nitride layer 12 can be ensured to be located in the first region.
Specifically, after step S1221, the suspension located outside the first region may be wiped or sucked off. Therefore, the suspension outside the first region can be cleaned in time, and the silicon nitride layer 12 is prevented from being formed outside the first region.
Alternatively, in step S123, the baking temperature ranges from 100 ℃ to 600 ℃. For example, 100 ℃, 101 ℃, 105 ℃, 110 ℃, 150 ℃, 200 ℃, 280 ℃, 350 ℃, 430 ℃, 560 ℃ and 600 ℃. Therefore, the baking temperature is in a proper range, adverse reaction caused by overhigh baking temperature is avoided, and insufficient baking caused by overlow baking temperature can also be avoided.
Optionally, in step S123, the baking time period ranges from 10min to 30 min. For example, 10min, 11min, 15min, 17min, 20min, 22min, 25min, 29min, and 30 min. So for it is in suitable scope to toast time, avoids toasting long time and leads to the efficiency too low, also can avoid toasting long too short not enough of leading to toasting.
Optionally, before step S123, a protective gas may be introduced into the baking chamber. Therefore, impurity gas in the baking cavity can be removed, the battery substrate 11 or suspension liquid is prevented from reacting with the impurity gas at high temperature, and other substances are prevented from affecting the preparation of the silicon nitride layer 12.
Alternatively, in step S124, the sintering temperature ranges from 700 ℃ to 800 ℃. For example, 700 deg.C, 702 deg.C, 715 deg.C, 720 deg.C, 735 deg.C, 744 deg.C, 750 deg.C, 765 deg.C, 780 deg.C, 792 deg.C, 800 deg.C. Therefore, the sintering temperature is in a proper range, excessive energy consumption caused by overhigh sintering temperature is avoided, and poor sintering effect caused by overlow sintering temperature can also be avoided.
Optionally, in step S124, the sintering time period ranges from 1min to 5 min. For example, 1min, 1.2min, 1.5min, 2min, 2.4min, 3min, 3.6min, 4min, 4.8min, 5 min. Therefore, the sintering time is in a proper range, the problem that the efficiency is too low due to too long sintering time is avoided, and the problem that the sintering effect is poor due to too short sintering time is also avoided.
Optionally, before step S124, a protective gas may be introduced into the sintering chamber. Therefore, impurity gas in the sintering cavity can be removed, and the battery substrate 11 or silicon nitride is prevented from reacting with the impurity gas at high temperature, so that other substances are prevented from affecting the preparation of the silicon nitride layer 12.
In this embodiment, the battery substrate 11 to which the suspension is attached may be put in an oven, and baked in the oven. The baked battery substrate 11 may be placed in a tunnel furnace to be sintered using the tunnel furnace. Therefore, the baking advantages of the baking oven and the sintering advantages of the tunnel furnace can be fully utilized, and the baking and sintering effects are good.
In one example, the silicon nitride layer 12 is 3 μm thick. The baking temperature is 500 ℃, and the baking time is 20 min. The sintering temperature is 760 ℃, and the sintering time is 3 min.
It is understood that in other embodiments, the baking and sintering may be performed in the same apparatus. Thus, the battery substrate 11 does not need to be frequently transferred, which is advantageous for improving the production efficiency. In particular, a heating lamp tube may be disposed within the chamber. The temperature in the chamber can be controlled by adjusting the power of the heating lamps and adjusting the number of the heating lamps which are turned on.
Alternatively, in step S13, the orthographic projection of the silicon nitride layer 12 on the battery substrate 11 covers and exceeds the orthographic projection of the printed area of the first paste on the battery substrate 11. In this way, the edge of the printed area of the first paste is spaced from the edge of the silicon nitride layer 12, preventing the first paste from flowing along the side of the silicon nitride layer to the cell substrate 11.
In this embodiment, the printing of the first paste and the printing of the second paste both employ a screen printing process.
The solar cell 10 according to the embodiment of the present application is manufactured by any one of the above-described methods.
The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
Claims (10)
1. A method for manufacturing a solar cell, comprising:
manufacturing a silicon wafer into a battery substrate of a circuit to be manufactured, wherein the battery substrate comprises a plurality of spaced first areas and a plurality of spaced second areas, and the first areas and the second areas are crossed;
preparing a silicon nitride layer in the first region;
printing a first slurry on the silicon nitride layer;
printing a second paste on the second area;
and sintering the battery substrate printed with the first paste and the second paste, so that a main grid sintered by the first paste is embedded into the silicon nitride layer, and a secondary grid sintered by the second paste is in half-contact with the silicon wafer, and the secondary grid is overlapped with the main grid.
2. The method of claim 1, wherein the step of forming a silicon nitride layer in the first region comprises:
preparing a silicon nitride suspension;
attaching the suspension to the first region;
baking the battery substrate attached with the suspension;
and sintering the baked battery substrate.
3. The method of claim 2, wherein preparing a suspension of silicon nitride comprises:
silicon nitride powder, polyethylene glycol and polyvinylpyrrolidone were mixed to prepare the suspension.
4. The method of claim 2, wherein attaching the suspension to the first region comprises:
and attaching the suspension to the first area by adopting a printing process or a spraying process.
5. The method according to claim 2, wherein in the step of baking the cell substrate to which the suspension is attached, the baking temperature is in a range of 100 ℃ to 600 ℃, and/or the baking time is in a range of 10min to 30 min.
6. The method of claim 2, wherein in the step of sintering the baked cell substrate, the sintering temperature is in a range of 700 ℃ to 800 ℃, and/or the sintering time is in a range of 1min to 5 min.
7. The method of claim 1, wherein the silicon nitride layer has a thickness in a range of 0.3 μm to 5 μm.
8. A solar cell, characterized in that it is produced by the method according to any one of claims 1 to 7.
9. A solar cell, comprising: the solar cell comprises a cell substrate, a silicon nitride layer, a main grid and an auxiliary grid, wherein the cell substrate is made of a silicon wafer, the cell substrate comprises a plurality of spaced first regions and a plurality of spaced second regions, the first regions are crossed with the second regions, the silicon nitride layer is positioned in the first regions, the main grid is formed by sintering first slurry printed on the silicon nitride layer, the main grid is embedded into the silicon nitride layer, the auxiliary grid is formed by sintering second slurry printed on the second regions, the auxiliary grid is in half-contact with the silicon wafer, and the auxiliary grid is in lap joint with the main grid.
10. The solar cell of claim 9, wherein the silicon nitride layer has a thickness in a range of 0.3 μ ι η to 5 μ ι η.
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| WO2014012432A1 (en) * | 2012-07-16 | 2014-01-23 | 杭州塞利仕科技有限公司 | Front-side electrode structure of solar cell sheet and fabrication method therefor |
| CN112133767A (en) * | 2019-06-24 | 2020-12-25 | 泰州隆基乐叶光伏科技有限公司 | Solar cell and manufacturing method thereof |
| CN112234109A (en) * | 2020-11-06 | 2021-01-15 | 通威太阳能（安徽）有限公司 | Solar cell, front electrode thereof, preparation method and application |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2014012432A1 (en) * | 2012-07-16 | 2014-01-23 | 杭州塞利仕科技有限公司 | Front-side electrode structure of solar cell sheet and fabrication method therefor |
| CN112133767A (en) * | 2019-06-24 | 2020-12-25 | 泰州隆基乐叶光伏科技有限公司 | Solar cell and manufacturing method thereof |
| CN112234109A (en) * | 2020-11-06 | 2021-01-15 | 通威太阳能（安徽）有限公司 | Solar cell, front electrode thereof, preparation method and application |
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