CN113782529A - Integrated chip, manufacturing method thereof and integrated circuit - Google Patents
Integrated chip, manufacturing method thereof and integrated circuit Download PDFInfo
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- CN113782529A CN113782529A CN202110995384.5A CN202110995384A CN113782529A CN 113782529 A CN113782529 A CN 113782529A CN 202110995384 A CN202110995384 A CN 202110995384A CN 113782529 A CN113782529 A CN 113782529A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Abstract
The application provides an integrated chip, a manufacturing method thereof and an integrated circuit. The integrated chip includes: the switch comprises a silicon substrate, a switch control circuit based on a silicon semiconductor, a gallium arsenide epitaxial structure and a switch circuit based on gallium arsenide; the silicon substrate is divided into a silicon device region and a gallium arsenide device region; the switch control circuit based on the silicon semiconductor is arranged on the silicon substrate and correspondingly arranged in the silicon device area; the gallium arsenide epitaxial structure is arranged on the silicon substrate and corresponds to the gallium arsenide device region; and a gallium arsenide-based switching circuit disposed on the gallium arsenide epitaxial structure; the silicon semiconductor-based switch control circuit and the gallium arsenide-based switch circuit are interconnected through metal; the gallium arsenide-based switching circuit comprises a gallium arsenide high electron mobility transistor, and a silicon semiconductor-based switching control circuit and a gallium arsenide-based switching circuit can be integrated on one chip, so that higher integration level, smaller device area, lower manufacturing cost and better performance are realized.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to an integrated chip, a method for manufacturing the same, and an integrated circuit.
Background
With the development of communication technology, radio frequency devices are widely used, including base stations, mobile phones and other various intelligent terminal devices, as well as Sub-6GHz frequency bands and millimeter wave frequency bands. The radio frequency front end is a core system for realizing the radio frequency signal receiving and transmitting functions of the front end of the whole wireless communication intelligent terminal, and is generally composed of a plurality of devices such as a Power Amplifier (PA), a Filter (Filter), a Low Noise Amplifier (LNA), a radio frequency Switch (RF Switch) and the like. The pursuit of low power consumption, high performance and low cost is the main driving force for upgrading communication technology and also the main direction for chip design and development. The technical upgrade of the radio frequency circuit mainly depends on the combination of new design, new process and new material, and the miniaturization and integration of devices are the main trend in 5G and future mobile communication.
Gallium arsenide (GaAs) compound semiconductor is one of the main materials of radio frequency power amplifiers and radio frequency switches of wireless communication systems, and has gained important application in the fabrication of microwave devices and high speed digital circuits due to its high electron mobility. The semiconductor device made of gallium arsenide has the advantages of good high-frequency performance, low noise, strong radiation resistance and the like. The method is used for manufacturing a heterojunction bipolar transistor (GaAs HBT) and a high electron mobility transistor (GaAs pHEMT), and is widely applied to equipment systems such as mobile phones, satellite communication, microwave point-to-point connection, radar systems and the like.
At present, various radio frequency front-end chips are produced by different manufacturers or manufactured by different product lines of the same company and then integrated into a module in a packaging stage to be provided for an end user, so that the defects of high manufacturing cost, large device area, large system loss and the like are overcome.
Disclosure of Invention
The purpose of the application is to provide an integrated chip, a manufacturing method thereof and an integrated circuit, wherein a gallium arsenide device and a silicon device are integrated on one chip.
The application discloses integrated chip includes: the switch comprises a silicon substrate, a switch control circuit based on a silicon semiconductor, a gallium arsenide epitaxial structure and a switch circuit based on gallium arsenide; the silicon substrate is divided into a silicon device region and a gallium arsenide device region; the switch control circuit based on the silicon semiconductor is arranged on the silicon substrate and correspondingly arranged in the silicon device area; the gallium arsenide epitaxial structure is arranged on the silicon substrate and corresponds to the gallium arsenide device region; and a gallium arsenide-based switching circuit disposed on the gallium arsenide epitaxial structure; the silicon semiconductor-based switch control circuit is electrically connected with the gallium arsenide-based switch circuit; the gallium arsenide based switching circuit includes gallium arsenide high electron mobility transistors.
Optionally, the gallium arsenide-based switching circuit includes: a first transistor and a second transistor; the output ends of the first transistor and the second transistor are connected to a common port, the input end of the first transistor is connected to a first input port, the input end of the second transistor is connected to a second input port, and the control ends of the first transistor and the second transistor are respectively connected to a switch control circuit based on a silicon semiconductor.
Optionally, the gallium arsenide-based switching circuit further includes: the circuit comprises a first resistor, a second resistor, a first capacitor and a second capacitor; the first resistor is connected to the control end of the first transistor in series, one end of the first capacitor is connected to the control end of the first transistor, and the other end of the first capacitor is grounded; the second resistor is connected in series to the control end of the second transistor, one end of the second capacitor is connected to the control end of the second transistor, and the other end of the second capacitor is grounded.
Optionally, the silicon semiconductor-based switch control circuit comprises a Si CMOS inverter; the Si CMOS inverter comprises an N-type MOS tube and a P-type MOS tube; the source electrode of the N-type MOS tube is connected to the drain electrode of the P-type MOS tube; the first transistor and the second transistor are gallium arsenide high electron mobility transistors respectively; the gallium arsenide high electron mobility transistor includes: the grid electrode, the source electrode and the drain electrode are arranged above the epitaxial structure; a passivation layer disposed over the gate electrode, the source electrode and the drain electrode; the first metal layer is arranged above the passivation layer and is connected with the source electrode and the drain electrode; and the second metal layer is connected with the first metal layer and is arranged above the first metal layer.
Optionally, the gallium arsenide epitaxial structure includes: a buffer layer disposed on the silicon substrate; a superlattice layer disposed on the buffer layer; a first isolation layer disposed on the superlattice layer; a channel layer disposed on the first isolation layer; a second isolation layer disposed on the channel layer; a barrier layer disposed on the second isolation layer; a cap layer disposed on the barrier layer.
The application also discloses a manufacturing method of the integrated chip, which comprises the following steps:
dividing a silicon device region and a gallium arsenide device region on a wafer;
forming a gallium arsenide epitaxial structure on the silicon substrate corresponding to the gallium arsenide device region;
forming a gallium arsenide-based switching circuit on the gallium arsenide epitaxial structure;
forming a silicon semiconductor-based switch control circuit in a silicon device region corresponding to a silicon substrate;
forming a metal interconnect layer between the gallium arsenide based switch circuitry and the silicon semiconductor based switch control circuitry;
wherein the gallium arsenide based switching circuit comprises a gallium arsenide high electron mobility transistor.
Optionally, the step of forming the gallium arsenide-based switch circuit on the gallium arsenide epitaxial structure includes the steps of:
forming a source electrode and a drain electrode on the gallium arsenide epitaxial structure;
forming a first passivation layer on the source electrode and the drain electrode;
etching the first passivation layer;
forming a gate electrode so that the gate electrode is connected with the epitaxial structure;
forming a second passivation layer on the first passivation layer;
etching on the second passivation layer corresponding to the source and drain electrodes;
forming a first metal layer;
forming an inter-metal dielectric on the second passivation layer;
forming a second metal layer on the inter-metal dielectric, wherein the second metal layer is connected with the first metal layer;
optionally, the step of forming the gallium arsenide epitaxial structure on the silicon substrate corresponding to the gallium arsenide device region includes:
forming a gallium arsenide epitaxial structure on a silicon substrate;
removing the gallium arsenide epitaxial structure in the silicon device region by wet etching or dry etching; and keeping a gallium arsenide epitaxial structure on the gallium arsenide device region.
Optionally, the step of forming the gallium arsenide epitaxial structure on the silicon substrate corresponding to the gallium arsenide device region includes:
forming a layer of silicon oxide or silicon nitride on a silicon substrate;
removing silicon oxide or silicon nitride in the gallium arsenide device region by etching;
forming a gallium arsenide epitaxial structure corresponding to the gallium arsenide device region on the silicon substrate;
and removing the silicon oxide or the silicon nitride in the silicon device area.
The application also discloses an integrated circuit, which comprises the wafer and the integrated chip, wherein the integrated chip is arranged on the wafer.
Compared with the technical scheme that a GaAs-based device (such as a gallium arsenide device of a semiconductor or a photoelectric chip) and a Si-based device (such as a silicon device of a control or drive chip) are manufactured respectively, the method has the advantages that the gallium arsenide material and the epitaxial structure are manufactured on the silicon substrate, the existing GaAs HBT and GaAs pHEMT devices and various photoelectric chips can be manufactured, integration of silicon-based semiconductor devices (such as CMOS chips) can be realized, and meanwhile, the manufacturing cost of the chips can be reduced by utilizing large-size silicon wafers. In addition, in the application of forming the gallium arsenide device on the silicon substrate, the consumption of gallium arsenide substrate materials is greatly reduced, and the pollution risk of arsenic to the environment is greatly reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
FIG. 1 is a schematic diagram of an exemplary silicon device and gallium arsenide device package of the present application;
FIG. 2 is a schematic diagram illustrating steps of a method for fabricating an integrated chip according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating steps of another method for fabricating an integrated chip according to an embodiment of the present application;
FIG. 4 is a schematic illustration of the present application corresponding to FIG. 3 for forming a gallium arsenide epitaxial structure;
FIG. 5 is a schematic diagram illustrating steps in another method for fabricating an integrated chip according to an embodiment of the present application;
figure 6 is a schematic illustration of forming a gallium arsenide epitaxial structure of the present application corresponding to figure 3;
FIG. 7 is a schematic diagram illustrating steps in another method for fabricating an integrated chip according to an embodiment of the present application;
FIG. 8 is a schematic illustration of a gallium arsenide epitaxial structure formed on a silicon substrate according to an embodiment of the present application;
FIG. 9 is a schematic view of another gallium arsenide epitaxial structure formed on a silicon substrate according to an embodiment of the present application;
FIG. 10 is a schematic view of another gallium arsenide epitaxial structure formed on a silicon substrate according to an embodiment of the present application;
FIG. 11 is a schematic diagram of an integrated chip of an embodiment of the present application;
FIG. 12 is a schematic view of a wafer according to an embodiment of the present application;
FIG. 13 is a schematic diagram of a gallium arsenide based switching circuit according to an embodiment of the present application;
FIG. 14 is a schematic diagram of a silicon semiconductor based switch control circuit according to an embodiment of the present application;
FIG. 15 is a schematic diagram of another silicon semiconductor based switch control circuit according to an embodiment of the present application;
FIG. 16 is a schematic diagram of an integrated silicon semiconductor-based switch control circuit and gallium arsenide-based switch circuit according to an embodiment of the present application;
FIG. 17 is a schematic diagram of an integrated silicon semiconductor-based switch control circuit and gallium arsenide-based switch circuit according to an embodiment of the present application;
FIG. 18 is a schematic illustration of a method of fabricating an integrated chip according to an embodiment of the present application;
fig. 19 is a schematic diagram of a gallium arsenide high electron mobility transistor according to an embodiment of the present application;
fig. 20 is a schematic diagram of another gallium arsenide high electron mobility transistor according to an embodiment of the present application.
100, an integrated circuit; 110. a wafer; 120. an integrated chip; 121. a silicon substrate; 122. a gallium arsenide epitaxial structure; 1221. a buffer layer; 1222. a superlattice layer; 1223. a first isolation layer; 1224. a channel layer; 1225. a second isolation layer; 1226. a barrier layer; 1227. a cap layer; 124. a gallium arsenide device; 124a, a gallium arsenide device region; 125. a silicon device; 125a, a silicon device region; 130. a gallium arsenide based switching circuit; 131. a first transistor; 132. A second transistor; 133. a first resistor; 134. a second resistor; 135. a first capacitor; 136. A second capacitor; 140. a gallium arsenide high electron mobility transistor; 1401. a source electrode; 1402. a drain electrode; 1403. a first passivation layer; 1404. a gate electrode; 1405. a second passivation layer; 1406. a first metal layer; 1407. a second metal layer; 1408. an inter-metal dielectric; 150. a silicon semiconductor based switch control circuit; 151. a Si CMOS inverter; 152. an N-type MOS tube; 153. a P-type MOS tube; 201. silicon dioxide; 202. and (7) photoresist.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application is described in detail below with reference to the figures and alternative embodiments.
In the exemplary embodiment shown in fig. 1, a GaAs based device (e.g., a GaAs device 124 such as a semiconductor or optoelectronic chip) and a Si based device (e.g., a Si device 125 such as a control or driver chip) are fabricated separately. Wherein the silicon device 125 is completed in a silicon-based semiconductor factory and the GaAs device is completed in a compound semiconductor factory. And the manufactured chips form an integrated module during packaging to achieve the required device function or performance. The pursuit of high performance, low cost and low power consumption is the main driving force for upgrading the technology thereof, and is also the main direction for chip design and development. Improving the integration level of the device is one of means for realizing high performance, low cost and low power consumption. There are two ways to improve the integration: firstly, integrate the device of different functions, form the module when the encapsulation, secondly make the device of multiple different functions on same chip, reach higher integrated level, obtain better performance, littleer volume and lower cost. The present application proposes a technical solution for integrating the gaas device 124 and the si device 125 on one chip, which is as follows:
as shown in fig. 2, as an embodiment of the present application, a method for manufacturing an integrated chip is disclosed, which includes the steps of:
s10: dividing a silicon device region and a gallium arsenide device region on a wafer;
s20: forming a gallium arsenide epitaxial structure on the silicon substrate corresponding to the gallium arsenide device region;
s30: forming a gallium arsenide-based switching circuit on the gallium arsenide epitaxial structure;
s40: forming a silicon semiconductor-based switch control circuit on a silicon substrate corresponding to a silicon device region;
s50: forming a metal interconnect layer between the gallium arsenide based switch circuitry and the silicon semiconductor based switch control circuitry;
wherein the gallium arsenide based switching circuit comprises a gallium arsenide high electron mobility transistor.
Compared with the technical scheme that a GaAs-based device (such as a GaAs device 124 such as a semiconductor or a photoelectric chip) and a Si-based device (such as a silicon device 125 such as a control or drive chip) are respectively manufactured, the method has the advantages that the GaAs material and the epitaxial structure are manufactured on the silicon substrate 121, the existing GaAs HBT and GaAs pHEMT devices and various photoelectric chips can be manufactured, integration of silicon-based semiconductor devices (such as CMOS chips) can be realized, and meanwhile, the manufacturing cost of the chips can be reduced by using the large-size silicon wafer 110. In addition, in the application of forming the gaas device 124 on a si substrate, the consumption of the gaas substrate material is greatly reduced, and the risk of environmental pollution caused by arsenic is greatly reduced.
It should be noted that, in the above steps, the steps of S30 and S40 may be interchanged, that is, the "silicon device fabrication process" is performed first, and then the "GaAs device fabrication process" is performed. In order to improve the manufacturing efficiency, the GaAs device manufacturing process and the silicon-based device manufacturing process may be alternately performed, or a common process between the GaAs device manufacturing process and the silicon-based device manufacturing process may be simultaneously performed, which is not particularly limited in the present application. The switch control circuit based on silicon semiconductor comprises a silicon-based CMOS control circuit or a silicon-based CMOS drive circuit; gallium arsenide-based switching circuits include: a gallium arsenide-based semiconductor transistor or a gallium arsenide-based monolithic integrated circuit; the gallium arsenide epitaxial structure comprises: an epitaxial structure of a gallium arsenide heterojunction bipolar transistor or an epitaxial structure of a gallium arsenide high electron mobility transistor or an epitaxial structure of a gallium arsenide laser diode.
As shown in fig. 3, in step S20, the method further includes the following steps:
s201: forming a gallium arsenide epitaxial structure on a silicon substrate;
s202: removing the gallium arsenide epitaxial structure in the silicon device region by wet etching or dry etching; and keeping a gallium arsenide epitaxial structure on the gallium arsenide device region.
In the embodiment, the silicon substrate 121 of the wafer 110 is divided into a divided silicon device region 125a and a gallium arsenide device region 124a by an etching process; the divided regions in S10 are defined by the silicon device region 125a and the gallium arsenide device region 124a in consideration of the positions where the silicon device 125 and the gallium arsenide device 124 are placed when designing the integrated chip. The divided silicon device region 125a is different from the gallium arsenide device region 124a in that the silicon device 125 may be formed directly on the silicon substrate 121, and the gallium arsenide device 124 needs to be formed on the gallium arsenide epitaxial structure 122. Therefore, the present embodiment employs removing the gaas epitaxial structure 122 in the si device region 125a after forming a layer of the gaas epitaxial structure 122 on the si substrate 121.
As shown in FIG. 4, a silicon substrate 121 is formed with a first layerThe layered gallium arsenide epitaxial structure 122 forms a photoresist corresponding to the gallium arsenide device region 124a, after alignment, exposure and development, the gallium arsenide epitaxial structure 122 of the silicon device region 125a is removed by using a wet or dry etching process, and after the photoresist is stripped and cleaned, the gallium arsenide epitaxial structure 122 corresponding to the gallium arsenide device region 124a and the silicon substrate 121 corresponding to the silicon device region 125a on the silicon substrate 121 can be formed. Note that, the etching of the GaAs epitaxy may use a wet or dry etching process. The wet process is carried out in an aqueous solution of phosphoric acid (H3PO4) and hydrogen peroxide (H2O 2). The dry etching adopts plasma etching process, and the gas can be Cl2、BCl3、SiCl4、CF4、CCl2F2And the required etching result is achieved by controlling the microwave power of the reaction cavity, the pressure in the cavity, the type and the flow of the gas.
As shown in fig. 5, a selective gallium arsenide epitaxial structure 122 may also be used, and the step of S20 further includes the steps of:
s211: forming a layer of silicon oxide or silicon nitride on a silicon substrate;
s212: removing silicon oxide or silicon nitride in the gallium arsenide device region by etching;
s213: forming a gallium arsenide epitaxial structure corresponding to the gallium arsenide device region on the silicon substrate;
s214: and removing the silicon oxide or the silicon nitride in the silicon device area.
In the selective growth method of the gaas epitaxial structure 122 adopted in this embodiment, as shown in fig. 6, before the gaas epitaxial structure 122 is fabricated, a layer of silicon oxide or silicon nitride is fabricated on the surface of the silicon substrate 121, and the silicon oxide or silicon nitride corresponding to the gaas region is removed by etching. Because the gallium arsenide epitaxial structure 122 will only grow on the silicon surface and not on the silicon oxide or silicon nitride surface, when forming the gallium arsenide epitaxial structure 122, it will only grow on the corresponding gallium arsenide device region 124a and not on the silicon device region 125 a; finally, the silicon oxide or silicon nitride on the surface of the silicon substrate 121 is removed by etching. Among them, there are many methods for forming silicon oxide and silicon nitride films, such as PECVD. LPCVD, and the like. The thickness of the silicon oxide and silicon nitride films is generally between 10nm and 100 nm; the etching of the silicon oxide and the silicon nitride can adopt a wet method or a dry method, and the wet method can adopt hydrofluoric acid (HF) wet etching or buffered silicon oxide etching solution (BOE) or buffered hydrofluoric acid (BHF). Dry etching is a plasma etching process, typically using a fluorocarbon chemistry, such as CF4、C3F8、CHF3、 C4F8And the like.
Specifically, gallium arsenide materials can also be classified into gallium arsenide crystals (bulk single crystals) and gallium arsenide epitaxial structures 122 (epitaxial materials). The bulk single crystal can be used as a substrate material for the gallium arsenide epitaxial structure 122, or an ion implantation doping process can be used to directly fabricate an integrated circuit (using a high quality, large cross-section, semi-insulating gallium arsenide single crystal). One commonly used method is the liquid seal czochralski method (called the liquid seal geohryski method for short LEC method), and the other method is the horizontal boat growth method (called the horizontal brilliance method), and the single crystal produced has good quality and uniformity, and still receives certain attention. A new development of the liquid seal Czochralski method is the direct synthesis and pulling of undoped, semi-insulating gallium arsenide single crystals in a high pressure single crystal furnace using a Pyrolytic Boron Nitride (PBN) crucible and a dry boron oxide liquid seal. In addition, methods using a quartz crucible and hydrous boron oxide as a liquid sealant under normal pressure have also been successfully tested. No matter the horizontal boat growth method or the liquid seal Czochralski method, the diameter of the crystal can reach 100-150 mm, and is similar to that of a silicon single crystal.
Gallium arsenide epitaxial structure 122 growth may be divided into vapor phase and liquid phase epitaxy by process, with the resulting epitaxial structure being superior to bulk single crystal materials in terms of both purity and crystal integrity. The general vapor phase epitaxy process is Ga/AsCl3/H2The method is carried out. A variant of this process is Ga/HCl/AsH3/H2And Ga/AsCl3/N2The method is carried out. In order to improve Ga/AsCl3/H2The quality of the vapor phase epitaxial structure of the system also researches the epitaxial growth process at low temperature and low pressure. The liquid phase epitaxy process is to cover the surface of the substrate with Ga/GaAs molten pool and then to grow epitaxial structure by cooling, and may also adopt temperature gradient growth method or electric epitaxy method applying direct current.Vapor phase epitaxy has been used more widely than liquid phase epitaxy in the fabrication of devices, particularly microwave devices. Liquid phase epitaxy can be used to fabricate heterojunctions (e.g., GaAs/AlxGa1-xAs), and is therefore an important tool for fabricating GaAs double heterojunction lasers and solar cells, among others.
Gallium arsenide epitaxy technology also includes Molecular Beam Epitaxy (MBE) and metalorganic vapor deposition (MOCVD) epitaxy. Molecular beam epitaxy is a method of growing epitaxial structures by reacting one or more thermal molecular beams with the surface of a crystal under ultra-high vacuum conditions. By applying tight control over the incident molecular or atomic beam current, a superlattice structure may be grown, for example, a structure consisting of alternating thin layers of GaAs and AlxGaAs (only 10 angstroms thick). Vapor deposition epitaxy of organometallic compounds is performed using Trimethylgallium (Ga (CH)3)3Or TMG) or triethyl gallium (Triethylgallium, Ga (C)2H5)3) With arsine (AsH)3) Interact to grow an epitaxial structure. The concentration, thickness and structure of the epitaxial structure can also be suitably controlled in this way. Compared with molecular beam epitaxy, the metal organic compound vapor phase deposition epitaxy equipment and the process are simpler, but the molecular beam epitaxy structure has higher quality.
Specifically, as shown in fig. 7, the method of specifically fabricating a gallium arsenide material or a gallium arsenide epitaxial structure 122 on a silicon substrate 121, that is, the step of forming a gallium arsenide crystal and a gallium arsenide epitaxial structure 122 on the silicon substrate 121, includes:
s221: cleaning the wafer;
s222: forming an arsenic pre-layer or a gallium pre-layer on a silicon substrate;
s223: carrying out initial nucleation on the pre-layer;
s224: heating to form gallium arsenide crystal;
s225: forming a gallium arsenide epitaxial structure on the gallium arsenide crystal;
in this embodiment, the formed gallium arsenide crystal is a gallium arsenide single crystal, which can be used as the gallium arsenide epitaxial structure 122, or can be used as a substrate of the gallium arsenide epitaxial structure 122, as shown in fig. 8, which is a schematic diagram of the gallium arsenide epitaxial structure 122 on a silicon substrate 121. Namely, the gallium arsenide epitaxial structure 122 obtained by the above-described method through the step of forming the gallium arsenide crystal and the gallium arsenide epitaxial structure 122 on the silicon substrate 121. More specifically, the method comprises the following steps: the surface of the silicon wafer 110 is cleaned to remove any particles or organic contaminants on the surface of the wafer 110, and the cleaning method includes a chemical method and a thermal cleaning method. A pre-layer of Ga or As is produced, which is the first atomic layer of Ga or As grown on the silicon surface. The temperature is between 30 and 400 ℃. The thickness of the pre-layer is between 2-10 monoatomic layers (monolayers), or 0.5-5 nm. The growth method of the pre-layer may be MBE (molecular beam epitaxy), MOCVD (metal organic chemical vapor deposition), or ALE (atomic layer epitaxy). GaAs Nucleation can be carried out in MBE (molecular beam epitaxy) and MOCVD (metal organic chemical vapor deposition) equipment at a low temperature (30-600 ℃) and with a thickness of 5-100 nm. The growth rate is between 0.1-0.3 um/hr. And (3) manufacturing a GaAs layer: the temperature is raised to the normal GaAs growth temperature, 600-1000C, and a GaAs layer with the thickness of 1-3um is manufactured by using an MBE or MOCVD method. In the present embodiment, in order to improve the quality of the GaAs crystal formed on the silicon substrate 121, the following methods may be adopted, for example: ensuring the cleanness of the silicon surface; such that the dislocation of the silicon substrate 121 is oriented; real-time thermal cleaning of the wafer 110; the type and quality of the pre-layer; controlling the growth temperature and the growth rate in the equipment; and performing an on-line annealing process.
On the basis of GaAs crystal thin films, epitaxial structures 122 meeting different requirements can be fabricated, as shown in fig. 9, which is a schematic diagram of a basic GaAs pHEMT (GaAs high electron mobility transistor) epitaxial structure 122; the gallium arsenide epitaxial structure 122 includes: channel layer 1224, barrier layer 1226, and cap layer 1227; the channel layer 1224 is disposed on the silicon substrate 121; the barrier layer 1226 is disposed on the channel layer 1224; the cap layer 1227 is disposed on the barrier layer 1226. In a corresponding method, the step of forming the gallium arsenide epitaxial structure 122 on the silicon substrate 121 corresponding to the gallium arsenide device region 124a includes: forming a channel layer 1224 on the silicon substrate 121; forming a barrier layer 1226 on the channel layer 1224; a cap layer 1227 is formed on the barrier layer 1226.
A more complex GaAs pHEMT epitaxial structure 122 is shown in fig. 10; the epitaxial structure 122 is a schematic view of another epitaxial structure 122, a Channel layer 1224 (Channel) is disposed in the epitaxial structure 122, the Channel layer 1224 is made of gallium arsenide or indium gallium arsenide material, and the thickness is generally 10nm-1 um; above the channel is a Barrier layer 1226(Barrier) that forms a heterojunction with the channel layer 1224 and produces a high mobility two-dimensional electron gas (2DEG), the Barrier layer 1226 may be comprised of an n-type doped AlGaAs material with a thickness between 10-50 nm; the barrier layer 1226 is provided to supply free electrons to the interface and restrict upward movement of electrons. Between the channel layer 1224 and the barrier layer 1226, a thin second Spacer layer 1225 (Spacer) may also be interposed, which may restrict the upward movement of free electrons to further increase the concentration of the two-dimensional electron gas; the second spacer layer 1225 is typically undoped AlGaAs, 5-25nm thick; the barrier layer 1226 may also have a doped Cap layer 1227(Cap layer), such as n-type doped GaAs, with a thickness of 10-50nm, over the barrier layer 1226, the Cap layer 1227 protecting the barrier layer 1226 and reducing ohmic contact resistance by high doping. In addition, before the channel layer 1224 is fabricated, a buffer layer 1221 may be formed on the substrate to improve the quality of the epitaxial structure 122, where the buffer layer 1221 may be made of GaAs and may have a thickness of 0.5-2 um; a buffer layer 1221, a superlattice layer 1222, and a first spacer layer 1223 may be sequentially added between the silicon substrate and the channel layer 1224, the second spacer layer 1223 typically being undoped AlGaAs with a thickness of 5-25 nm.
As shown in fig. 11, the wafer 110 may be divided into two or more regions by the method of fig. 2 or 4; which may be divided into a gaas device region 124a and a si device region 125a, the gaas device region 124a may be used to fabricate a variety of devices based on gaas epitaxial structure 122, such as HBTs, HEMTs, VCSELs, LDs, etc.; a single chip may be integrated with the silicon semiconductor or the like of the silicon device region 125 a. The integration level and the overall performance of the device are improved. The two are integrated on the same chip, so that the area of the chip is reduced, the integration level is increased, the manufacturing cost is reduced, and the overall performance of the device is improved. The input matching circuit, the output matching circuit, or both may also be fabricated on the same chip. The integrated chip of the GaAs-based semiconductor transistors (HBT and HEMT) and the matching circuit is referred to as GaAs MMIC (monolithic integrated circuit). As shown in fig. 16, a wafer 110 is disclosed, and the integrated chips are fabricated on the wafer 110. Therefore, multifunctional devices (a GaAs transistor, a Si CMOS control circuit and an input-output matching circuit) can be integrated on the same chip, the integration level and performance of the low-noise amplifier are improved, the loss is reduced, and the cost is reduced.
As shown in fig. 14-20, as another embodiment of the present application, an integrated circuit is disclosed, which includes a wafer 110 and integrated chips 120, wherein the integrated chips 120 are disposed on the wafer 110. The integrated chip 120 includes: a silicon substrate 121, a silicon semiconductor-based switch control circuit 150, a gallium arsenide epitaxial structure 122, and a gallium arsenide-based switch circuit 130, the silicon substrate 121 being divided into a silicon device region 125a and a gallium arsenide device region 124 a; the silicon semiconductor-based switch control circuit 150 is shown disposed on a silicon substrate 121, correspondingly disposed in the silicon device region 125 a; a gallium arsenide epitaxial structure 122 disposed on the silicon substrate 121, corresponding to the gallium arsenide device region 124 a; and gallium arsenide based switching circuitry 130 is shown disposed on gallium arsenide epitaxial structure 122; the silicon semiconductor based switch control circuit 150 is electrically connected to the gallium arsenide based switch circuit 130; the gallium arsenide based switching circuit 130 includes: gallium arsenide high electron mobility transistor 140.
The method can integrate multifunctional devices (GaAs transistor, Si CMOS control circuit and input/output matching circuit) on the same chip, and use the silicon substrate to replace GaAs as substrate material, thereby reducing the cost of raw materials; the advantages of a large silicon wafer (8-12 inches) can be utilized, and the manufacturing cost of the chip is reduced; in the manufacturing process, the planarization processes such as CMP (chemical mechanical polishing) and the like can be used, so that the process capability, the device performance and the reliability are improved; the chip can be integrated with various chips based on silicon semiconductors, the integration level and the comprehensive performance of the device are improved, and new functions are realized through integration; the consumption of gallium arsenide substrate materials is greatly reduced by using silicon as the substrate, the reduction amplitude is up to 70-90%, and the pollution risk of arsenic to the environment is greatly reduced. And the integration level and the performance of the low-noise amplifier are improved, the loss is reduced, and the cost is reduced.
As shown in fig. 13, the gallium arsenide based switching circuit 130 includes: a first transistor 131 and a second transistor 132; the output terminals of the first transistor 131 and the second transistor 132 are connected to a common port COM, the input terminal of the first transistor 131 is connected to a first input port IN1, the input terminal of the second transistor 132 is connected to a second input port IN2, and the control terminals of the first transistor 131 and the second transistor 132 are respectively connected to a silicon semiconductor-based switch control circuit.
Specifically, the gallium arsenide based switching circuit further comprises: a first resistor 133, a second resistor 134, a first capacitor 135 and a second capacitor 136; the first resistor 133 is connected in series to the control terminal of the first transistor, one end of the first capacitor 135 is connected to the control terminal of the first transistor 131, and the other end is grounded; the second resistor 134 is connected in series to the control terminal of the second transistor 132, and one end of the second capacitor 136 is connected to the control terminal of the second transistor 132, and the other end is grounded.
Fig. 13 shows a schematic diagram of a gallium arsenide based switch circuit. The first transistor Q1 and the second transistor Q2 are two gallium arsenide high electron mobility transistors (GaAs pHEMT), Q1 and Q2 are controlled by two corresponding control voltages V1 and V2, respectively. When one of V1 or V2 is zero, the other is negative and below the pinch-off voltage of the transistor. Under such conditions, one of the inputs (port 1) is connected to the common port (COM) through the lower on-resistance of GaAs pHEMT, while the other input (port 2) is in pinch-off mode, isolated from the common port (COM) through the larger drain-source resistance value, thus achieving the switching function. The isolation value depends mainly on the finite resistance value between the drain and source of the HEMT. Some leakage of the radio frequency signal occurs through pinch-off transistors due to the presence of residual conductance. The isolation, insertion loss, switching time and power handling capability of the switch can be improved by improving the transistor design and process, and designing more complex circuits, which will not be described in detail here.
As shown in fig. 14, the silicon semiconductor-based switch control circuit 150 includes a Si CMOS inverter 151; the Si CMOS inverter 151 comprises an N-type MOS transistor 152 and a P-type MOS transistor 153; the source electrode of the N-type MOS tube 152 is connected to the drain electrode of the P-type MOS tube 153; the source of the P-type MOS transistor 153 is connected to a Vdd voltage; the control ends of the N-type MOS transistor 152 and the P-type MOS transistor 153 are connected to Vi, and the source electrode of the N-type MOS transistor 152 is connected to the drain electrode of the P-type MOS transistor 153 and is connected to Vo respectively.
The process for manufacturing the Si CMOS device in the silicon device area comprises the following steps: well and P-Well ion implantation/diffusion; formation of an Active Area (Active Area); manufacturing a grid; injecting/diffusing source and drain ions; contact hole fabrication (Contact Holes); a first layer of metal interconnects; multilayer metal interconnection; and manufacturing a passivation layer and a bonding pad (bonding pad). The completed inverter CMOS chip is shown in fig. 15. The above "CMOS process flow" is only an example, and does not represent the most advanced and comprehensive process method, and is not a limitation on the CMOS process.
As shown in fig. 16, which is a circuit diagram of the integration of a silicon semiconductor-based switch control circuit and a gallium arsenide-based switch circuit, V0 is connected to Q1, and other circuits are connected specifically to the designed lines; and will not be described in detail herein. Fig. 17 is a circuit diagram showing another silicon semiconductor-based switch control circuit and gallium arsenide-based switch circuit integration;
in view of the above, in the method for manufacturing the integrated chip, as shown in fig. 18, the step of forming the switch circuit based on gallium arsenide on the gallium arsenide epitaxial structure includes the steps of:
s301: forming a source electrode and a drain electrode on the gallium arsenide epitaxial structure;
s302: forming a first passivation layer on the source electrode and the drain electrode;
s303: etching the first passivation layer;
s304: forming a gate electrode so that the gate electrode is connected with the epitaxial structure;
s305: forming a second passivation layer on the first passivation layer;
s306: etching on the second passivation layer corresponding to the source and drain electrodes;
s307: forming a first metal layer;
s308: forming an inter-metal dielectric on the second passivation layer;
s309: forming a second metal layer on the inter-metal dielectric, wherein the second metal layer is connected with the first metal layer;
correspondingly, as shown in fig. 19, a schematic diagram of a gallium arsenide hemt 221 includes: a gate 1404, a source 1401, and a drain 1402 disposed over the epitaxial structure 122; a passivation layer disposed over the gate electrode 1404, the source electrode 1401, and the drain electrode 1402; a first metal layer 1406 disposed over the passivation layer, connected to the source 1401 and the drain 1402; a second metal layer 1407 connected to the first metal layer 1406 and disposed above the first metal layer 1406. The passivation layer may be divided into a first passivation layer 1403 and a second passivation layer 1405, the first passivation layer 1403 is processed before the gate is formed, and the gate is formed at the position of the gate by etching away the first passivation layer at the corresponding position. A second metal layer is formed on inter-metal dielectric 1408 and in the gallium arsenide hemt, the substrate is comprised of a silicon substrate material, which may be between 50-150mm in size or larger. The epitaxial structure is mainly composed of gallium arsenide material; the source electrode and the drain electrode can be made of one metal of Ti, Al, Ni or Au, or can be made of alloy formed by combining several metals through high-temperature annealing, so that the resistance can be further reduced; the gate may be made of metal such as Ni, Au, Pt, Ti, and Al, and the cross-sectional shape of the gate may be rectangular, or "T" or "Y", and the like, which is not limited herein; the material of the first passivation layer and the second passivation layer may be silicon nitride (Si)3N4) Or silicon oxide (SiO)2) And the like. The gallium arsenide epitaxial structure comprises: a buffer layer disposed on the silicon substrate; a superlattice layer disposed on the buffer layer; a first isolation layer disposed on the superlattice layer; a channel layer disposed on the first isolation layer; a second isolation layer disposed on the channel layer; a barrier layer disposed on the second spacerSeparating layer; a cap layer disposed on the barrier layer.
Another method for manufacturing the gaas hemt of fig. 18 is: forming a substrate or wafer; forming a source electrode and a drain electrode on the epitaxial structure; forming a first passivation layer on the source electrode and the drain electrode; etching the first passivation layer; then forming a grid electrode, so that the grid electrode is connected with the epitaxial structure; forming a second passivation layer on the first passivation layer; etching on the second passivation layer corresponding to the source and drain electrodes; then forming a first metal layer; forming an inter-metal dielectric on the second passivation layer; a second metal layer is formed on the inter-metal dielectric, and the second metal layer is connected to the first metal layer. More metal layers, passivation layers, dielectric layers and the like can be arranged in the device according to the needs. The front side is the front side process of the substrate, and Wafer bonding (Wafer bonding) can be performed on the back side of the substrate; then thinning and polishing the wafer; then, carrying out back hole etching (backside via etch) to etch back holes penetrating through the wafer and the epitaxial structure; and then performing via metallization (via metallization), namely forming a back metal layer on the back surface of the wafer, so that the back metal layer is connected with the source electrode through the back hole.
Because gallium arsenide has the advantages of good frequency response, high speed, high working temperature and the like, the power amplifier 111 or other structures based on the gallium arsenide high electron mobility transistor 221(GaAs pHEMT) can bring better performance to the chip, and will be more and more widely applied to 5G and future communications, including wireless base stations, mobile phones, intelligent terminals, WIFI and other devices, and places such as satellite communications, microwave point-to-point connections, radar systems and the like.
It should be noted that, the limitations of each step in the present disclosure are not considered to limit the order of the steps without affecting the implementation of the specific embodiments, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all the steps should be considered as belonging to the protection scope of the present application.
It should be noted that the inventive concept of the present application can form many embodiments, but the present application has a limited space and cannot be listed one by one, so that, on the premise of no conflict, any combination between the above-described embodiments or technical features can form a new embodiment, and after the embodiments or technical features are combined, the original technical effect will be enhanced
The technical scheme of the application can be widely applied to the integration of various chips based on silicon-based and gallium arsenide, except the silicon-based devices and the gallium arsenide devices. Other silicon-based and gallium arsenide based chip integrations may be suitable for this scheme.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (10)
1. An integrated chip, comprising:
a silicon substrate divided into a silicon device region and a gallium arsenide device region;
the switch control circuit based on the silicon semiconductor is arranged on the silicon substrate and correspondingly arranged in the silicon device area;
the gallium arsenide epitaxial structure is arranged on the silicon substrate and corresponds to the gallium arsenide device region; and
the switch circuit based on gallium arsenide is arranged on the gallium arsenide epitaxial structure;
wherein the silicon semiconductor based switch control circuit is electrically connected to the gallium arsenide based switch circuit; the gallium arsenide based switching circuit includes gallium arsenide high electron mobility transistors.
2. The integrated chip of claim 1, wherein the gallium arsenide based switching circuit comprises: the switch control circuit comprises a first transistor and a second transistor, wherein output ends of the first transistor and the second transistor are connected to a common port, an input end of the first transistor is connected to a first input port, an input end of the second transistor is connected to a second input port, and control ends of the first transistor and the second transistor are respectively connected to a silicon semiconductor-based switch control circuit.
3. The integrated chip of claim 2, wherein the gallium arsenide based switching circuit further comprises: the circuit comprises a first resistor, a second resistor, a first capacitor and a second capacitor; the first resistor is connected to the control end of the first transistor in series, one end of the first capacitor is connected to the control end of the first transistor, and the other end of the first capacitor is grounded;
the second resistor is connected in series to the control end of the second transistor, one end of the second capacitor is connected to the control end of the second transistor, and the other end of the second capacitor is grounded.
4. An integrated chip according to claim 2, wherein the silicon semiconductor based switch control circuit comprises a SiCMOS inverter; the SiCMOS inverter comprises an N-type MOS tube and a P-type MOS tube; the source electrode of the N-type MOS tube is connected to the drain electrode of the P-type MOS tube;
the first transistor and the second transistor are gallium arsenide high electron mobility transistors respectively;
the gallium arsenide high electron mobility transistor includes:
the grid electrode, the source electrode and the drain electrode are arranged above the epitaxial structure;
a passivation layer disposed over the gate electrode, the source electrode and the drain electrode;
the first metal layer is arranged above the passivation layer and is connected with the source electrode and the drain electrode;
and the second metal layer is connected with the first metal layer and is arranged above the first metal layer.
5. The integrated chip of claim 1, wherein the gallium arsenide epitaxial structure comprises:
a buffer layer disposed on the silicon substrate;
a superlattice layer disposed on the buffer layer;
a first isolation layer disposed on the superlattice layer;
a channel layer disposed on the first isolation layer;
a second isolation layer disposed on the channel layer;
a barrier layer disposed on the second isolation layer; and
a cap layer disposed on the barrier layer.
6. A method for manufacturing an integrated chip is characterized by comprising the following steps:
dividing a silicon device region and a gallium arsenide device region on a silicon substrate;
forming a gallium arsenide epitaxial structure on the silicon substrate corresponding to the gallium arsenide device region;
forming a gallium arsenide-based switching circuit on the gallium arsenide epitaxial structure;
forming a silicon semiconductor-based switch control circuit in a silicon device region corresponding to a silicon substrate; and
forming a metal interconnect layer between the gallium arsenide based switch circuitry and the silicon semiconductor based switch control circuitry;
wherein the gallium arsenide based switching circuit comprises a gallium arsenide high electron mobility transistor.
7. The method of claim 6, wherein the step of forming the GaAs based switch circuit on the GaAs epitaxial structure comprises the steps of:
forming a source electrode and a drain electrode on the gallium arsenide epitaxial structure;
forming a first passivation layer on the source electrode and the drain electrode;
etching the first passivation layer;
forming a gate electrode so that the gate electrode is connected with the epitaxial structure;
forming a second passivation layer on the first passivation layer;
etching on the second passivation layer corresponding to the source and drain electrodes;
forming a first metal layer;
forming an inter-metal dielectric on the second passivation layer; and
a second metal layer is formed on the inter-metal dielectric, and the second metal layer is connected to the first metal layer.
8. The method of claim 6, wherein the step of forming the GaAs epitaxial structure on the GaAs device region corresponding to the silicon substrate comprises:
forming a gallium arsenide epitaxial structure on a silicon substrate; and
removing the gallium arsenide epitaxial structure in the silicon device region by wet etching or dry etching; and keeping a gallium arsenide epitaxial structure on the gallium arsenide device region.
9. The method of claim 6, wherein the step of forming the GaAs epitaxial structure on the Si substrate corresponding to the GaAs device region comprises:
forming a layer of silicon oxide or silicon nitride on a silicon substrate;
removing silicon oxide or silicon nitride in the gallium arsenide device region by etching;
forming a gallium arsenide epitaxial structure corresponding to the gallium arsenide device region on the silicon substrate; and
and removing the silicon oxide or the silicon nitride in the silicon device area.
10. An integrated circuit comprising a wafer and an integrated chip according to any of claims 1-5, the integrated chip being disposed on the wafer.
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