CN113782438A - Method for improving performance of FinFET device - Google Patents
Method for improving performance of FinFET device Download PDFInfo
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- CN113782438A CN113782438A CN202110973279.1A CN202110973279A CN113782438A CN 113782438 A CN113782438 A CN 113782438A CN 202110973279 A CN202110973279 A CN 202110973279A CN 113782438 A CN113782438 A CN 113782438A
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- groove
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 81
- 239000011241 protective layer Substances 0.000 claims abstract description 55
- 239000002184 metal Substances 0.000 claims abstract description 51
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 25
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 12
- 238000002161 passivation Methods 0.000 description 8
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 206010010144 Completed suicide Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention provides a method for improving the performance of a FinFET device, wherein a first protective layer is formed on a Fin structure and a gate structure; forming a second protective layer to cover the second Fin structure; removing the first Fin structure to form a first groove; widening the first groove, and forming an NMOS epitaxial structure in the first groove; covering a third protective layer on the Fin structure and the gate structure; forming a fourth protective layer to cover the first Fin structure; removing the second Fin structure to form a second groove, and widening the second groove; forming a PMOS epitaxial structure in the second groove; forming an HK metal gate; a layer of metal silicide is formed. The embedded epitaxial structure is limited by the protective layer, so that epitaxial merging cannot occur; the side wall of the Fin structure is widened for enlarging the volume of the epitaxial structure, so that the external resistance can be effectively reduced; forming metal silicide on the epitaxial structure to further reduce external resistance; the formation of the contact line on the metal silicide can reduce the parasitic fringe capacitance between the grid and the contact hole and better realize the alternating current performance.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving the performance of a FinFET device.
Background
With the technical node exceeding 14nm, the proportion of the external resistance in the total resistance is larger and larger, and the performance of the device is governed by the external resistance; therefore, it is required to reduce the external resistance, and the deep epitaxial layer and the large volume epitaxial layer are effective ways to reduce the external resistance. While increasing the contact area is an effective way to reduce the external resistance, if the epitaxial layer grows too large, epitaxial merging occurs and the contact area is not further increased.
Therefore, a new method is needed to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a method for improving the performance of a FinFET device, which is used to solve the problem of how to reduce the external resistance during the fabrication of the FinFET device structure in the prior art.
To achieve the above and other related objects, the present invention provides a method for improving performance of a FinFET device, comprising the steps of: the device comprises a plurality of Fin structures which are longitudinally arranged on a substrate at intervals, wherein thin oxide layers cover the outer surfaces of the Fin structures; the STI region is positioned outside the thin oxide layer and is filled between the adjacent Fin structures; the height of the upper surface of the STI region is lower than that of the top of the Fin structure, and a plurality of gate structures which are arranged at intervals transversely are formed on the substrate and on the thin oxide layer on the outer surfaces of the Fin structures which are arranged at intervals longitudinally; the gate structure comprises a polysilicon layer; the plurality of Fin structures include a first Fin structure functioning as an NMOS and a second Fin structure adjacent to the first Fin structure functioning as a PMOS;
depositing a first protective layer covering the outer surface of the Fin structure and the outer surface of the gate structure;
step three, forming a second protective layer to cover the outer surface of the second Fin structure;
removing the part, higher than the upper surface of the STI region, of the first Fin structure to form a first groove;
etching the silicon on the side wall of the first groove, widening the first groove for the first time, and exposing the thin oxide layer on the side wall of the first groove;
sixthly, etching to remove the thin oxide layer on the side wall of the first groove, widening the first groove for the second time, and exposing the first protective layer on the side wall of the first groove;
seventhly, etching to remove the first protective layer on the side wall of the first groove, and widening the first groove for the third time;
step eight, forming an NMOS epitaxial structure in the first groove;
ninthly, removing the first protective layer and the second protective layer, and covering a third protective layer on the outer surface of the Fin structure and the outer surface of the gate structure;
step ten, forming a fourth protective layer to cover the outer surface of the first Fin structure;
step eleven, etching and removing parts, higher than the upper surface of the STI region, in the second Fin structure in sequence to form a second groove, then etching and removing silicon, a thin oxide layer and the third protective layer on the side wall of the second groove in sequence, and widening the second groove;
step twelve, forming a PMOS epitaxial structure in the second groove;
thirteen, removing the third and fourth protective layers;
fourteen, covering ILD layers on the outer surface of the Fin structure and the outer surface of the gate structure; the ILD layer is filled in the space between the gate structures;
step fifteen, opening the gate structure, removing the polycrystalline silicon in the gate structure and forming an HK metal gate;
sixthly, removing the ILD layer, and then covering a metal layer, wherein the metal layer respectively reacts with the NMOS epitaxial structure and the PMOS epitaxial structure to form a layer of metal silicide;
seventhly, removing the residual metal layer after the reaction;
eighteen, forming a contact groove on the side wall of the HK metal gate above the metal silicide;
nineteen, forming a contact line connected with the metal silicide in the contact groove.
Preferably, in the third step, a second protective layer is formed on the outer surface of the second Fin structure, and the first protective layer on the outer surface of the gate structure along the lateral region of the first Fin structure is exposed.
Preferably, in the fourth step, a silicon etching method is used to remove a portion of the first Fin structure, which is higher than the upper surface of the STI region.
Preferably, in the step eight, the NMOS epitaxial structure is formed in the first recess by growing an epitaxial layer.
Preferably, while the fourth protective layer is formed in the tenth step to cover the outer surface of the first Fin structure, the gate structure in the lateral direction of the first Fin structure is also covered by the fourth protective layer.
As described above, the method for improving the performance of the FinFET device of the present invention has the following beneficial effects: the embedded epitaxial structure is limited by the protective layer, so that epitaxial merging cannot occur; before the epitaxial structure grows, the side wall of the Fin structure is widened to enlarge the volume of the epitaxial structure, so that the external resistance can be effectively reduced; meanwhile, the invention forms metal silicide on the epitaxial structure to further reduce the external resistance; the contact line formed on the metal silicide can reduce the parasitic fringe capacitance between the grid and the contact hole, and better realize the alternating current performance.
Drawings
Fig. 1 shows a schematic diagram of a FinFET device structure at step one in the present invention;
FIG. 2 is a schematic structural diagram of the present invention after a second passivation layer is formed;
FIG. 3 is a schematic structural diagram of the first Fin structure after removing a portion of the first Fin structure above the upper surface of the STI region;
FIG. 4 is a schematic structural view of the first groove after being widened for the first time in the present invention;
FIG. 5 is a schematic structural view of the first groove after the second widening;
FIG. 6 is a schematic structural view of the first groove after the third widening;
FIG. 7 is a schematic diagram illustrating a structure of the NMOS epitaxial structure formed in the first recess according to the present invention;
FIG. 8 is a schematic structural view of the present invention after removing the first and second passivation layers;
FIG. 9 is a schematic view showing a structure after a third protective layer and a fourth protective layer are formed in the present invention;
FIG. 10 is a schematic diagram illustrating a PMOS epitaxial structure formed in a second recess according to the present invention;
FIG. 11 is a schematic diagram of the structure of the present invention after forming an ILD layer and an HK metal gate;
FIG. 12 is a schematic view of a structure after forming a metal silicide according to the present invention;
FIG. 13 is a schematic view of the structure of the present invention after removing the metal layer to expose the metal silicide;
FIG. 14 is a schematic view of the structure of the present invention after forming a contact trench;
fig. 15 is a schematic structural diagram of a contact line formed in a contact trench to connect metal silicide according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 15. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The invention provides a method for improving the performance of a FinFET device, which at least comprises the following steps:
step one, providing a FinFET device structure, wherein the FinFET device structure at least comprises: the device comprises a plurality of Fin structures which are longitudinally arranged on a substrate at intervals, wherein thin oxide layers cover the outer surfaces of the Fin structures; the STI region is positioned outside the thin oxide layer and is filled between the adjacent Fin structures; the height of the upper surface of the STI region is lower than that of the top of the Fin structure, and a plurality of gate structures which are arranged at intervals transversely are formed on the substrate and on the thin oxide layer on the outer surfaces of the Fin structures which are arranged at intervals longitudinally; the gate structure comprises a polysilicon layer; the plurality of Fin structures include a first Fin structure functioning as an NMOS and a second Fin structure adjacent to the first Fin structure functioning as a PMOS; as shown in fig. 1, fig. 1 shows a schematic diagram of a FinFET device in step one of the present invention. The FinFET device structure of this step one includes in this embodiment: the device comprises a plurality of Fin structures 01 which are longitudinally arranged on a substrate at intervals, wherein thin oxide layers cover the outer surfaces of the Fin structures 01; the STI regions 04 are positioned outside the thin oxide layer and filled between the adjacent Fin structures 01; the height of the upper surface of the STI region 04 is lower than that of the top of the Fin structure 01, and a plurality of gate structures 02 which are arranged on the substrate at intervals transversely are formed on the thin oxide layer on the outer surfaces of the plurality of Fin structures which are arranged at intervals longitudinally; the gate structure 02 comprises a polysilicon layer; the plurality of Fin structures include a first Fin structure functioning as an NMOS and a second Fin structure functioning as a PMOS adjacent to the first Fin structure. For example, in fig. 1, the Fin structure on the left side is the first Fin structure; the Fin structure on the right side is the second Fin structure.
Depositing a first protective layer covering the outer surface of the Fin structure and the outer surface of the gate structure; as shown in fig. 1, in the second step, a first protective layer 03 is deposited to cover the outer surface of the Fin structure 01 and the outer surface of the gate structure 02.
Step three, forming a second protective layer to cover the outer surface of the second Fin structure; as shown in fig. 2, fig. 2 is a schematic structural diagram after a second passivation layer is formed in the present invention, and a second passivation layer 05 is formed in the third step to cover the outer surface of the second Fin structure.
Further, in the third step of this embodiment, while forming the second passivation layer 05 on the outer surface of the second Fin structure, the first Fin structure and the first passivation layer 03 on the outer surface of the gate structure 02 along the lateral region thereof are exposed.
Removing the part, higher than the upper surface of the STI region, of the first Fin structure to form a first groove; as shown in fig. 3, fig. 3 is a schematic structural view illustrating the first Fin structure after removing a portion of the first Fin structure above the upper surface of the STI region. In the fourth step, the part of the first Fin structure, which is higher than the upper surface of the STI region 04, is removed to form a first groove 06.
Furthermore, in the fourth step of this embodiment, a silicon etching method is used to remove a portion of the first Fin structure, which is higher than the upper surface of the STI region 04.
Etching the silicon on the side wall of the first groove, widening the first groove for the first time, and exposing the thin oxide layer on the side wall of the first groove; as shown in fig. 4, fig. 4 is a schematic structural view of the first groove after being widened for the first time in the present invention. In the fifth step, the silicon on the side wall of the first groove 06 is etched, the first groove 06 is widened for the first time, and the thin oxide layer on the side wall of the first groove 06 is exposed.
Sixthly, etching to remove the thin oxide layer on the side wall of the first groove, widening the first groove for the second time, and exposing the first protective layer on the side wall of the first groove; as shown in fig. 5, fig. 5 is a schematic structural view of the first groove after the second widening. In the sixth step, the thin oxide layer on the sidewall of the first groove 06 is etched and removed, the first groove 06 is widened for the second time, and meanwhile, the first protective layer 03 on the sidewall of the first groove 06 is exposed.
Seventhly, etching to remove the first protective layer on the side wall of the first groove, and widening the first groove for the third time; as shown in fig. 6, fig. 6 is a schematic structural view of the first groove after the first groove is widened for the third time in the present invention. And seventhly, etching to remove the first protective layer on the side wall of the first groove 06, and widening the first groove for the third time.
Step eight, forming an NMOS epitaxial structure in the first groove; as shown in fig. 7, fig. 7 is a schematic structural diagram of the NMOS epitaxial structure formed in the first recess according to the present invention. In this step eight, an NMOS epitaxial structure 07 is formed in the first recess.
Further, in step eight of this embodiment, the NMOS epitaxial structure is formed in the first recess by growing an epitaxial layer.
Ninthly, removing the first protective layer and the second protective layer, and covering a third protective layer on the outer surface of the Fin structure and the outer surface of the gate structure; as shown in fig. 8, fig. 8 is a schematic structural view of the present invention after removing the first and second passivation layers. As shown in fig. 9, fig. 9 is a schematic structural view after forming a third protective layer and a fourth protective layer in the present invention. In the ninth step, the first and second protective layers are removed, and a third protective layer 09 covers the outer surface of the Fin structure and the outer surface of the gate structure.
Step ten, forming a fourth protective layer to cover the outer surface of the first Fin structure; as shown in fig. 9, a fourth protective layer 10 is formed in this step ten to cover the outer surface of the first Fin structure.
Further, in the present invention, in the tenth step of this embodiment, while a fourth protection layer 10 is formed to cover the outer surface of the first Fin structure, the gate structure along the lateral direction of the first Fin structure is also covered by the fourth protection layer 10.
Step eleven, etching and removing parts, higher than the upper surface of the STI region, in the second Fin structure in sequence to form a second groove, then etching and removing silicon, a thin oxide layer and the third protective layer on the side wall of the second groove in sequence, and widening the second groove; as shown in fig. 9, in the eleventh step, a second groove 11 is formed in a portion of the second Fin structure, which is higher than the upper surface of the STI region, and then the silicon, the thin oxide layer, and the third protective layer on the sidewall of the second groove are etched and removed in sequence, so that the second groove is widened.
Step twelve, forming a PMOS epitaxial structure in the second groove; as shown in fig. 10, fig. 10 is a schematic structural view of the PMOS epitaxial structure formed in the second recess according to the present invention. A PMOS epitaxial structure 12 is formed in the second recess 11 in this twelfth step.
Thirteen, removing the third and fourth protective layers; as shown in fig. 10, after the third and fourth passivation layers are removed in the thirteenth step, the thin oxide layer 08 is exposed.
Fourteen, covering ILD layers on the outer surface of the Fin structure and the outer surface of the gate structure; the ILD layer is filled in the space between the gate structures; as shown in fig. 11, fig. 11 is a schematic structural diagram after forming an ILD layer and an HK metal gate in the present invention. In the fourteenth step, an ILD layer (interlayer dielectric layer) 13 covers the outer surface of the Fin structure and the outer surface of the gate structure; the ILD layer fills spaces between the gate structures.
Step fifteen, opening the gate structure, removing the polycrystalline silicon in the gate structure and forming an HK metal gate; as shown in fig. 11, in this step fifteen, the gate structure is opened, and after the polysilicon is removed, the HK metal gate 14 is formed.
Sixthly, removing the ILD layers on the PMOS epitaxial structure and the NMOS epitaxial structure, and then covering a metal layer, wherein the metal layer respectively reacts with the NMOS epitaxial structure and the PMOS epitaxial structure to form a layer of metal silicide; as shown in fig. 12, fig. 12 is a schematic structural view after forming a metal silicide according to the present invention. Sixthly, removing the ILD layers on the PMOS epitaxial structure and the NMOS epitaxial structure, and then covering a metal layer 15, wherein the metal layer reacts with the NMOS epitaxial structure and the PMOS epitaxial structure respectively to form a layer of metal silicide.
Seventhly, removing the residual metal layer after the reaction; as shown in fig. 13, fig. 13 is a schematic structural view of the present invention after removing the metal layer to expose the metal silicide. Seventhly, removing the residual metal layer after the reaction, and forming a layer of metal silicide 17 on the tops of the NMOS epitaxial structure and the PMOS epitaxial structure.
Eighteen, forming a contact groove on the side wall of the HK metal gate above the metal silicide; as shown in fig. 14, fig. 14 is a schematic structural view after forming a contact trench in the present invention. This step eighteen forms contact trenches 18 in the sidewalls of the HK metal gate above the metal silicide.
Nineteen, forming a contact line connected with the metal silicide in the contact groove. As shown in fig. 15, fig. 15 is a schematic structural diagram illustrating the formation of a contact line connecting metal silicide in a contact trench according to the present invention. In this step nineteen contact lines 19 are formed in the contact trenches connecting the metal suicide.
In summary, the embedded epitaxial structure in the present invention is limited by the protection layer, so that epitaxial merging does not occur; before the epitaxial structure grows, the side wall of the Fin structure is widened to enlarge the volume of the epitaxial structure, so that the external resistance can be effectively reduced; meanwhile, the invention forms metal silicide on the epitaxial structure to further reduce the external resistance; the contact line formed on the metal silicide can reduce the parasitic fringe capacitance between the grid and the contact hole, and better realize the alternating current performance. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (5)
1. A method of improving performance of a FinFET device, comprising:
step one, providing a FinFET device structure, wherein the FinFET device structure at least comprises: the device comprises a plurality of Fin structures which are longitudinally arranged on a substrate at intervals, wherein thin oxide layers cover the outer surfaces of the Fin structures; the STI region is positioned outside the thin oxide layer and is filled between the adjacent Fin structures; the height of the upper surface of the STI region is lower than that of the top of the Fin structure, and a plurality of gate structures which are arranged at intervals transversely are formed on the substrate and on the thin oxide layer on the outer surfaces of the Fin structures which are arranged at intervals longitudinally; the gate structure comprises a polysilicon layer; the plurality of Fin structures include a first Fin structure functioning as an NMOS and a second Fin structure adjacent to the first Fin structure functioning as a PMOS;
depositing a first protective layer covering the outer surface of the Fin structure and the outer surface of the gate structure;
step three, forming a second protective layer to cover the outer surface of the second Fin structure;
removing the part, higher than the upper surface of the STI region, of the first Fin structure to form a first groove;
etching the silicon on the side wall of the first groove, widening the first groove for the first time, and exposing the thin oxide layer on the side wall of the first groove;
sixthly, etching to remove the thin oxide layer on the side wall of the first groove, widening the first groove for the second time, and exposing the first protective layer on the side wall of the first groove;
seventhly, etching to remove the first protective layer on the side wall of the first groove, and widening the first groove for the third time;
step eight, forming an NMOS epitaxial structure in the first groove;
ninthly, removing the first protective layer and the second protective layer, and covering a third protective layer on the outer surface of the Fin structure and the outer surface of the gate structure;
step ten, forming a fourth protective layer to cover the outer surface of the first Fin structure;
step eleven, etching and removing parts, higher than the upper surface of the STI region, in the second Fin structure in sequence to form a second groove, then etching and removing silicon, a thin oxide layer and the third protective layer on the side wall of the second groove in sequence, and widening the second groove;
step twelve, forming a PMOS epitaxial structure in the second groove;
thirteen, removing the third and fourth protective layers;
fourteen, covering ILD layers on the outer surface of the Fin structure and the outer surface of the gate structure; the ILD layer is filled in the space between the gate structures;
step fifteen, opening the gate structure, removing the polycrystalline silicon in the gate structure and forming an HK metal gate;
sixthly, removing the ILD layers on the PMOS epitaxial structure and the NMOS epitaxial structure, and then covering a metal layer, wherein the metal layer respectively reacts with the NMOS epitaxial structure and the PMOS epitaxial structure to form a layer of metal silicide;
seventhly, removing the residual metal layer after the reaction;
eighteen, forming a contact groove on the side wall of the HK metal gate above the metal silicide;
nineteen, forming a contact line connected with the metal silicide in the contact groove.
2. The method of claim 1, wherein the FinFET device performance is improved by: and step three, forming a second protective layer on the outer surface of the second Fin structure, and simultaneously exposing the first protective layer on the outer surface of the first Fin structure and the gate structure along the transverse area of the first Fin structure.
3. The method of claim 1, wherein the FinFET device performance is improved by: and step four, removing the part of the first Fin structure, which is higher than the upper surface of the STI region, by using a silicon etching method.
4. The method of claim 1, wherein the FinFET device performance is improved by: and step eight, forming the NMOS epitaxial structure in the first groove by a method of growing an epitaxial layer.
5. The method of claim 1, wherein the FinFET device performance is improved by: and step ten, forming a fourth protective layer to cover the outer surface of the first Fin structure, wherein the gate structure along the transverse direction of the first Fin structure is also covered by the fourth protective layer.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109300845A (en) * | 2017-07-25 | 2019-02-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109427678A (en) * | 2017-08-24 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US20210234047A1 (en) * | 2020-01-24 | 2021-07-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Leakage Prevention Structure And Method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109300845A (en) * | 2017-07-25 | 2019-02-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109427678A (en) * | 2017-08-24 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US20210234047A1 (en) * | 2020-01-24 | 2021-07-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Leakage Prevention Structure And Method |
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