CN113782427A - Process method for etching high depth-width ratio groove - Google Patents
Process method for etching high depth-width ratio groove Download PDFInfo
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- CN113782427A CN113782427A CN202111011360.8A CN202111011360A CN113782427A CN 113782427 A CN113782427 A CN 113782427A CN 202111011360 A CN202111011360 A CN 202111011360A CN 113782427 A CN113782427 A CN 113782427A
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- 238000005530 etching Methods 0.000 title claims abstract description 98
- 238000000034 method Methods 0.000 title claims abstract description 46
- 230000008569 process Effects 0.000 title claims abstract description 35
- 229920000642 polymer Polymers 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000000460 chlorine Substances 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims abstract description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052801 chlorine Inorganic materials 0.000 claims abstract description 4
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 4
- 239000011737 fluorine Substances 0.000 claims abstract description 4
- 239000007789 gas Substances 0.000 claims description 64
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 239000003085 diluting agent Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 230000006872 improvement Effects 0.000 description 7
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000000877 morphologic effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a process method for etching a high-aspect-ratio groove, which is characterized in that when etching gas is introduced into a semiconductor substrate to etch to form a deep groove, a polymer introduced with fluorine-based or chlorine-based gas generates gas, and the flow of the etching gas is gradually increased or the flow of the gas generating the polymer is gradually reduced along with the continuous etching to reduce the generation of the polymer; or both may be performed simultaneously; the formation of different trench profiles is controlled by the gradual control of the rate of etching gas and/or polymer generation gas.
Description
Technical Field
The invention relates to the field of semiconductor device design and manufacture, in particular to a process method for etching a high-aspect-ratio groove in a super junction device process.
Background
The super junction power device is a novel power semiconductor device which is developed rapidly and widely applied. The Super Junction structure is introduced on the basis of a double-Diffused Metal Oxide Semiconductor (DMOS), and the Super Junction structure has the characteristics of high DMOS input impedance, high switching speed, high working frequency, good thermal stability, simple driving circuit, easiness in integration and the like, and overcomes the defect that the on-resistance of the DMOS is increased along with the breakdown voltage in a 2.5-power relation. At present, super junction DMOS has been widely used as power supplies or adapters for personal computers, notebook computers, netbooks, mobile phones, lighting (high-pressure gas discharge lamp) products, and consumer electronics products such as televisions (liquid crystal or plasma televisions) and game machines.
The super junction device utilizes an N/P alternate arrangement structure to replace an N drift region in the traditional VDMOS, and combines with a VDMOS process known in the industry to manufacture the MOSFET with the super junction structure, and the on-resistance of the device can be greatly reduced by using an epitaxial layer with low resistivity under the conditions of reverse breakdown voltage and the traditional VDMOS. At present, a preparation process of a super junction power device is formed by etching a plurality of parallel grooves in an N-type epitaxial layer and then filling P-type epitaxial materials in the parallel grooves in a manner of deep groove etching and P-column filling, so as to form a structure of P, N, P, N which is alternately and repeatedly arranged. A MOSFET structure utilizing PN charge balance in-vivo Resurf technology to improve reverse BV breakdown of the device while maintaining a small on-resistance. With the gradual reduction of the size of the device, the difficulty of groove etching is gradually increased, and the groove with high aspect ratio can cause etching gas to be difficult to enter the bottom of the groove, so that the etching time is greatly increased, and simultaneously, the substrate material at the top is damaged to form a gap. In the case that the depth-to-width ratio of the groove exceeds 20 in the conventional etching menu, the finished groove top has obvious morphological defects and the top cross-cut is serious. As shown in fig. 1 and fig. 2, fig. 1 is a schematic cross-sectional view of a deep trench of a super junction device, and fig. 2 is a partially enlarged view of a top opening of the deep trench shown in fig. 1, as can be clearly shown by the partially enlarged view of fig. 2, a lateral undercut (undercut) phenomenon occurs at the deep trench opening under a hard mask layer or a photoresist, and the opening morphology of the trench is not good, which affects the device performance.
Disclosure of Invention
The invention aims to solve the technical problem of providing a process method for etching a high-aspect-ratio groove in a super junction device process.
In order to solve the problems, the process method for etching the high aspect ratio groove, provided by the invention, comprises the steps of introducing etching gas into a semiconductor substrate to etch to form a deep groove, introducing fluorine-based or chlorine-based gas into a polymer to generate gas, and gradually increasing the flow of the etching gas or gradually reducing the generation of the polymer along with the continuous etching; or both may be performed simultaneously; the formation of different trench profiles is controlled by the gradual control of the rate of etching gas and/or polymer generation gas.
In a further improvement, the semiconductor substrate is a silicon substrate.
In a further improvement, the etching gas at least contains Cl2、HBr、O2。
In a further improvement, the Cl2HBr gas is used as etching gas of silicon to etch the silicon substrate; o is2Mainly as a gas of polymer formation.
In a further improvement, the deep trench aspect ratio is greater than 20.
During normal etching, the depth of the groove is gradually increased along with the progress of the etching, the formed polymer is gradually accumulated, and the slope of the side wall of the groove is increased.
In a further refinement, the etching gas further comprises a diluent gas.
In a further improvement, the diluent gas is helium.
In a further improvement, the etching gas further comprises C2F6Etching silicon oxide and silicon nitrideAnd performing chamfer etching on the top of the deep trench.
The invention relates to a process method for etching a high-aspect-ratio groove, which mainly aims at substrate etching and is characterized in that when a deep groove with the aspect ratio larger than 20 is formed by etching a silicon substrate, the shape of the etched groove is further controlled by controlling and utilizing gradual change control of etching gas and polymer.
Drawings
FIG. 1 is a schematic diagram of a deep trench cross-sectional structure of a super junction device.
Fig. 2 is an enlarged view of a portion of the cross-sectional open area of the deep trench shown in fig. 1.
FIG. 3 is a cross-sectional view of a process state according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
When an element or layer is referred to herein as being "on …", "adjacent …", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
The invention relates to a process method for etching a high-aspect-ratio groove, which is characterized in that when etching gas is introduced into a semiconductor substrate to etch to form a deep groove, a polymer introduced with fluorine-based or chlorine-based gas generates gas, and the flow of the etching gas is gradually increased or the generation of the polymer is gradually reduced along with the continuous etching; or both may be performed simultaneously; the formation of different trench profiles is controlled by the gradual control of the rate of etching gas and/or polymer generation gas.
In one embodiment, a deep trench with an aspect ratio of more than 20 needs to be formed on a silicon substrate, and in a conventional process, polymer generated continuously during etching interferes with the deep etching of the trench.
In the invention, etching gas is introduced into the silicon substrate to mainly etch the silicon material, and the gas for silicon etching generally contains Cl2And HBr gas, which is the main gas for etching silicon material, by Cl2Reacting with HBr gas and silicon to etch away silicon of the substrate material to form deep trenches, O2As the generated gas of the polymer, as the etching progresses, the more the polymer is, the more the side walls of the formed trench have a certain inclination angle, a slope is formed, and finally a V-shaped trench is formed, which is not an ideal appearance that we want, and a U-shaped trench with steep side walls is needed in the deep trench etching. The flow of etching gas is controlled, and with the continuous increase of the etching depth of the groove, the etching amount of the lower part of the groove needs to be gradually increased, so that the problem that the deeper and the harder the groove is etched can be solved, and the etching gas of silicon is increasedThe flow can increase the etching amount of the lower part of the groove, and the compensation modification is carried out on the side wall of the groove with the inclined appearance, so that the appearance of the side wall of the groove is steeper. That is to say, the flow of the etching gas is gradually controlled to be gradually increased in the etching process of the whole groove, the etching rate of the lower part of the groove is accelerated, and the aim of correcting the side wall appearance of the groove is fulfilled.
In addition, because the etching difficulty in the etching process of the lower part of the groove is that the etching gas can only reach the lower part or the bottom of the groove in a small amount, and the root cause is that the generation and the accumulation of the polymer prevent the etching gas from entering the lower part of the groove, the other scheme can be adopted to enable the etching gas to enter the lower part of the groove more easily by reducing the generation of the polymer, so that the aim of correcting the side wall morphology of the groove is achieved. Due to the formation of polymer mainly following O2Correlation, therefore, can be achieved by gradually reducing O2To achieve this. Adding O to etching gas2The selectivity of the silicon etch can be increased, the sidewalls are protected by the polymer, but as the depth of the trench etch increases, the O is gradually reduced since the etch gas is less likely to enter the bottom of the trench itself and the polymer protects, making the etching of the bottom of the trench more difficult2The flow rate of (a) can reduce polymer generation and enhance etching capability of the sidewalls.
Control of etching gas flow or of O2The flow control needs to be determined by combining the actual process, and the flow control is flexibly controlled according to the characteristics of the respective process and the actual modification amount, and is not limited to a specific parameter range.
Of course, the above two schemes can be combined together, i.e., the flow rate of the silicon etching gas is gradually increased and the polymer forming gas O is gradually decreased2The flow rate of the deep groove is corrected, so that the purpose of correcting the etching morphology of the bottom of the deep groove is achieved. While for how to gradually increase the flow rate of the silicon etching gas and gradually decrease the polymer generation gas O2The flow rate, i.e. the gradual control parameters of the flow rate, needs to be optimized by repeated tests according to the process characteristics of the flow rate, so that a better parameter combination can be obtained. The present embodiment is not described in detail hereinFor example.
In some etching processes, the etching gas also includes a diluent gas, such as helium. The introduction of the diluent gas mainly solves the problem of a large amount of heat generated in the etching process, and the diluent gas takes away the heat of reaction to enhance the stability of the process environment.
Meanwhile, in some etching processes, the etching gas also comprises C2F6Etching the silicon oxide and the silicon nitride, and etching the chamfer at the top of the deep groove.
The process method for etching the high-aspect-ratio groove mainly aims at substrate etching, and mainly controls the appearance of the etched groove by controlling gradual change control of etching gas and polymer when a deep groove with the aspect ratio more than 20 is formed by etching a silicon substrate.
The invention mainly aims to provide a gas gradual change control method, which is not only limited to a specific etching process, but also can be used in other process fields, such as growth of a film and the like, and is not limited to the range of the groove etching process.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A process method for etching a trench with a high depth-to-width ratio is characterized in that: when etching gas is introduced into a semiconductor substrate to etch to form a deep groove, introducing fluorine-based or chlorine-based gas into a polymer to generate gas, and gradually increasing the flow of the etching gas or gradually reducing the flow of the gas for generating the polymer to reduce the generation of the polymer along with the continuous etching; or both may be performed simultaneously; the formation of different trench profiles is controlled by the gradual control of the rate of etching gas and/or polymer generation gas.
2. The process of etching a high aspect ratio trench as claimed in claim 1, wherein: the semiconductor substrate is a silicon substrate.
3. The process of etching a high aspect ratio trench as claimed in claim 1, wherein: the etching gas at least contains Cl2、HBr、O2。
4. The process of etching a high aspect ratio trench as claimed in claim 3, wherein: said Cl2HBr gas is used as etching gas of silicon to etch the silicon substrate; o is2Mainly as a gas of polymer formation.
5. The process of etching a high aspect ratio trench as claimed in claim 1, wherein: the depth-to-width ratio of the deep groove is more than 20.
6. The process of etching a high aspect ratio trench as claimed in claim 1, wherein: during normal etching, the depth of the groove is gradually increased along with the progress of the etching, the formed polymer is gradually accumulated, and the slope of the side wall of the groove is increased.
7. The process of etching a high aspect ratio trench as claimed in claim 1, wherein: the etching gas also comprises a diluent gas.
8. The process of etching a high aspect ratio trench as claimed in claim 7, wherein: the diluent gas is helium.
9. The process of etching a high aspect ratio trench as claimed in claim 4, wherein: the etching gas also comprises C2F6, and is used for etching silicon oxide and silicon nitride and etching chamfers on the tops of the deep grooves.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111011360.8A CN113782427A (en) | 2021-08-31 | 2021-08-31 | Process method for etching high depth-width ratio groove |
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| CN202111011360.8A CN113782427A (en) | 2021-08-31 | 2021-08-31 | Process method for etching high depth-width ratio groove |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001085638A (en) * | 1999-08-31 | 2001-03-30 | Promos Technologies Inc | Method for making bottle type deep trench |
| CN102117761A (en) * | 2010-01-05 | 2011-07-06 | 上海华虹Nec电子有限公司 | Wet process method for improving chamfer smoothness on top of shallow trench isolation |
| CN105655283A (en) * | 2014-11-13 | 2016-06-08 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Isolation etching method for shallow trench with high depth-to-width ratio |
| CN110668393A (en) * | 2018-07-02 | 2020-01-10 | 北京北方华创微电子装备有限公司 | Method for etching substrate |
-
2021
- 2021-08-31 CN CN202111011360.8A patent/CN113782427A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001085638A (en) * | 1999-08-31 | 2001-03-30 | Promos Technologies Inc | Method for making bottle type deep trench |
| CN102117761A (en) * | 2010-01-05 | 2011-07-06 | 上海华虹Nec电子有限公司 | Wet process method for improving chamfer smoothness on top of shallow trench isolation |
| CN105655283A (en) * | 2014-11-13 | 2016-06-08 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Isolation etching method for shallow trench with high depth-to-width ratio |
| CN110668393A (en) * | 2018-07-02 | 2020-01-10 | 北京北方华创微电子装备有限公司 | Method for etching substrate |
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Application publication date: 20211210 |