CN113782082A

CN113782082A - Two-dimensional wear leveling method for flash memory and solid state disk

Info

Publication number: CN113782082A
Application number: CN202111062883.5A
Authority: CN
Inventors: 方浩俊; 黄运新; 杨亚飞
Original assignee: Shenzhen Dapu Microelectronics Co Ltd
Current assignee: Shenzhen Dapu Microelectronics Co Ltd
Priority date: 2021-09-10
Filing date: 2021-09-10
Publication date: 2021-12-10
Anticipated expiration: 2041-09-10
Also published as: CN113782082B

Abstract

The invention discloses a two-dimensional wear leveling method for a flash memory and a solid state disk, which evaluate the wear condition of a flash memory block from two dimensions of an electronic leakage degree value and an electronic leakage trend value of the flash memory block. The electronic leakage degree value of the flash memory block can represent the erasing wear degree of the flash memory block, and the electronic leakage degree values of all the flash memory blocks are gathered in a certain range so as to achieve the erasing wear balance; the electronic leakage trend value of the flash memory block can represent the data retention time of the flash memory block, and the electronic leakage trend values of all the flash memory blocks are gathered in a certain range so as to achieve data retention time balance. Therefore, the method and the device realize balance control from two dimensions of erasing abrasion and data retention time, are more comprehensive and accurate, have better abrasion balance effect and further prolong the whole service life of the solid state disk.

Description

Two-dimensional wear leveling method for flash memory and solid state disk

Technical Field

The invention relates to the field of solid-state storage, in particular to a two-dimensional wear leveling method for a flash memory and a solid-state hard disk.

Background

Flash memory contains a plurality of flash blocks (blocks), each containing a plurality of flash pages (pages). The flash memory block is a basic unit for erasing the flash memory, and after data is written into a flash memory page, new writing operation can be performed only after the erasing operation is performed on the flash memory block.

For a solid state disk based on a flash memory (a solid state disk using a flash memory chip as a storage medium), wear leveling control of each flash memory block is a key factor for ensuring storage reliability of the solid state disk. At present, the wear leveling control scheme of each flash memory block is generally adopted as follows: and respectively acquiring the erasing times of each flash memory block in the flash memory, and performing erasing operation on each flash memory block by taking the erasing times of each flash memory block as a constraint condition. The consistent erasing times of the flash memory blocks are equal to the consistent abrasion degree of the flash memory blocks caused by the erasing times, so that the erasing abrasion balance of the flash memory blocks is realized. However, the existing wear leveling control scheme for each flash memory block can only realize single-dimensional leveling control of erasing wear, which is not comprehensive and accurate enough, and affects the wear leveling effect, and further affects the overall service life of the solid state disk.

Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.

Disclosure of Invention

The invention aims to provide a two-dimensional wear leveling method of a flash memory and a solid state disk, which realize leveling control from two dimensions of erasing wear and data retention time, are more comprehensive and accurate, have better wear leveling effect and further prolong the whole service life of the solid state disk.

In order to solve the above technical problem, the present invention provides a two-dimensional wear leveling method for a flash memory, comprising:

respectively acquiring an electron leakage degree value of each flash memory block in the flash memory immediately after electrons are injected, and respectively acquiring an electron leakage trend value of each flash memory block into which electrons are injected;

calculating the average leakage degree of the electronic leakage degree values of the flash memory blocks, and calculating the average leakage tendency of the electronic leakage tendency values of the flash memory blocks;

respectively calculating the leakage degree difference value between the electronic leakage degree value of each flash memory block and the leakage degree average value, and respectively calculating the leakage tendency difference value between the electronic leakage tendency value of each flash memory block and the leakage tendency average value;

and performing erasing operation on each flash memory block by taking the condition that the leakage degree difference value is smaller than a preset first dimension threshold value and the leakage trend difference value is smaller than a preset second dimension threshold value as constraints.

Preferably, the obtaining the electron leakage degree value of each flash block in the flash memory immediately after injecting electrons comprises:

calculating an electron leakage value LL of the target flash block just after the injection of the electrons according to LL ═ f (EPC) f (f1(T1) IRBER) or LL ═ f (EPC) f (f1(T1) IFBC); wherein the target flash memory block is any one of the flash memory blocks;

the EPC is the erasing times of the target flash memory block; t1 is the temperature value of the target flash block just after the electrons are injected; f1(T1) is a first temperature compensation coefficient corresponding to the temperature value T1; the IRBER is the IRBER value of the target flash memory block just after the electrons are injected; the IFBC is an IFBC value of the target flash memory block just after the electrons are injected; EPC and IRBER/IFBC are positively correlated with LL.

Preferably, the obtaining of the electron leakage trend values of the flash memory blocks into which electrons have been injected respectively comprises:

calculating an electron leakage trend value LT of the target flash block in a preset time delta T according to LT ═ f (delta RBER/delta T) × f2(T2) or LT ═ f (delta FBC/delta T) × f2 (T2);

wherein, the delta RBER is the RBER increase of the target flash memory block within a preset time delta t; Δ FBC is the FBC growth of the target flash block within a preset time Δ t; t2 is the average temperature value of the target flash memory block in the preset time delta T; f2(T2) is a second temperature compensation coefficient corresponding to the average temperature value T2; and the delta RBER/delta t is in positive correlation with LT.

Preferably, the method for obtaining the electron leakage degree value of each flash block in the flash memory immediately after injecting electrons further comprises:

multiplying the electron leakage degree value of the target flash memory block just after the electrons are injected by a preset first scale factor, and taking the multiplication result as the electron leakage degree value of the target flash memory block just after the electrons are injected;

respectively acquiring an electron leakage trend value of each flash memory block into which electrons have been injected, further comprising:

and multiplying the electronic leakage trend value of the target flash memory block in the preset time by a preset second scale factor, and taking the multiplication result as the electronic leakage trend value of the target flash memory block in the preset time.

Preferably, with the constraint that the leakage degree difference is smaller than a preset first dimension threshold and the leakage trend difference is smaller than a preset second dimension threshold, performing an erasing operation on each flash memory block, including:

selecting a target flash memory block with the leakage degree difference value smaller than a preset first low threshold value from the flash memory blocks; wherein the preset first low threshold is less than the preset first dimension threshold;

and selecting a required erasing block from the target flash memory blocks based on a data retention time balancing strategy for cold and hot data writing.

Preferably, based on the data retention time balancing strategy, selecting a required erase block from the target flash memory blocks for cold and hot data writing, comprising:

selecting a first flash memory block with the leakage trend difference value larger than a preset first threshold value from the target flash memory block so as to select a required erasing block from the first flash memory block, and writing heat supply data;

selecting a second flash memory block with the leakage trend difference value smaller than a preset second threshold value from the target flash memory blocks so as to select a required erasing block from the second flash memory block for cold data writing; the preset second threshold is less than or equal to the preset first threshold, and the preset first threshold is less than the preset second dimension threshold.

respectively acquiring an IRBER value or an IFBC value of each flash memory block immediately after electrons are injected;

judging whether the current corresponding IRBER value or IFBC value of each flash memory block is the same or not;

if not, selecting a third flash memory block of which the current corresponding IRBER value or IFBC value is smaller than a preset low error bit threshold value from the flash memory blocks so as to select a required erasing block from the third flash memory block for writing data to be written;

if so, selecting a fourth flash memory block of which the leakage trend difference value is smaller than a preset second low threshold value from the flash memory blocks so as to select a required erasing block from the fourth flash memory block for writing data to be written; wherein the preset second low threshold is less than the preset second dimension threshold.

Preferably, the determining whether the IRBER value or the IFBC value corresponding to each flash block is the same includes:

calculating an average value of the error bit predicted values corresponding to the flash memory blocks, and judging whether the difference values of the error bit predicted values corresponding to the flash memory blocks and the average value are all smaller than a preset difference threshold value; wherein the error bit estimated value is an IRBER value or an IFBC value;

if yes, determining that the current corresponding IRBER value or IFBC value of each flash block is the same;

if not, determining that the current corresponding IRBER value or IFBC value of each flash memory block is different.

Preferably, the obtaining the IRBER value or the IFBC value of the target flash memory block immediately after the electrons are injected comprises:

respectively obtaining IRBER values or IFBC values of N flash memory pages which just inject electrons in the target flash memory block; wherein N is a positive integer;

and selecting the maximum IRBER value or IFBC value from the IRBER values or IFBC values of the N flash memory pages, and taking the maximum IRBER value or IFBC value as the IRBER value or IFBC value of the target flash memory block just after the electrons are injected.

In order to solve the above technical problem, the present invention further provides a solid state disk, including:

flashing;

a controller for implementing the steps of any of the above-described two-dimensional wear leveling methods for flash memory when executing a stored computer program.

The invention provides a two-dimensional wear leveling method of a flash memory, which is used for evaluating the wear condition of a flash memory block from two dimensions of an electronic leakage degree value and an electronic leakage trend value of the flash memory block. The electronic leakage degree value of the flash memory block can represent the erasing wear degree of the flash memory block, and the electronic leakage degree values of all the flash memory blocks are gathered in a certain range so as to achieve the erasing wear balance; the electronic leakage trend value of the flash memory block can represent the data retention time of the flash memory block, and the electronic leakage trend values of all the flash memory blocks are gathered in a certain range so as to achieve data retention time balance. Therefore, the method and the device realize balance control from two dimensions of erasing abrasion and data retention time, are more comprehensive and accurate, have better abrasion balance effect and further prolong the whole service life of the solid state disk.

The invention also provides a solid state disk which has the same beneficial effect as the two-dimensional wear leveling method.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a flowchart of a two-dimensional wear leveling method for a flash memory according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an electron leakage of a memory cell according to an embodiment of the present invention;

FIG. 3 is an aggregation chart of the wear level of a flash block according to an embodiment of the present invention;

FIG. 4 is an aggregate graph of wear leveling of flash blocks over time according to an embodiment of the present invention;

FIG. 5 is a graph of the wear level of flash blocks as a function of time for time-only equalization according to an embodiment of the present invention;

FIG. 6 is a graph of the wear of flash blocks as they are worn out and time kept balanced over time according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating the relationship between DR time and RBER of a flash block according to an embodiment of the present invention;

FIG. 8 is a schematic diagram illustrating the retention time of cold and hot data according to an embodiment of the present invention;

FIG. 9 is a diagram illustrating a retention time balance of hot and cold data according to an embodiment of the present invention;

FIG. 10 is a diagram illustrating an adjustment of a flash lifetime dimension according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a solid state disk SSD based on a flash memory according to an embodiment of the present invention.

Detailed Description

The core of the invention is to provide a two-dimensional wear leveling method of a flash memory and a solid state disk, which realize leveling control from two dimensions of erasing wear and data retention time, are more comprehensive and accurate, ensure better wear leveling effect and further prolong the whole service life of the solid state disk.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a flowchart illustrating a two-dimensional wear leveling method for a flash memory according to an embodiment of the present invention.

The two-dimensional wear leveling method of the flash memory comprises the following steps:

step S1: respectively acquiring the electron leakage degree value of each flash memory block in the flash memory just after the electrons are injected, and respectively acquiring the electron leakage trend value of each flash memory block with the injected electrons.

Specifically, flash memory is a non-volatile storage medium, which is widely used and is suitable for various storage situations, and the architecture thereof is generally divided into three types, namely SLC (Single-Level Cell, Single-layer Cell, which means that 1 memory Cell can store 1 bit of data, and there are two cases of 0 and 1), MLC (Multi-Level Cell, double-layer Cell, which means that 1 memory Cell can store 2 bits of data, and there are four cases of (11, 10, 01, 00)), and TLC (Triple-Level Cell, three-layer Cell, which means that 1 memory Cell can store 3 bits of data, and there are 8 cases of (000, 001, 010, 011, 100, 101, 110, 111)).

For SLC flash, each flash page in a flash block is used to store a single bit of data. For the MLC flash memory, each data block includes two types of pages, which are called MSB (Most Significant Bit) page and LSB (Least Significant Bit) page, respectively, where the MSB page is used to store the high bits of the two bits, and the LSB page is used to store the low bits of the two bits; that is, the MSB page and the LSB page are a pair of pages, and the high bits in the MSB page and the corresponding low bits in the LSB page constitute the complete double bits. For the TLC flash memory, each data block includes three types of pages, which are called MSB (Most Significant Bit) page, CSB (Central Significant Bit) page and LSB (Least Significant Bit) page, respectively, where the MSB page is used for storing the upper bits of three bits, the CSB page is used for storing the middle bits of the three bits, and the LSB page is used for storing the lower bits of the three bits; that is, the MSB page, the CSB page, and the LSB page are a pair of pages, and the high bits in the MSB page, the corresponding middle bits in the CSB page, and the corresponding low bits in the LSB page constitute the complete three bits.

Flash memories actually store electrons in a memory Cell (Cell), and the number of stored electrons is represented as a voltage value to express a stored bit value by the voltage value. Flash memory errors are mainly read misjudgment caused by voltage changes of memory cells due to electron leakage, namely, a wrong bit value occurs, and if the number of wrong bits is larger than the error correction capability of a reading device, the flash memory is not usable.

And wear is a major factor affecting the electronic storage capacity of the memory cell. For easy understanding, as shown in fig. 2, the memory cell corresponds to a room with a door, the writing operation is to inject electrons, and the target is to inject 100 electrons, but due to wear and tear, only 90 electrons are injected (in the case of TLC, 3 bits of the memory cell are read, and 1 bit error is shown to the outside) when the actual completion is completed, the electrons continuously escape with time, and only 80 electrons remain when the reading is performed again (in the case of reading 3 bits of the memory cell, and 2 bit errors are shown to the outside). It can be understood that the wear of the flash memory block can be evaluated by adopting two dimensions of the electronic leakage degree value and the electronic leakage trend value of the flash memory block; the electronic leakage degree value of the flash memory block represents an initial state (difference between the actual quantity of injected electrons and the expected quantity of injected electrons) of the flash memory block just after the electrons are injected, and is externally represented by an initial error bit number of the flash memory block just after data are written; the trend value of electron leakage of flash memory block is characterized by the state change (electron escape speed) of the flash memory block with injected electrons, and the appearance is that the number of error bits is continuously increased on the basis of the initial number of error bits, and the DR (Data Retention) capability is weaker and weaker.

Based on this, the electronic leakage degree values of the flash memory blocks in the flash memory immediately after the electrons are injected are respectively obtained (the corresponding electronic leakage degree value can be obtained immediately after the electrons are injected into each flash memory block every time), and the electronic leakage trend values of the flash memory blocks with the injected electrons are respectively obtained, so that a basis is provided for the subsequent wear leveling control.

Step S2: the average value of the leakage degree of the electronic leakage degree value of each flash memory block is obtained, and the average value of the leakage tendency of the electronic leakage tendency value of each flash memory block is obtained.

Specifically, the electronic leakage degree values of the flash memory blocks are added to obtain a total electronic leakage degree value, and the total electronic leakage degree value is divided by the number of the flash memory blocks to obtain a leakage degree average value of the flash memory blocks. Similarly, the electronic leakage trend values of the flash memory blocks are added to obtain a total electronic leakage trend value, and the total electronic leakage trend value is divided by the number of the flash memory blocks to obtain a leakage trend average value of the flash memory blocks.

Step S3: and respectively calculating the leakage degree difference value between the electronic leakage degree value of each flash memory block and the leakage degree average value, and respectively calculating the leakage tendency difference value between the electronic leakage tendency value of each flash memory block and the leakage tendency average value.

Specifically, the electronic leakage degree value of each flash memory block is respectively subtracted from the average leakage degree value, and the leakage degree difference (absolute value) corresponding to each flash memory block is correspondingly obtained. Similarly, the electronic leakage trend value of each flash memory block is respectively subtracted from the average leakage trend value, and the leakage trend difference value (absolute value) corresponding to each flash memory block is correspondingly obtained.

Step S4: and performing erasing operation on each flash memory block by taking the condition that the leakage degree difference value is smaller than a preset first dimension threshold value and the leakage trend difference value is smaller than a preset second dimension threshold value as constraints.

Specifically, if the electron Leakage Level value is LL (Leakage Level) and the electron Leakage tendency value is LT (Leakage Trend), the wear Level of the flash block can be expressed as Pa ═ LL (LT), where Pa is a two-dimensional value of LL and LT. When Pa is used as a wear leveling index, the method for judging wear leveling by adopting the aggregation degree is one of feasible methods, wherein the aggregation degree refers to the fact that the wear degrees Pa of different flash memory blocks are aggregated in a certain range of the wear degree Pa _ ref of a reference block. Specifically, the wear leveling takes the wear degree Pa _ ref of a reference block as a central point, and the aggregation metric values of the wear degrees Pa of different flash memory blocks to the central point are taken as a leveling standard; the two-dimensional value of the reference abrasion degree Pa _ ref of the central point is a two-dimensional average value of the abrasion degrees Pa of all the flash memory blocks; the aggregate metric is the difference between the two-dimensional value of the degree of wear Pa of the target block and the two-dimensional average of the center point: Δ LL is an absolute difference between the LL value of the target block and the LL value of the center point, and Δ LT is an absolute difference between the LT value of the target block and the LT value of the center point. The concentration is controlled by a threshold value, and the threshold value is set as follows: th1 is a first dimension threshold, Th2 is a second dimension threshold, Δ LL < Th1, Δ LT < Th 2. That is, if the wear degrees Pa of all flash blocks are gathered within a range controlled by a threshold value (i.e., Δ LL < Th1, Δ LT < Th2) within a certain time, it is considered that wear leveling is achieved during the time. As shown in fig. 3, the virtual loop with the reference wear degree Pa _ ref as the center point is a range controlled by a threshold, and of the four flash memory blocks, the wear degrees (Pa1, Pa3, Pa4) of three flash memory blocks are in the virtual loop and meet the wear leveling standard; the wear level (Pa2) of one flash block is outside the dotted circle, deviates from the center point, does not meet the wear leveling standard, and is to be improved by the leveling strategy.

It should be noted that the reference wear degree Pa _ ref varies with time, so the reference wear degree Pa _ ref calculates the average value of two dimensions of all the flash memory blocks at certain time intervals to obtain the average value

The target block has a degree of wear Pa _ x (LLx, LTx), then

ΔPa_x(ΔLLx,ΔLTx)。

The first dimension LL is used for wear leveling and the second dimension LT is used for keeping time leveling. In the first dimension LL value, Th1 is set as a first dimension threshold value for controlling wear leveling. In the second dimension LT value, Th2 is set as a second dimension threshold value for data retention time equalization. When Δ LLx < Th1, Δ LTx < Th2, the flash blocks are concentrated near the reference wear level (center point). As shown in fig. 4, Δ LT takes a large value for the performance of only wear leveling, i.e., the second dimension LT, the second dimension threshold margin for Δ LT control. As shown in fig. 5, to perform only the time keeping balanced performance, i.e., the first dimension LL, the first dimension threshold margin for Δ LL control, Δ LL assumes a larger value.

Based on the method, the erasing operation is carried out on each flash memory block by taking the condition that the leakage degree difference value is smaller than the preset first dimension threshold value and the leakage trend difference value is smaller than the preset second dimension threshold value as constraints, so that the abrasion degree Pa of each flash memory block is ensured to be gathered in a range controlled by the threshold value, and the abrasion balance is achieved. As shown in fig. 6, during t0 to tn, although the reference wear degree Pa _ ref (center point) changes with time, all flash blocks are gathered toward the reference wear degree Pa _ ref (center point) in each period. It should be noted that the electronic leakage degree value of the flash memory block can represent the erasing wear degree of the flash memory block, and the electronic leakage degree values of all the flash memory blocks are gathered in a certain range, so that the erasing wear balance can be achieved; the electronic leakage trend value of the flash memory block can represent the data retention time of the flash memory block, and the electronic leakage trend values of all the flash memory blocks are gathered in a certain range, so that the data retention time balance can be achieved. Therefore, on the basis that the wear condition of the flash memory block is evaluated by adopting two dimensions of the electronic leakage degree value and the electronic leakage trend value of the flash memory block, the method and the device can realize balanced control from two dimensions of erasing wear and data retention time, and are more comprehensive and accurate, so that the wear balance effect is better, and the whole service life of the solid state disk is prolonged.

On the basis of the above-described embodiment:

as an alternative embodiment, the obtaining the electron leakage degree value of each flash block in the flash memory immediately after injecting electrons includes:

calculating an electron leakage value LL of the target flash block just after the injection of the electrons according to LL ═ f (EPC) f (f1(T1) IRBER) or LL ═ f (EPC) f (f1(T1) IFBC); wherein, the target flash memory block is any flash memory block;

the EPC is the erasing times of the target flash memory block; t1 is the temperature value of the target flash block just after the injection of electrons; f1(T1) is a first temperature compensation coefficient corresponding to the temperature value T1; the IRBER is the IRBER value of the target flash memory block just after the electrons are injected; the IFBC is an IFBC value of the target flash memory block just after the electrons are injected; EPC and IRBER/IFBC are positively correlated with LL.

Specifically, the calculation relation of the electron leakage level value LL of any flash block immediately after the injection of electrons is: wherein LL ═ f (EPC) f (f1(T1) × IRBER), which indicates that the electron leakage level value LL is a functional relationship between EPC (Erase-Program Cycles) and IRBER (Initial Raw Bit Error Rate, Initial Raw Bit Error Rate immediately after electron injection, and Raw Bit Error Rate) values, it should be noted that the more EPCs of flash blocks, the greater the electron leakage level value LL immediately after electron injection, the greater the positive correlation between the EPCs and IRBER and LL; the larger the IRBER value of the flash block immediately after the injection of electrons, the larger the electron leakage level value LL of the flash block immediately after the injection of electrons. In addition, since the IRBER value of the flash block immediately after the injection of electrons is affected by temperature, the present application further provides a first temperature compensation coefficient f1(T1), T1 being the temperature value of the flash block immediately after the injection of electrons, so that the IRBER value is corrected by the first temperature compensation coefficient f1(T1) to reduce the effect of temperature on the IRBER value as much as possible. If f1(T1) is δ, δ ∈ {1.1,1.2,1.3,1.4 … … } (T1 ═ 40 ℃,50 ℃,60 ℃,70 ℃, … …), i.e., T1 ═ 40 ℃, δ is 1.1; when T1 is 50 ℃, delta is 1.2; when T1 is 60 ℃, delta is 1.3; when T1 is 70 ℃, δ is 1.4 … … (of course, δ may be set to other compensation values, and set according to actual requirements).

More specifically, the positive correlation between the EPC and IRBER of the flash memory block and LL is specifically: LL ═ EPC ×. δ IRBER, can also be: LL ═ EPC + k · (δ × IRBER), k is a preset coefficient; LL is i × EPC + j (δ × IRBER), i and j are predetermined coefficients, and any relational expression may be used as long as it represents a positive correlation between EPC, IRBER and LL.

It should be noted that FBC (Failure Bit Counter) and RBER of the flash block have similar meanings, and the relationship between FBC and RBER can be expressed as FBC ═ RBER BitCNT, and BitCNT is the total number of bits of the flash block. Therefore, the RBERs mentioned in this embodiment can be expressed by FBC instead, and similarly, IRBER can also be expressed by IFBC (Initial Failure Bit Counter).

As an alternative embodiment, the obtaining of the electron leakage trend value of each flash memory block into which electrons have been injected comprises:

calculating an electron leakage trend value LT of the target flash block within a preset time delta T according to LT ═ f (delta RBER/delta T) × f2(T2) or LT ═ f (delta FBC/delta T) × f2 (T2);

wherein, the delta RBER is the RBER increase of the target flash memory block within a preset time delta t; the delta FBC is the FBC growth amount of the target flash memory block within a preset time delta t; t2 is the average temperature value of the target flash memory block within the preset time delta T; f2(T2) is a second temperature compensation coefficient corresponding to the average temperature value T2; and the delta RBER/delta t is in positive correlation with LT.

Specifically, the calculation relation of the electron leakage tendency value LT of any flash memory block in the preset time Δ t is as follows: it should be noted that the Δ RBER/Δ T of the flash block and the LT have a positive correlation, that is, the greater the Δ RBER/Δ T of the flash block, the greater the tendency value LT of the flash block to leak electrons within the preset time Δ T. In addition, since the RBER increase Δ RBER of the flash memory block within the preset time Δ T is affected by the temperature, the present application further provides a second temperature compensation coefficient f1(T2), where T2 is an average temperature value of the flash memory block within the preset time Δ T, so as to modify the Δ RBER value by the second temperature compensation coefficient f1(T2), thereby reducing the influence of the temperature on the Δ RBER value as much as possible.

More specifically, when the average temperature value T2 of the flash block during the preset time Δ T is greater than the preset standard temperature (25 ℃), the calculation relationship of the electron leakage tendency value LT of the flash block during the preset time Δ T is:

f2(T2) ═ γ, γ < 1, such as γ ∈ {0.9,0.8,0.7,0.6 … … } (T2 ═ 40 ℃,50 ℃,60 ℃,70 ℃, … …), i.e. when T2 ═ 40 ℃, γ is 0.9; when T2 is 50 ℃, gamma is 0.8; when T2 is 60 ℃, gamma is 0.7; at 70 ℃ T2, γ is 0.6 … … (of course,_γother compensation value settings can be carried out, and RBER acceleration under the reduction standard temperature can be considered); when the average temperature value T2 of the flash memory block in the preset time delta T is not more than the preset standard temperature, the calculation relation of the electron leakage trend value LT of the flash memory block in the preset time delta T is as follows:

in addition, the nominal reliability of a flash block refers to: under the requirements of nominal erasing times and error correction capability of reading deviceWith a data retention time. All flash blocks have a nominal maximum hold time, since RBER increases in proportion to time, and for a sufficiently long time the RBER must exceed the error correction capability threshold of the reading device (set as RBER'), as shown in fig. 7. Based on the method, the current RBER value of the flash memory block is subtracted from the error correction capacity threshold value RBER' corresponding to the flash memory block to obtain the current RBER growth allowance of the flash memory block, and then the current RBER growth allowance of the flash memory block is divided by the current RBER growth rate of the flash memory block

And obtaining the current remaining data retention time of the flash memory block.

It should be noted that FBC and RBER of the flash block have similar meanings, and therefore, RBER mentioned in this embodiment can be expressed by FBC instead, and similarly, Δ RBER can be expressed by Δ FBC instead, and RBER' can be expressed by FBC instead.

As an alternative embodiment, the method for separately obtaining the electron leakage degree value of each flash block in the flash memory immediately after injecting electrons further includes:

respectively acquiring an electron leakage trend value of each flash memory block injected with electrons, and further comprising:

Furthermore, the electron leakage rate value LL ═ α ═ LL and the electron leakage trend value LT ═ β ═ LT, that is, the wear rate of the flash block is Pa ═ LL, β ═ LT), α is the first scaling factor, and β is the second scaling factor, and is used to adjust the proportional relationship between LL and LT. Typically, α is 1- β, α, β ∈ {0.1,0.2,0.3,0.4 … … 0.9.9 }; specifically, the size of the scaling factor may be preset for adjusting different design requirements, for example, if some flash memories are located in a place with a higher working temperature, the ratio of the electron leakage trend value LT needs to be increased, and α < β, β is 0.6,0.7, etc. (the ratio may be set according to the temperature); some flash memories are novel QLCs (quad-Level cells, four-layer memory cells, which means that 1 memory Cell can store 4 bits of data), and if the nominal value is small, the electronic leakage Level LL occupation ratio needs to be increased, α > β, α is 0.6,0.7, and the like.

As an alternative embodiment, performing an erasing operation on each flash memory block with the constraint that the leakage degree difference is smaller than the preset first dimension threshold and the leakage trend difference is smaller than the preset second dimension threshold includes:

selecting a target flash memory block with a leakage degree difference value smaller than a preset first low threshold value from all the flash memory blocks; wherein the preset first low threshold is smaller than the preset first dimension threshold;

and selecting a required erasing block from the target flash memory blocks based on the data retention time balancing strategy for cold and hot data writing.

Specifically, the first equalization strategy of the present application is: the erasing wear balance is prioritized (that is, the LL value of each flash memory block is kept to be close to the average value of the leakage degree to the maximum extent so as to ensure that the wear times of each flash memory block are consistent and each flash memory block has a similar service life), and the data holding time is kept as balanced as possible. Based on this, when selecting the target erase block, the method preferentially selects the target flash memory block with the leakage degree difference value delta LL smaller than the preset first low threshold value from all the flash memory blocks, namely, the flash memory block with the smaller delta LL is taken as the target flash memory block, and then selects the required erase block from the target flash memory block based on the data retention time balancing strategy for cold and hot data writing, so that the priority of erasing wear balancing is met, and the data retention time is kept as balanced as possible.

As an alternative embodiment, based on the data retention time balancing strategy, selecting a desired erase block from the target flash memory blocks for cold and hot data writing, comprising:

selecting a first flash memory block with a leakage trend difference value larger than a preset first threshold value from the target flash memory block so as to select a required erasing block from the first flash memory block, and writing heat supply data;

selecting a second flash memory block with the leakage trend difference smaller than a preset second threshold value from the target flash memory block so as to select a required erasing block from the second flash memory block for cold data writing; the preset second threshold is less than or equal to the preset first threshold, and the preset first threshold is less than the preset second dimension threshold.

Specifically, the imbalance of the flash memory blocks occurs due to various reasons, such as hot data, which refers to data that is updated relatively frequently, and cold data, which refers to data that is not updated for a relatively long period of time. The hot data is updated fast, i.e., the number of rewrites is large, and the cold data is updated slow, i.e., the number of rewrites is small, so that the data retention time of the hot data is longer than that of the cold data. As shown in fig. 8, if data retention time equalization is not performed, the flash block0, the flash block1, and the flash block 2 have similar wear times, but the RBER increases the speed differently, the data retention time differs, the data retention time of cold data in the flash block0 is shorter, and hot data is transferred between the flash block1 and the flash block 2, which further increases the overall retention time of hot data.

In order to equalize data retention time, the application selects a first flash memory block with a leakage tendency difference value delta LT larger than a preset first threshold value from target flash memory blocks (the leakage degree difference value delta LL is smaller than a preset first low threshold value) so as to select a required erasing block for writing heat supply data into the first flash memory block, namely, the flash memory block with the larger delta LT is taken as the erasing block for writing the heat supply data; and selecting a second flash memory block with the leakage trend difference value delta LT smaller than a preset second threshold value (the second threshold value is smaller than or equal to the first threshold value) from the target flash memory blocks so as to select a required erasing block for writing cold data from the second flash memory block, namely selecting the flash memory block with smaller delta LT as the erasing block for writing cold data. It should be noted that since the error bit increase speed of the flash block with a large Δ LT is fast, the data holding time is short, that is, the data holding time of the flash block with a small Δ LT is longer than that of the flash block with a large Δ LT, and therefore, the hot data selects the flash block with a low data holding time represented by a high Δ LT, and the extension of the data holding time is compensated by rewriting, so that the data holding time is equalized, as shown in fig. 9, when comparing points, it can be seen that the holding time of the cold data and the holding time of the hot data are equalized to each other.

respectively obtaining an IRBER value or an IFBC value of each flash memory block immediately after electrons are injected;

judging whether the IRBER value or IFBC value corresponding to each flash memory block is the same or not;

if not, selecting a third flash memory block of which the current corresponding IRBER value or IFBC value is smaller than a preset low error bit threshold value from all the flash memory blocks so as to select a required erasing block from the third flash memory block for writing data to be written;

if so, selecting a fourth flash memory block with the leakage trend difference smaller than a preset second low threshold value from all the flash memory blocks so as to select a required erasing block from the fourth flash memory block for writing data to be written; and the preset second low threshold is smaller than the preset second dimension threshold.

Specifically, the second equalization strategy of the present application is: firstly, the service life dimension of the flash memory is adjusted, the erasing times of the flash memory block with low IRBER are properly increased: when selecting the erasing block, preferentially selecting the flash memory block with low IRBER as the erasing block; secondly, further fine tuning the data retention time: when the number of times of erasing and writing of each flash memory block is slightly different and the IRBER is the same, the second dimension LT is further selected, and the flash memory block with smaller Delta LT is preferentially selected as the erasing block.

Based on the above, the method and the device respectively obtain the IRBER value of each flash memory block immediately after the electrons are injected, and then judge whether the corresponding IRBER values of the flash memory blocks are the same or not; if the data are the same (certain deviation is allowed), selecting a third flash memory block of which the current corresponding IRBER value is smaller than a preset low error bit threshold value from the flash memory blocks, and selecting a required erasing block from the third flash memory block (namely selecting the flash memory block with low IRBER as the erasing block) for writing the data to be written; if not, selecting a fourth flash memory block with the leakage trend difference value delta LT smaller than a preset second low threshold value from all the flash memory blocks, and selecting a required erasing block from the fourth flash memory block (namely selecting the flash memory block with smaller delta LT as the erasing block) for writing data to be written.

It should be noted that, the balance strategy properly relaxes the wear balance, the flash memory block with low IRBER properly increases the erasing times, the flash memory block with high IRBER properly decreases the erasing times, and the total life of the flash memory can be higher than the nominal value: the reliability requirement can still be reached beyond the end of a certain number of erasures (the RBER under the data retention time is lower than the error correction capability). As shown in fig. 10, in (i), only by adjusting the number of times of erasing, of two flash memory blocks, Block0 and Block1, Block0 reaches the end of life first (DRt is the nominal maximum retention time), and Block1 has a longer life; secondly, the erasing times of the Block0 are reduced to prolong the service life of the flash memory, and the erasing times of the Block1 are increased to shorten the service life of the flash memory, so that the reliability requirement at the end of the life is met (the DR0 and the DR1 are close to DRt'), and finally the service lives of two flash memory blocks of the Block0 and the Block1 are balanced, so that the whole service life of the flash memory is prolonged.

As an alternative embodiment, the determining whether the IRBER value or the IFBC value corresponding to each flash block is the same includes:

calculating the average value of the error bit estimated values corresponding to each flash memory block, and judging whether the difference values of the error bit estimated values corresponding to each flash memory block and the average value are all smaller than a preset difference threshold value; wherein, the error bit estimated value is IRBER value or IFBC value;

if yes, determining that the currently corresponding IRBER value or IFBC value of each flash memory block is the same;

Specifically, the method and the device solve the IRBER average value of the IRBER value corresponding to each flash memory block, and judge whether the difference value between the IRBER value corresponding to each flash memory block and the IRBER average value is smaller than a preset difference threshold value; if all the difference values are smaller than the preset difference value threshold value, the current corresponding IRBER values of all the flash memory blocks are considered to be the same; and if the difference value which is not smaller than the preset difference value threshold exists in all the difference values, the current corresponding IRBER value or IFBC value of each flash memory block is considered to be different.

It should be noted that the IFBC and IRBER of the flash block have similar meanings, and therefore, the IRBER mentioned in this embodiment can be expressed by the IFBC instead.

As an alternative embodiment, obtaining the IRBER value or the IFBC value of the target flash memory block immediately after the injection of electrons includes:

respectively obtaining IRBER values or IFBC values of N flash memory pages which just inject electrons into a target flash memory block; wherein N is a positive integer;

and selecting the maximum IRBER value or IFBC value from the IRBER values or IFBC values of the N flash memory pages, and correspondingly taking the maximum IRBER value or IFBC value as the IRBER value or IFBC value of the target flash memory block just after the electrons are injected.

Specifically, the process of acquiring the IRBER value of any flash block immediately after the injection of electrons in the present application is as follows (explained with reference to a target flash block): 1) respectively obtaining IRBER values of N flash memory pages which are just injected with electrons in a target flash memory block; 2) comparing the IRBER values of the N just-injected electron flash memory pages to select a maximum IRBER value from the IRBER values of the N just-injected electron flash memory pages; 3) and taking the selected maximum IRBER value as the IRBER value of the target flash block just after the electrons are injected.

For example, for TLC flash memory, data is written in MSB page, CSB page and LSB page of a pair of pages of the target flash block, and then the process of obtaining IRBER value of the target flash block just after injecting electrons is as follows: 1) respectively obtaining the IRBER values of the MSB page, the CSB page and the LSB page of the target flash memory block into which electrons are just injected; 2) comparing the IRBER values of the MSB page, the CSB page and the LSB page to select the largest IRBER value from the IRBER values of the MSB page, the CSB page and the LSB page; 3) and taking the selected maximum IRBER value as the IRBER value of the target flash block just after the electrons are injected.

In addition, the flash-based Solid State Disk is generally referred to as SSD (Solid State Disk), and as shown in fig. 11, the Solid State Disk SSD includes: 1) SSD Controller (solid state hard disk Controller): as a control operation unit, managing an SSD internal system; 2) NAND Flash Array (non-volatile Flash memory Array): as storage units, storing data (user data and system data), typically presenting multiple Flash channels (channels, abbreviated as CH), one Channel independently connected to a set of NAND Flash Array, as shown in fig. 11 as CH0/CH1 · · CHx; the NAND Flash (Flash memory) has the characteristics that erasing is required before writing, and the erasing times of each Flash memory are limited; 3) DDR (Double Data Rate, Double Data synchronous Dynamic Random Access Memory)/DRAM (Dynamic Random Access Memory): the cache is used as a cache; 4) connector: for connecting to a host, such as a PC (Personal Computer) or a server; 5) other Peripheral units, such as PMIC (Power Management IC), OSC (crystal Oscillator), JTAG (Joint Test Action Group) Interface, SPI (Serial Peripheral Interface) Interface, Sensor (Sensor), and UART (Universal Asynchronous Receiver/Transmitter) Interface.

It should be noted that the two-dimensional wear leveling method for the flash memory provided in the above embodiments may be implemented by controller programming or hardware logic circuits in the solid state disk based on the flash memory.

The application also provides a solid state disk, including:

flashing;

For introduction of the solid state disk provided in the present application, reference is made to the above-mentioned embodiment of the two-dimensional wear leveling method, which is not described herein again.

It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A two-dimensional wear leveling method for a flash memory, comprising:

2. The method of claim 1, wherein the step of obtaining the electron leakage level of each flash block in the flash memory immediately after injecting electrons comprises:

3. The method for two-dimensional wear leveling of a flash memory according to claim 2, wherein separately obtaining electron leakage trend values for said flash blocks into which electrons have been injected, comprises:

calculating an electron leakage trend value LT of the target flash block within a preset time delta T according to LT ═ f (delta RBER/delta T) f2(T2) or LT ═ f (delta FBC/. DELTA T) f2 (T2);

wherein, the Delta RBER is the RBER growth amount of the target flash memory block within a preset time Delta t; Δ FBC is the FBC growth of the target flash block within a preset time Δ t; t2 is the average temperature value of the target flash memory block in the preset time delta T; f2(T2) is a second temperature compensation coefficient corresponding to the average temperature value T2; and the delta RBER/delta t is in positive correlation with LT.

4. The two-dimensional wear leveling method for flash memories according to claim 3, wherein the step of obtaining the electron leakage level value of each flash block in the flash memory immediately after the injection of electrons further comprises:

5. The method for two-dimensional wear leveling of flash memory according to any of claims 1-4, wherein the erasing operation for each flash block is constrained by the difference in the leakage levels being less than a predetermined first dimension threshold and the difference in the leakage trends being less than a predetermined second dimension threshold, comprising:

6. The two-dimensional wear leveling method for flash memory according to claim 5, wherein selecting a desired erase block from the target flash memory blocks for hot and cold data writing based on a data retention time leveling policy comprises:

7. The method for two-dimensional wear leveling of flash memory according to any of claims 2-4, wherein the erasing operation for each flash block is constrained by the difference in the leakage levels being less than a predetermined first dimension threshold and the difference in the leakage trends being less than a predetermined second dimension threshold, comprising:

8. The method for two-dimensional wear leveling of flash memories according to claim 7, wherein determining whether the IRBER or IFBC values corresponding to the flash blocks are the same comprises:

9. The method for two-dimensional wear leveling of flash memory according to claim 7, wherein obtaining the IRBER value or the IFBC value of the target flash block immediately after the injection of electrons comprises:

10. A solid state disk, comprising:

flashing;

a controller for implementing the steps of the two-dimensional wear leveling method of a flash memory according to any of claims 1-9 when executing a stored computer program.