CN113778216A - Method for reducing chip power consumption - Google Patents
Method for reducing chip power consumption Download PDFInfo
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- CN113778216A CN113778216A CN202111095072.5A CN202111095072A CN113778216A CN 113778216 A CN113778216 A CN 113778216A CN 202111095072 A CN202111095072 A CN 202111095072A CN 113778216 A CN113778216 A CN 113778216A
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- power supply
- supply network
- power consumption
- chip
- switch unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention relates to a method for reducing chip power consumption, which comprises the steps of determining the power consumption requirement of a power consumption load in a chip module; the electric load comprises a standard unit and a hard macro in a chip module; determining a plurality of turn-off domains according to the physical location of the electrical load; wherein each turn-off domain contains one or more standard cells and/or one or more hard macros; correspondingly inserting switch units in the turn-off domain according to the positions of the hard macro and the standard units in the turn-off domain; establishing a first stacking hole between a high-level power supply network and a switch unit, and establishing a second stacking hole between the switch unit and a transition-level power supply network; and the switching unit is used for switching on or switching off the connection between the standard unit and the hard macro and the power supply according to the received control signal.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a method for reducing chip power consumption.
Background
In the field of low power consumption design, the most effective means for reducing power consumption is to turn off the power supply. The reason for this is that no matter how low the voltage, how small the current, how slow the speed or how small the leakage current is, is not as thorough as completely turning off the power supply.
However, it is clearly impractical to power down the entire chip for an active chip. Then a truly low power consumption can be achieved if the inactive modules in the chip can be shut down while the modules that remain active continue to operate.
In the existing chip, a power supply network is realized by one layer of metal, the top layer of metal is always maintained in a power-on state, and the bottom layer of metal is connected with the top layer of metal through holes layer by layer for power supply transmission.
How to maintain the working module in the chip to continue working and simultaneously turn off the non-working module to reduce the power consumption of the chip is the technical purpose to be realized by the invention.
Disclosure of Invention
The embodiment of the invention provides a method for reducing chip power consumption, wherein a turn-off domain is controlled by a switch unit, so that when some modules in a chip do not need to participate in work, the switch unit can be controlled to turn off power loads in the corresponding turn-off domain, and the purpose of reducing chip power consumption is achieved.
Therefore, the embodiment of the invention provides a method for reducing chip power consumption, which comprises the following steps:
determining the power consumption requirement of a power consumption load in the chip module; the electric load comprises standard cells and Hard Macro Hard Macro in a chip module;
determining a plurality of turn-off domains according to the physical location of the electrical load; wherein each turn-off domain contains one or more standard cells and/or one or more hard macros;
according to the positions of the hard macro and the standard cell in the turn-off domain, correspondingly inserting a switch cell in the turn-off domain; the switch units, the standard units and the hard macros are arranged in a horizontal position, and the position relation among the inserted switch units, the hard macros and the standard units meets the requirement of a design rule;
establishing a first stacking hole between a high-level power supply network and the switch unit, and establishing a second stacking hole between the switch unit and a transition-level power supply network; the high-level power network is a power network with one or two layers at the top for connecting a power supply; the transition layer power supply network is specifically a power supply network of each layer between the high-layer power supply network and the bottom layer power supply network except the high-layer power supply network and the bottom layer power supply network; the bottom layer power supply network is connected with the transition layer power supply network; the bottom layer power supply network is a power supply network for connecting the standard unit and the hard macro in the chip module;
and the switch unit is connected or disconnected with the standard unit and the hard macro and the power supply according to the received control signal.
Preferably, the switching units in the chip module are connected in parallel.
Preferably, the sum of the IR Drop of each switch unit in the chip module and the chip module itself is less than 10% of the power supply operating voltage.
Further preferably, the IR-drop of one of said switching units is equal to the operating current and the on-resistance R of the switching unitONThe product of (a).
Further preferably, the working current is obtained by calculating a ratio of power consumption to working voltage when the chip module is working.
Preferably, the switch unit is disposed below the underlying power supply network.
According to the method for reducing the power consumption of the chip, the turn-off domain is controlled through the switch unit, so that when some modules in the chip do not need to participate in work, the switch unit can be controlled to turn off the power load in the corresponding turn-off domain, and the purpose of reducing the power consumption of the chip is achieved.
Drawings
The technical solutions of the embodiments of the present invention are further described in detail with reference to the accompanying drawings and embodiments.
FIG. 1 is a flowchart of a method for reducing power consumption of a chip according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a specific implementation manner for reducing power consumption of a chip according to an embodiment of the present invention.
Detailed Description
The invention is further illustrated by the following figures and specific examples, but it should be understood that these examples are for the purpose of illustration only and are not to be construed as in any way limiting the present invention, i.e., as in no way limiting its scope.
The embodiment of the invention provides a method for reducing chip power consumption, the main flow is shown in figure 1, and the method comprises the following steps:
specifically, the electric load comprises a standard cell (STDcell) and a Hard Macro (Hard Macro) in a chip module; the power consumption requirement of the power consumption load refers to the requirement of the power consumption load on power supply when the circuit module works normally.
specifically, according to the physical position of the electric load in the layout design, the actual driving capability of the switch unit may be combined to divide one or more standard cells and/or one or more hard macros that are physically adjacent to each other into a turn-off domain. This switch-off domain is thus controlled by a switching unit.
that is, one switch unit controls power supply to one area, and all switch units in one module are in parallel connection, and whether each switch unit supplies power to each turn-off area is controlled by driving of series control signals.
The switch unit, the standard unit and the hard macro are arranged in a horizontal position, and the position relation among the inserted switch unit, the hard macro and the standard unit meets the requirement of a design rule. Specifically, the method may include, for example: and whether the spacing between the switch unit and the hard macro and standard unit meets the specification of the minimum spacing, and the like.
the high-level power network is a power network which is used for connecting a power supply at one or two levels of the top level; the transition layer power supply network is specifically a power supply network of each layer between the high-layer power supply network and the bottom layer power supply network except the high-layer power supply network and the bottom layer power supply network; the bottom layer power supply network is connected with the transition layer power supply network; the bottom layer power supply network is a power supply network for connecting the standard unit and the hard macro in the chip module;
the stacked holes are used because there are multiple layers of media between the high-level power supply network and the switch unit, and similarly, there are multiple layers of media between the switch unit and the transition-level power supply network, and the common through holes cannot achieve the connection, so that stacked holes with a multilayer stacked structure are needed. The middle of the first stacking hole and the middle of the second stacking hole are filled with metal and have a conductive function, so that the power connection between the high-level power supply network and the switch unit is realized through the first stacking hole, and the power connection between the switch unit and the transition layer power supply network is realized through the second stacking hole.
And 150, switching on or switching off the connection between the standard unit and the hard macro and the power supply according to the received control signal by the switch unit.
The control signals are given by a Power Management Unit (PMU) which inputs the control signals to the individual switching units in each module, preferably in the form of series signals. One module is in the chip, and the internal electric load is consistent with the on-off, namely the control signal.
It should be noted that, after the switch units are introduced, the sum of the IR Drop (IR Drop) of each switch unit in a chip module and the chip module itself is less than 10% of the power supply operating voltage. IR drop is a phenomenon that indicates a voltage drop or rise on the power and ground networks present in an integrated circuit. As the width of the metal interconnection line becomes narrower and narrower as the semiconductor process progresses, the resistance value of the metal interconnection line rises, so that a certain IR drop exists in the whole chip range.
Further, the IR voltage drop of a switch unit is equal to the working current and the on-resistance R of the switch unitONThe product of (a). The working current can be calculated by the ratio of the power consumption and the working voltage of the chip module during workingAnd (5) obtaining the product.
Although it is considered theoretically that the sum of the IR Drop (IR Drop) of each switch unit and the chip module itself is less than 10% of the power supply operating voltage, and each switch unit is in a parallel relationship, it seems that the IR Drop is reduced when the number of the switch units is increased, and the requirement that the sum of the IR Drop (IR Drop) of the chip module itself is less than 10% of the power supply operating voltage can be satisfied, in actual operation, the loss caused by the leakage power consumption of the switch units needs to be considered, and those skilled in the art know how to handle the calculation of the leakage power consumption, and the detailed description is omitted here.
The method for realizing low power consumption of the invention is characterized in that the switch unit is added below the metal layer, the high-level power supply network is communicated with the switch unit through the first laminated hole, so that a power supply passage which is directly communicated is formed between the switch unit and the high-level power supply network, and the switch unit is communicated with the transition layer power supply network through the second laminated hole, so that the switch unit, the transition layer power supply network, a standard unit and a hard macro which are powered by the bottom layer power supply network form another power supply passage. Each switch unit controls a plurality of connected electric loads in the turn-off domain through the transition layer power supply network and the bottom layer power supply network.
Fig. 2 is a schematic diagram of a specific implementation method for reducing the power consumption of a chip.
In the structure shown in the figure, there are seven layers of metal power supply networks, wherein M7 (i.e. layer 7 metal layer) is a higher layer power supply network connected to the power supply of the chip module, M6-M3 are transition layer power supply networks, and M2 and M1 are bottom layer power supply networks directly supplying power to some standard cells (only 4 shown) and 1 hard macro.
The switch unit is connected with the M7 through the first laminated hole and is connected to the M6 through the second laminated hole, so that some standard units (only 4 in the figure) and 1 hard macro for supplying the M6 downwards can be turned on or off by controlling the switch unit.
In a chip module, there are a plurality of structures like this, each switch unit is controlled by control signal, when this chip module does not need to work, can control each switch unit in this chip module and cut off the power supply of the high-level power network to the transition layer power network, thus close this part of power consumption load.
According to the method for reducing the power consumption of the chip, the turn-off domain is controlled through the switch unit, so that when some modules in the chip do not need to participate in work, the switch unit can be controlled to turn off the power load in the corresponding turn-off domain, and the purpose of reducing the power consumption of the chip is achieved.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (6)
1. A method for reducing power consumption of a chip, the method comprising:
determining the power consumption requirement of a power consumption load in the chip module; the electric load comprises standard cells and Hard Macro Hard Macro in a chip module;
determining a plurality of turn-off domains according to the physical location of the electrical load; wherein each turn-off domain contains one or more standard cells and/or one or more hard macros;
according to the positions of the hard macro and the standard cell in the turn-off domain, correspondingly inserting a switch cell in the turn-off domain; the switch units, the standard units and the hard macros are arranged in a horizontal position, and the position relation among the inserted switch units, the hard macros and the standard units meets the requirement of a design rule;
establishing a first stacking hole between a high-level power supply network and the switch unit, and establishing a second stacking hole between the switch unit and a transition-level power supply network; the high-level power network is a power network with one or two layers at the top for connecting a power supply; the transition layer power supply network is specifically a power supply network of each layer between the high-layer power supply network and the bottom layer power supply network except the high-layer power supply network and the bottom layer power supply network; the bottom layer power supply network is connected with the transition layer power supply network; the bottom layer power supply network is a power supply network for connecting the standard unit and the hard macro in the chip module;
and the switch unit is connected or disconnected with the standard unit and the hard macro and the power supply according to the received control signal.
2. The method for reducing chip power consumption according to claim 1, wherein each switch unit in the one chip module is connected in parallel.
3. The method for reducing the power consumption of the chip according to claim 1, wherein the sum of the IR Drop of each switch unit in the chip module and the chip module is less than 10% of the operating voltage of the power supply.
4. The method for reducing chip power consumption according to claim 3, wherein the IR drop of one of the switch units is equal to the operating current and the on-resistance R of the switch unitONThe product of (a).
5. The method for reducing chip power consumption according to claim 4, wherein the operating current is obtained by calculating a ratio of power consumption to operating voltage when the chip module operates.
6. The method for reducing chip power consumption according to claim 1, wherein the switch unit is disposed below the underlying power network.
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| CN202111095072.5A CN113778216B (en) | 2021-09-17 | 2021-09-17 | Method for reducing chip power consumption |
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| CN202111095072.5A CN113778216B (en) | 2021-09-17 | 2021-09-17 | Method for reducing chip power consumption |
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