CN113765513B - Impedance correction circuit - Google Patents
Impedance correction circuit Download PDFInfo
- Publication number
- CN113765513B CN113765513B CN202010505553.8A CN202010505553A CN113765513B CN 113765513 B CN113765513 B CN 113765513B CN 202010505553 A CN202010505553 A CN 202010505553A CN 113765513 B CN113765513 B CN 113765513B
- Authority
- CN
- China
- Prior art keywords
- voltage
- control signal
- correction circuit
- transistor
- comparison result
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
The invention provides an impedance correction circuit. The impedance correction circuit includes a first correction circuit, a second correction circuit, and a control circuit. The first correction circuit is suitable for being coupled to the external resistor through the correction connecting pad and generates a first voltage according to the first control signal and the resistance value of the external resistor. The second correction circuit generates a second voltage according to the first control signal and the second control signal. The control circuit is used for comparing the first voltage with the reference voltage to obtain a first comparison result, comparing the first voltage with the second voltage to obtain a second comparison result, generating a first control signal according to the first comparison result, and generating a second control signal according to the second comparison result.
Description
Technical Field
The present invention relates to a memory device, and more particularly, to an impedance correction circuit.
Background
In the prior art, when the output impedance of the transmission line between the memory devices and the output impedance of the output circuit of the memory device cannot be matched with each other, the signal transmitted to the output circuit will have a problem of signal reflection, thereby affecting the quality of signal or data transmission between the memory devices.
Therefore, the memory device generally performs ZQ calibration operation to generate a control signal capable of optimizing the output impedance of the output circuit, so that the output circuit can precisely control the impedance value by the control signal, and the output impedance of the transmission line between the memory devices and the output impedance of the output circuit can be matched with each other. However, in the prior art, the correction must be performed on the pull-up circuit in the correction circuit to obtain the control signal for optimizing the pull-up circuit of the output circuit, and then the correction must be performed on the pull-down circuit in the correction circuit to obtain the control signal for optimizing the pull-down circuit of the output circuit.
In this case, the conventional memory device will take a long correction time when performing the ZQ correction operation, thereby affecting the operation quality of the memory device.
Disclosure of Invention
The invention provides an impedance correction circuit, which can simultaneously perform correction actions on a first correction circuit and a second correction circuit to obtain a control signal for optimizing the output impedance of an output circuit of a memory device, thereby effectively reducing the processing time of the impedance correction circuit.
The impedance correction circuit comprises a first correction circuit, a second correction circuit and a control circuit. The first correction circuit is suitable for being coupled to the external resistor through the correction connecting pad and generates a first voltage according to the first control signal and the resistance value of the external resistor. The second correction circuit generates a second voltage according to the first control signal and the second control signal. The control circuit is used for comparing the first voltage with the reference voltage to obtain a first comparison result, comparing the first voltage with the second voltage to obtain a second comparison result, generating a first control signal according to the first comparison result, and generating a second control signal according to the second comparison result.
Based on the above, the impedance correction circuit according to the embodiments of the present invention can correct the resistance value of the first transistor according to the first control signal by using the first correction circuit so that the resistance value of the first transistor is the same as the resistance value of the external resistor, and simultaneously correct the resistance values of the second and third transistors according to the first and second control signals by using the second correction circuit so that the resistance values of the second and third transistors can be the same as the resistance value of the external resistor. In this way, the impedance correction circuit can simultaneously provide the first control signal and the second control signal corresponding to the resistance values of the first transistor to the third transistor which are substantially the same as the resistance value of the external resistor to the output circuit of the memory device so as to optimize the output impedance of the output circuit and effectively reduce the processing time of the impedance correction circuit.
Drawings
FIG. 1 is a schematic circuit diagram of an impedance correction circuit according to an embodiment of the invention;
FIG. 2 is a timing diagram of control signals according to an embodiment of the invention;
FIG. 3 is a timing diagram of control signals according to another embodiment of the present invention;
fig. 4 is a partial circuit schematic diagram illustrating the impedance correction circuit shown in fig. 1 in accordance with another embodiment of the present invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 1 is a circuit diagram of an impedance correction circuit 100 according to an embodiment of the invention. Referring to fig. 1, the impedance correction circuit 100 includes correction circuits 110 and 120 and a control circuit 130. In this embodiment, the impedance correction circuit 100 may be provided in a memory device, and the control signals CODEP, CODEN generated by the impedance correction circuit 100 may be provided to an output circuit of the memory device to optimize an output impedance of the output circuit. Thus, the output impedance of the output circuit can be adjusted to an optimal value by the optimized control signals CODEP, CODEN.
In the present embodiment, the correction circuit 110 includes a transistor M1. The first end of the transistor M1 is coupled to the operating voltage VDD, and the second end of the transistor M1 is coupled to the external resistor RZQ through the correction pad ZQPAD. The correction circuit 110 can generate the voltage VZQ according to the control signal CODEP and the resistance value of the external resistor RZQ.
In the present embodiment, the correction circuit 120 includes a transistor M2 and a transistor M3. The first terminal of the transistor M2 is coupled to the operating voltage VDD, and the control terminal of the transistor M2 receives the control signal code. The first terminal of the transistor M3 is coupled to the ground voltage GND, the second terminal of the transistor M3 is coupled to the second terminal of the transistor M2, and the control terminal of the transistor M3 receives the control signal CODEN. The correction circuit 120 may generate the voltage VNZQ according to the control signal code and the control signal code.
It is particularly mentioned that the correction circuit 110 and the correction circuit 120 of the present embodiment may have substantially the same arrangement as the output circuit of the memory device, and the correction circuit 110 and the correction circuit 120 may have voltage-to-current characteristics equivalent to the output circuit of the memory device. The transistors M1 and M2 of the present embodiment may be P-type transistors, and the transistor M3 may be N-type transistors, but the present invention is not limited thereto. In addition, the external resistor RZQ of the present embodiment may have a resistance value that satisfies the requirement of the output circuit of the memory device.
On the other hand, the control circuit 130 is coupled to the calibration pad ZQPAD and the calibration circuit 120. In the present embodiment, the control circuit 130 includes comparators 131, 132 and an arithmetic circuit 133. The first input (i.e., the non-inverting input) of the comparator 131 is coupled to the calibration pad ZQPAD to receive the voltage VZQ, and the second input (i.e., the inverting input) of the comparator 131 receives the reference voltage VREF. Moreover, the comparator 131 can generate the comparison result COMP1 at its output terminal by comparing the voltage VZQ with the reference voltage VREF. The voltage value of the reference voltage VREF of the present embodiment may be set to be half of the voltage value of the operating voltage VDD, but the present invention is not limited thereto.
A first input (i.e., a non-inverting input) of the comparator 132 is coupled to the calibration circuit 120 for receiving the voltage VNZQ, and a second input (i.e., an inverting input) of the comparator 132 is coupled to the calibration pad ZQPAD for receiving the voltage VZQ. Moreover, the comparator 132 can generate the comparison result COMP2 at its output by comparing the voltage VZQ with the voltage VNZQ.
On the other hand, the operation circuit 133 is coupled to the output terminal of the comparator 131 and the output terminal of the comparator 132 to receive the comparison result COMP1 and the comparison result COMP2, respectively. Furthermore, the operation circuit 133 may generate the control signal code according to the comparison result COMP1 and generate the control signal code according to the comparison result COMP2.
Regarding the operation details of the impedance correction circuit 100, specifically, the impedance correction circuit 100 of the present embodiment has a correction pad ZQPAD for performing ZQ correction operation. Since the calibration pad ZQPAD can be coupled to the ground voltage GND through the external resistor RZQ, and the transistor M1 of the calibration circuit 110 is disposed between the operating voltage VDD and the calibration pad ZQPAD, the calibration circuit 110 can adjust the voltage value of the voltage VZQ on the calibration pad ZQPAD to be half of the voltage value of the operating voltage VDD according to the control signal code, so that the resistance value of the transistor M1 can be substantially equal (or approximately) to the resistance value of the external resistor RZQ.
Further, when the comparator 131 generates the comparison result COMP1 indicating that the voltage value of the voltage VZQ is not equal to the voltage value of the reference voltage VREF (i.e., half of the voltage value of the operating voltage VDD) by comparing the voltage VZQ with the reference voltage VREF, it indicates that the resistance value of the transistor M1 is not equal to (or approximately equal to) the resistance value of the external resistor RZQ. At this time, the operation circuit 133 further calculates the control signal code corresponding to the half of the voltage value of the operating voltage VDD by performing a Binary Search (Binary Search) according to the comparison result COMP1, so as to equalize (or approximate) the voltage value of the voltage VZQ on the correction pad ZQPAD.
In detail, assuming that the control signal code of the present embodiment is represented in a binary form of 7 bits, when the comparator 131 generates the comparison result COMP1 indicating that the voltage value of the voltage VZQ is not equal to the voltage value of the reference voltage VREF, the operation circuit 133 can adjust a plurality of bits of the control signal code bit by bit according to the voltage value of the current comparison result COMP1.
For example, when the impedance correction circuit 100 determines that the voltage difference between the voltage VZQ and the reference voltage VREF is larger according to the comparison result COMP1, the operation circuit 133 can adjust the most significant bit (Most Significant Bit, MSB) of the control signal code and provide the adjusted control signal code to the correction circuit 110. Then, the correction circuit 110 can adjust the voltage value of the voltage VZQ to be higher or lower by a relatively larger adjustment range according to the adjusted control signal CODEP, so that the voltage value of the voltage VZQ can be close to the voltage value of the reference voltage VREF.
In contrast, when the impedance correction circuit 100 determines that the voltage difference between the voltage VZQ and the reference voltage VREF is smaller according to the comparison result COMP1, the operation circuit 133 may adjust the least significant bit (Least Significant Bit, LSB) of the control signal code and provide the adjusted control signal code to the correction circuit 110. Then, the correction circuit 110 can adjust the voltage value of the voltage VZQ to be higher or lower by a relatively smaller adjustment range according to the adjusted control signal CODEP, so that the voltage value of the voltage VZQ can be substantially equal to (or similar to) the voltage value of the reference voltage VREF.
In other words, in the case that the voltage VZQ is not substantially equal to (or approximates) the voltage of the reference voltage VREF, the operation circuit 133 of the present embodiment can adjust the control signal code from the high bit to the low bit according to the comparison result COMP1 in sequence according to the voltage difference between the voltage VZQ and the reference voltage VREF, so that the correction circuit 110 can fine-adjust the voltage VZQ on the correction pad ZQPAD according to the adjusted control signal code until the correction circuit 110 can substantially equal (or approximates) the voltage VZQ to the voltage of the reference voltage VREF (i.e. the resistance of the transistor M1 is substantially equal to (or approximates) the resistance of the external resistor RZQ according to the adjusted control signal code.
It should be noted that, when the voltage value of the voltage VZQ is steadily close to the voltage value of the reference voltage VREF, the operation circuit 133 fixes the control signal code under the state, and provides the control signal code corresponding to the state to the transistor M1 of the correction circuit 110 and the transistor M2 of the correction circuit 120, so as to fix the resistance values of the transistor M1 and the transistor M2, such that the resistance values of the transistor M1 and the transistor M2 are fixed at the resistance value of the external resistor RZQ.
On the other hand, in the correction circuit 120, since the transistor M2 and the transistor M3 are serially coupled between the operating voltage VDD and the ground voltage GND, the correction circuit 120 can adjust the voltage value of the voltage VNZQ at the node P1 to be half of the voltage value of the operating voltage VDD according to the control signal code and the control signal code, so that the resistance value of the transistor M3 can be substantially equal (or similar) to the resistance value of the transistor M2.
In detail, while the operation circuit 133 fixes the state of the control signal CODEP so that the transistor M1 and the transistor M2 can be commonly adjusted to have the same resistance value as the external resistor RZQ according to the control signal CODEP, the comparator 132 further generates the comparison result COMP2 by comparing the voltage VZQ on the correction pad ZQPAD and the voltage VNZQ on the node P1.
Further, when the comparator 132 generates the comparison result COMP2 indicating that the voltage value of the voltage VNZQ is not equal to the voltage value of the voltage VZQ (i.e., half of the voltage value of the operating voltage VDD) by comparing the voltage VZQ with the voltage VNZQ, it indicates that the resistance value of the transistor M3 is not equal to (or similar to) the resistance value of the transistor M2. At this time, the operation circuit 133 further calculates the generation control signal CODEN corresponding to the voltage value of the voltage VNZQ that can be equal to (or approximate to) the voltage value of the voltage VZQ by performing the binary search according to the comparison result COMP2.
Specifically, assuming that the control signal code of the present embodiment is represented in a binary form of 7 bits, when the comparator 132 generates the comparison result COMP2 indicating that the voltage value of the voltage VNZQ is not equal to the voltage value of the voltage VZQ, the arithmetic circuit 133 may adjust a plurality of bits of the control signal code bit by bit according to the voltage value of the current comparison result COMP2.
For example, when the impedance correction circuit 100 determines that the voltage difference between the voltage VNZQ and the voltage VZQ is larger according to the comparison result COMP2, the operation circuit 133 may adjust the most significant bit of the control signal CODEN and provide the adjusted control signal CODEN to the transistor M3 of the correction circuit 120. Then, the transistor M3 can adjust the voltage value of the voltage VNZQ with a relatively large adjustment range according to the adjusted control signal CODEN, so that the voltage value of the voltage VNZQ can be approximated to the voltage value of the voltage VZQ.
In contrast, when the impedance correction circuit 100 determines that the voltage difference between the voltage VNZQ and the voltage VZQ is smaller according to the comparison result COMP2, the operation circuit 133 may adjust the least significant bit of the control signal CODEN and provide the adjusted control signal CODEN to the transistor M3 of the correction circuit 120. Then, the transistor M3 can adjust the voltage value of the voltage VNZQ with a relatively small adjustment range according to the adjusted control signal CODEN, so that the voltage value of the voltage VNZQ can be substantially equal to (or approximately equal to) the voltage value of the voltage VZQ.
In other words, in the case that the voltage value of the voltage VNZQ is not substantially equal to (or approximates to) the voltage value of the voltage VZQ, the operation circuit 133 of the present embodiment can adjust the control signal code from high to low according to the comparison result COMP2 in sequence, so that the correction circuit 120 can fine-tune the voltage VNZQ on the node P1 according to the adjusted control signal code and the control signal code until the correction circuit 120 can substantially equal (or approximates) the voltage value of the voltage VNZQ to the voltage value of the voltage VZQ (i.e. the resistance value of the transistor M3 is adjusted to be substantially equal to (or approximates to) the resistance value of the transistor M2) according to the adjusted control signal code and the control signal code.
Specifically, when the voltage VNZQ is steadily close to the voltage VZQ, the operation circuit 133 fixes the control signal code in this state, and provides the control signal code corresponding to this state to the transistor M3 of the correction circuit 120, so as to fix the resistance of the transistor M3, such that the transistor M2 is fixed at the resistance of the external resistor RZQ.
In this regard, please refer to fig. 1 and fig. 2 simultaneously, fig. 2 is a timing diagram of control signals code p and code n according to an embodiment of the present invention. In the present embodiment, the impedance correction circuit 100 may generate the Clock signal ZQCLK through an external Clock Generator (Clock Generator) or an Oscillator (Oscillator) (not shown). Also, the impedance correction circuit 100 may perform ZQ correction operation according to the timing state of the clock signal ZQCLK.
Specifically, the impedance correction circuit 100 may start performing the ZQ correction operation after the memory device performs the set period for completing the ZQ correction operation. In the embodiment of fig. 1 and 2, the voltage VZQ on the correction pad ZQPAD is commonly received by the first input (i.e., the non-inverting input) of the comparator 131 and the second input (i.e., the inverting input) of the comparator 132. Therefore, under some design requirements (in some embodiments), the comparator 131 and the comparator 132 can generate the comparison result COMP1 and the comparison result COMP2 at the same time, so that the operation circuit 133 can adjust a plurality of bits of the control signals COMP and CODEN through binary search according to the voltage values of the comparison results COMP1 and COMP2 at the same time.
In this case, the impedance correction circuit 100 of the present embodiment can perform the correction operation on the transistor M1 of the correction circuit 110 and the transistors M2 and M3 of the correction circuit 120 at the same time, so that the resistance values of the transistors M1 to M3 can be substantially equal (or approximate) to the resistance value of the external resistor RZQ according to the adjusted control signals CODEN and CODEP, thereby effectively reducing the processing time of the impedance correction circuit 100. Meanwhile, the impedance correction circuit 100 can provide the control signals CODEN and CODEP corresponding to the resistance values of the transistors M1 to M3 and the external resistor RZQ to the output circuit of the memory device to optimize the output impedance of the output circuit.
Fig. 3 is a timing diagram of control signals CODEP, CODEN according to another embodiment of the present invention. Referring to fig. 1 and fig. 3, in the present embodiment, since the correction circuit 120 needs to adjust the voltage VNZQ to the voltage VZQ according to the adjusted control signal CODEN, the resistance of the transistor M3 can be substantially the same as the resistance of the transistor M2, and therefore, when the voltage of the voltage VZQ is changed, the voltage of the voltage VNZQ is likely to be adjusted to some extent.
In this case, in the correction circuit 120, the voltage difference between the second terminal (i.e., the drain terminal) and the first terminal (i.e., the source terminal) of the transistor M3 may be affected by the voltage value variation of the voltage VNZQ, so that the setting value of the voltage difference may be incorrect, thereby affecting that the transistor M3 cannot operate in the linear region.
Therefore, under other design requirements (in other embodiments), the operation circuit 133 of the present embodiment may perform the ZQ correction operation by generating the control signal code after delay (for example, the control signal code is generated continuously until the most significant bit and the 6 th bit of the control signal code are output, but the present invention is not limited thereto), and correcting the resistance values of the transistors M1 and M2 first and then correcting the resistance value of the transistor M3.
Similarly, the impedance correction circuit 100 can also provide the control signals CODEN and CODEP corresponding to the resistances of the transistors M1 to M3 being substantially equal (or similar) to the resistance of the external resistor RZQ to the output circuit of the memory device to optimize the output impedance of the output circuit.
Fig. 4 is a partial circuit schematic diagram illustrating the impedance correction circuit 100 shown in fig. 1 according to another embodiment of the present invention. Referring to fig. 1 and 4, the impedance correction circuit 100 shown in fig. 1 may further include a signal format converter 440. The signal format converter 440 of the present embodiment may be a digital-to-analog converter (Digital to analog converter, DAC).
In this embodiment, the signal format converter 440 may be coupled to the arithmetic circuit 133 to receive the control signals CODEP, CODEN. Unlike the embodiment of fig. 1, in the present embodiment, after the arithmetic circuit 133 performs the completion of the binary search, the signal format converter 440 may convert the control signal codec having a digital form into the control signal AP having an analog form and generate the control signal AP to the transistor M1 of the correction circuit 110 and the transistor M2 of the correction circuit 120. In contrast, the signal format converter 440 may convert the control signal codec having a digital form into the control signal AN having AN analog form and generate the control signal AN to the transistor M3 of the correction circuit 120.
Therefore, in the present embodiment, the correction circuit 110 can adjust the voltage value of the voltage VZQ according to the control signal AP and the resistance value of the external resistor RZQ, and the correction circuit 120 can adjust the voltage value of the voltage VNZQ according to the control signals AP and AN.
Details of the operation circuit 133 for adjusting the bits of the control signals CODEP and CODEN by binary search can be analogized with reference to the related description of the embodiment of FIG. 1, and thus will not be repeated.
In summary, the impedance correction circuit of the present invention can correct the resistance value of the first transistor according to the first control signal by using the first correction circuit so that the resistance value of the first transistor is the same as the resistance value of the external resistor, and simultaneously correct the resistance values of the second and third transistors according to the first and second control signals by using the second correction circuit so that the resistance values of the second and third transistors can be the same as the resistance value of the external resistor. In this way, the impedance correction circuit can simultaneously provide the first control signal and the second control signal corresponding to the resistance values of the first transistor to the third transistor which are substantially the same as the resistance value of the external resistor to the output circuit of the memory device so as to optimize the output impedance of the output circuit and effectively reduce the processing time of the impedance correction circuit.
Claims (10)
1. An impedance correction circuit, comprising:
the first correction circuit is suitable for being coupled to the external resistor through the correction connecting pad and generating a first voltage according to a first control signal and the resistance value of the external resistor;
the second correction circuit generates a second voltage according to the first control signal and the second control signal; and
the control circuit is used for comparing the first voltage with a reference voltage to obtain a first comparison result, comparing the first voltage with the second voltage to obtain a second comparison result, generating the first control signal according to the first comparison result and generating the second control signal according to the second comparison result.
2. The impedance correction circuit of claim 1, wherein the first correction circuit comprises:
the first transistor has a first end coupled to an operating voltage, a second end coupled to the calibration pad, and a control end receiving the first control signal and adjusting a resistance value of the first transistor according to the first control signal.
3. The impedance correction circuit of claim 2, wherein the second correction circuit comprises:
the first end of the second transistor is coupled to the operating voltage, and the control end of the second transistor receives the first control signal and adjusts the resistance value of the second transistor according to the first control signal; and
and the first end of the third transistor is coupled to the ground voltage, the second end of the third transistor is coupled to the second end of the second transistor, and the control end of the third transistor receives the second control signal and adjusts the resistance value of the third transistor according to the second control signal.
4. The impedance correction circuit of claim 3 wherein the first transistor and the second transistor are P-type transistors and the third transistor is an N-type transistor.
5. The impedance correction circuit of claim 1, wherein the voltage value of the reference voltage is half the voltage value of the operating voltage.
6. The impedance correction circuit of claim 1, wherein the control circuit comprises:
a first comparator, a first input end of which receives the first voltage and a second input end of which receives the reference voltage, so as to generate the first comparison result at the output end of the first comparator;
a second comparator, a first input end of which receives the second voltage and a second input end of which receives the first voltage, so as to generate the second comparison result at an output end of the second comparator;
the operation circuit receives the first comparison result and the second comparison result, generates the first control signal according to the first comparison result, and generates the second control signal according to the second comparison result.
7. The impedance correction circuit of claim 6, wherein the operation circuit is configured to perform a binary search to generate the first control signal according to the first comparison result and to generate the second control signal according to the second comparison result.
8. The impedance correction circuit of claim 7, wherein the operation circuit sequentially adjusts the plurality of bits of the first control signal bit by bit according to the voltage value of the first comparison result and adjusts the plurality of bits of the second control signal bit by bit according to the voltage value of the second comparison result.
9. The impedance correction circuit of claim 1, further comprising:
and a signal format converter coupled to the control circuit and configured to format-convert the first control signal and the second control signal.
10. The impedance correction circuit of claim 9 wherein the signal format converter is a digital-to-analog converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010505553.8A CN113765513B (en) | 2020-06-05 | 2020-06-05 | Impedance correction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010505553.8A CN113765513B (en) | 2020-06-05 | 2020-06-05 | Impedance correction circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113765513A CN113765513A (en) | 2021-12-07 |
| CN113765513B true CN113765513B (en) | 2023-10-13 |
Family
ID=78784935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010505553.8A Active CN113765513B (en) | 2020-06-05 | 2020-06-05 | Impedance correction circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113765513B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007110615A (en) * | 2005-10-17 | 2007-04-26 | Elpida Memory Inc | Calibration circuit and semiconductor device with its circuit |
| CN1980057A (en) * | 2005-12-01 | 2007-06-13 | 瑞昱半导体股份有限公司 | Impedance matching device and method for output drive circuit |
| CN101145769A (en) * | 2006-09-13 | 2008-03-19 | 联发科技股份有限公司 | Calibration circuit for resistance component |
| US7459930B2 (en) * | 2006-11-14 | 2008-12-02 | Micron Technology, Inc. | Digital calibration circuits, devices and systems including same, and methods of operation |
| CN102045054A (en) * | 2009-10-13 | 2011-05-04 | 晨星软件研发(深圳)有限公司 | Method and related device for correcting output/input circuit |
| CN103312293A (en) * | 2012-03-15 | 2013-09-18 | 瑞昱半导体股份有限公司 | Impedance correction device and impedance correction method |
| CN104935321A (en) * | 2014-03-18 | 2015-09-23 | 扬智科技股份有限公司 | Input-output impedance correction circuit and method thereof |
| TW201740376A (en) * | 2016-05-11 | 2017-11-16 | 三星電子股份有限公司 | Impedance calibration circuit of semiconductor memory device, semiconductor memory device and method of operating the same |
-
2020
- 2020-06-05 CN CN202010505553.8A patent/CN113765513B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007110615A (en) * | 2005-10-17 | 2007-04-26 | Elpida Memory Inc | Calibration circuit and semiconductor device with its circuit |
| CN1980057A (en) * | 2005-12-01 | 2007-06-13 | 瑞昱半导体股份有限公司 | Impedance matching device and method for output drive circuit |
| CN101145769A (en) * | 2006-09-13 | 2008-03-19 | 联发科技股份有限公司 | Calibration circuit for resistance component |
| US7459930B2 (en) * | 2006-11-14 | 2008-12-02 | Micron Technology, Inc. | Digital calibration circuits, devices and systems including same, and methods of operation |
| CN102045054A (en) * | 2009-10-13 | 2011-05-04 | 晨星软件研发(深圳)有限公司 | Method and related device for correcting output/input circuit |
| CN103312293A (en) * | 2012-03-15 | 2013-09-18 | 瑞昱半导体股份有限公司 | Impedance correction device and impedance correction method |
| CN104935321A (en) * | 2014-03-18 | 2015-09-23 | 扬智科技股份有限公司 | Input-output impedance correction circuit and method thereof |
| TW201740376A (en) * | 2016-05-11 | 2017-11-16 | 三星電子股份有限公司 | Impedance calibration circuit of semiconductor memory device, semiconductor memory device and method of operating the same |
Non-Patent Citations (2)
| Title |
|---|
| 一款阻抗自校正5Gbit/s大摆幅电压模发送器;陈玉虎;周玉梅;张锋;;半导体技术(05);全文 * |
| 一种高频阻抗匹配自校准电路;尹勇生;赵鹏程;邓红辉;储松;;微电子学(03);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113765513A (en) | 2021-12-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7990184B2 (en) | Comparing device having hysteresis characteristics and voltage regulator using the same | |
| CN110266294B (en) | Duty ratio correction circuit | |
| US6888482B1 (en) | Folding analog to digital converter capable of calibration and method thereof | |
| US7002500B2 (en) | Circuit, apparatus and method for improved current distribution of output drivers enabling improved calibration efficiency and accuracy | |
| JP2007123987A (en) | Zq calibration circuit and semiconductor device having the same | |
| US10884674B2 (en) | Semiconductor memory device | |
| US20100188116A1 (en) | Impedance adjusting circuit | |
| US9048814B2 (en) | Resistance adjusting circuit and resistance adjusting method | |
| US7084663B2 (en) | Impedance adjustment circuit, impedance adjustment method, and semiconductor device | |
| US11296698B2 (en) | Impedance calibration circuit | |
| US20080001668A1 (en) | Impedance control device and impedance control method | |
| CN113765513B (en) | Impedance correction circuit | |
| US8669897B1 (en) | Asynchronous successive approximation register analog-to-digital converter and operating method thereof | |
| CN112187261B (en) | Digital-to-analog converter and compensation circuit | |
| TWI777464B (en) | Signal converting apparatus and signal converting method | |
| US11283447B2 (en) | Impedance calibration circuit | |
| CN107346959B (en) | Operational amplifier for correcting offset voltage aiming at output working point | |
| US20110032128A1 (en) | Analog-digital converter circuit and calibration method | |
| JP2004032721A (en) | Method for preparing control signal for impedance matching and its circuit | |
| TWI723887B (en) | Impedance calibration circuit | |
| CN114499459A (en) | Electronic equipment and signal driving chip thereof | |
| JPH09261035A (en) | Cmos device | |
| KR20230119098A (en) | Impedance calibration circuit | |
| TWI742694B (en) | Impedance calibration circuit | |
| CN113810041A (en) | Impedance correction circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |