CN113765513B - Impedance correction circuit - Google Patents

Abstract

The invention provides an impedance correction circuit. The impedance correction circuit includes a first correction circuit, a second correction circuit, and a control circuit. The first correction circuit is suitable for being coupled to the external resistor through the correction connecting pad and generates a first voltage according to the first control signal and the resistance value of the external resistor. The second correction circuit generates a second voltage according to the first control signal and the second control signal. The control circuit is used for comparing the first voltage with the reference voltage to obtain a first comparison result, comparing the first voltage with the second voltage to obtain a second comparison result, generating a first control signal according to the first comparison result, and generating a second control signal according to the second comparison result.

Description

Impedance correction circuit

Technical field

The present invention relates to a memory device, and in particular to an impedance correction circuit.

Background technique

In existing memory technology, when the output impedance of the transmission line between the memory devices and the output impedance of the output circuit of the memory device cannot match each other, the signal transmitted to the output circuit will suffer from signal reflection, thereby affecting the memory. The quality of signal or data transmission between devices.

Therefore, the memory device usually performs a ZQ correction operation to generate a control signal that can optimize the output impedance of the output circuit, so that the output circuit can accurately control the impedance value through this control signal and improve the transmission line between the memory devices. The output impedance of the circuit and the output impedance of the output circuit can match each other. However, in the prior art, the pull-up circuit in the correction circuit must first be calibrated to obtain the control signal for optimizing the pull-up circuit of the output circuit, and then the pull-down circuit in the correction circuit can be calibrated. To obtain the control signal for the pull-down circuit to optimize the output circuit.

In this case, when the existing memory device performs the ZQ calibration operation, it will take a long calibration time, thereby affecting the operation quality of the memory device.

Contents of the invention

The present invention provides an impedance correction circuit that can simultaneously perform correction operations on a first correction circuit and a second correction circuit to obtain a control signal for optimizing the output impedance of an output circuit of a memory device, thereby effectively reducing the impedance correction circuit processing time.

The impedance correction circuit of the present invention includes a first correction circuit, a second correction circuit and a control circuit. The first correction circuit is adapted to be coupled to the external resistor through the correction pad, and generate the first voltage according to the first control signal and the resistance value of the external resistor. The second correction circuit generates a second voltage according to the first control signal and the second control signal. The control circuit is used to compare the first voltage and the reference voltage to obtain a first comparison result, and to compare the first voltage and the second voltage to obtain a second comparison result, and to generate a first control signal according to the first comparison result, and to generate a first control signal according to the first comparison result. The second comparison result is used to generate a second control signal.

Based on the above, the impedance correction circuit according to the embodiments of the present invention can use the first correction circuit to correct the resistance value of the first transistor according to the first control signal, so that the resistance value of the first transistor is the same as the resistance value of the external resistor, and At the same time, the second correction circuit is used to correct the resistance values of the second and third transistors according to the first and second control signals, so that the resistance values of the second and third transistors can also be the same as the resistance values of the external resistors. In this way, the impedance correction circuit can simultaneously provide the first and second control signals corresponding to the resistance values of the first to third transistors that are substantially the same as the resistance values of the external resistor to the output circuit of the memory device, so as to optimally This reduces the output impedance of the output circuit and effectively reduces the processing time of the impedance correction circuit.

Description of the drawings

Figure 1 is a circuit schematic diagram of an impedance correction circuit according to an embodiment of the present invention;

Figure 2 is a timing diagram of control signals according to an embodiment of the present invention;

Figure 3 is a timing diagram of a control signal according to another embodiment of the present invention;

FIG. 4 is a partial circuit diagram illustrating the impedance correction circuit shown in FIG. 1 according to another embodiment of the present invention.

Detailed ways

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numbers are used in the drawings and description to refer to the same or similar parts.

FIG. 1 is a schematic circuit diagram of an impedance correction circuit 100 according to an embodiment of the present invention. Referring to FIG. 1 , the impedance correction circuit 100 includes correction circuits 110 and 120 and a control circuit 130 . In this embodiment, the impedance correction circuit 100 may be disposed in a memory device, and the control signals CODEP and CODEN generated by the impedance correction circuit 100 may be provided to the output circuit of the memory device to optimize the output circuit. Output impedance. Thereby, the output impedance of the output circuit can be adjusted to the optimal value through the optimized control signals CODEP and CODEN.

In this embodiment, the correction circuit 110 includes a transistor M1. The first terminal of the transistor M1 is coupled to the operating voltage VDD, and the second terminal of the transistor M1 is coupled to the external resistor RZQ through the calibration pad ZQPAD. The correction circuit 110 can generate the voltage VZQ according to the control signal CODEP and the resistance value of the external resistor RZQ.

In this embodiment, the correction circuit 120 includes a transistor M2 and a transistor M3. The first terminal of the transistor M2 is coupled to the operating voltage VDD, and the control terminal of the transistor M2 receives the control signal CODEP. The first terminal of the transistor M3 is coupled to the ground voltage GND, the second terminal of the transistor M3 is coupled to the second terminal of the transistor M2, and the control terminal of the transistor M3 receives the control signal CODEN. The correction circuit 120 may generate the voltage VNZQ according to the control signal CODEP and the control signal CODEN.

In particular, the correction circuit 110 and the correction circuit 120 of this embodiment may have substantially the same configuration as the output circuit of the memory device, and the correction circuit 110 and the correction circuit 120 may have configurations equivalent to the output circuit of the memory device. Voltage versus current characteristics. The transistor M1 and the transistor M2 in this embodiment may be implemented as P-type transistors, and the transistor M3 may be implemented as an N-type transistor, but the invention is not limited thereto. In addition, the external resistor RZQ of this embodiment may have a resistance value that meets the requirements of the output circuit of the memory device.

On the other hand, the control circuit 130 is coupled to the calibration pad ZQPAD and the calibration circuit 120 . In this embodiment, the control circuit 130 includes comparators 131 and 132 and an operation circuit 133. The first input terminal (that is, the non-inverting input terminal) of the comparator 131 is coupled to the calibration pad ZQPAD to receive the voltage VZQ, and the second input terminal (that is, the inverting input terminal) of the comparator 131 receives the reference voltage VREF. Furthermore, the comparator 131 can generate a comparison result COMP1 at its output terminal by comparing the voltage VZQ and the reference voltage VREF. The voltage value of the reference voltage VREF in this embodiment can be set to half of the voltage value of the operating voltage VDD, but the invention is not limited thereto.

The first input terminal (ie, the non-inverting input terminal) of the comparator 132 is coupled to the correction circuit 120 to receive the voltage VNZQ, and the second input terminal (ie, the inverting input terminal) of the comparator 132 is coupled to Calibrate pad ZQPAD to receive voltage VZQ. Furthermore, the comparator 132 can generate a comparison result COMP2 at its output terminal by comparing the voltage VZQ and the voltage VNZQ.

On the other hand, the operation circuit 133 is coupled to the output terminal of the comparator 131 and the output terminal of the comparator 132 to receive the comparison result COMP1 and the comparison result COMP2 respectively. Furthermore, the operation circuit 133 can generate the control signal CODEP according to the comparison result COMP1, and generate the control signal CODEN according to the comparison result COMP2.

Regarding the operation details of the impedance correction circuit 100, specifically, the impedance correction circuit 100 of this embodiment has a correction pad ZQPAD for performing a ZQ correction operation. Since the correction pad ZQPAD can be coupled to the ground voltage GND through the external resistor RZQ, and the transistor M1 of the correction circuit 110 is disposed between the operating voltage VDD and the correction pad ZQPAD, the correction circuit 110 can be based on the control signal CODEP. The voltage value of the voltage VZQ on the correction pad ZQPAD is adjusted to half of the voltage value of the operating voltage VDD, so that the resistance value of the transistor M1 can be substantially equal to (or approximately) the resistance value of the external resistor RZQ.

Furthermore, when the comparator 131 compares the voltage VZQ and the reference voltage VREF to generate a comparison result COMP1 indicating that the voltage value of the voltage VZQ is not equal to the voltage value of the reference voltage VREF (that is, half of the voltage value of the operating voltage VDD) , it means that the resistance value of the transistor M1 is not yet equal (or approximately) to the resistance value of the external resistor RZQ. At this time, the operation circuit 133 will further calculate a voltage that can make the voltage value of the voltage VZQ on the correction pad ZQPAD equal (or approximate) to the operating voltage VDD by performing a binary search based on the comparison result COMP1. The control signal CODEP corresponding to half the value.

In detail, assuming that the control signal CODEP of this embodiment is expressed in a 7-bit binary form, when the comparator 131 generates a comparison result COMP1 indicating that the voltage value of the voltage VZQ is not equal to the voltage value of the reference voltage VREF, the operation The circuit 133 can adjust multiple bits of the control signal CODEP bit by bit based on the voltage value of the current comparison result COMP1.

For example, when the impedance correction circuit 100 determines that the voltage difference between the voltage VZQ and the reference voltage VREF is relatively large based on the comparison result COMP1, the operation circuit 133 can adjust the Most Significant Bit of the control signal CODEP. MSB), and provides the adjusted control signal CODEP to the correction circuit 110 . Then, the correction circuit 110 can adjust the voltage value of the voltage VZQ with a relatively large adjustment range according to the adjusted control signal CODEP, so that the voltage value of the voltage VZQ can be close to the voltage value of the reference voltage VREF.

In contrast, when the impedance correction circuit 100 determines that the voltage difference between the voltage VZQ and the reference voltage VREF is small based on the comparison result COMP1, the operation circuit 133 can adjust the Least Significant Bit (LSB) of the control signal CODEP. , and provide the adjusted control signal CODEP to the correction circuit 110 . Then, the correction circuit 110 can adjust the voltage value of the voltage VZQ with a relatively small adjustment range according to the adjusted control signal CODEP, so that the voltage value of the voltage VZQ can be substantially equal to (or approximately) the reference value. The voltage value of voltage VREF.

In other words, when the voltage value of voltage VZQ is not substantially equal (or approximately) to the voltage value of reference voltage VREF, the operation circuit 133 of this embodiment can determine the voltage difference between voltage VZQ and reference voltage VREF. The control signal CODEP is adjusted from the high bit to the low bit according to the comparison result COMP1 in sequence, so that the correction circuit 110 can fine-tune the voltage VZQ on the correction pad ZQPAD according to the adjusted control signal CODEP until the correction circuit 110 can adjust the voltage VZQ on the correction pad ZQPAD according to the adjusted control signal CODEP. The adjusted control signal CODEP makes the voltage value of the voltage VZQ substantially equal to (or approximately) the voltage value of the reference voltage VREF (that is, the resistance value of the transistor M1 is adjusted to be substantially equal to (or approximately) the value of the external resistor RZQ resistance value).

It is worth mentioning that when the voltage value of voltage VZQ is stably close to the voltage value of reference voltage VREF, the operation circuit 133 will fix the control signal CODEP in this state and provide the corresponding control signal CODEP in this state to The transistor M1 of the correction circuit 110 and the transistor M2 of the correction circuit 120 thereby fix the resistance values of the transistor M1 and the transistor M2, so that the resistance values of the transistor M1 and the transistor M2 are fixed by the resistance value of the external resistor RZQ.

On the other hand, in the correction circuit 120, since the transistor M2 and the transistor M3 are coupled in series between the operating voltage VDD and the ground voltage GND, the correction circuit 120 can change the node P1 according to the control signal CODEP and the control signal CODEN. The voltage value of the voltage VNZQ is adjusted to half of the voltage value of the operating voltage VDD, so that the resistance value of the transistor M3 can be substantially equal to (or approximately) the resistance value of the transistor M2.

Specifically, while the operation circuit 133 fixes the state of the control signal CODEP so that the transistor M1 and the transistor M2 can be adjusted to the same resistance value as the external resistor RZQ based on the control signal CODEP, the comparator 132 will further The comparison result COMP2 is generated by comparing the voltage VZQ on the correction pad ZQPAD and the voltage VNZQ on the node P1.

Further, when the comparator 132 generates a comparison result COMP2 indicating that the voltage value of the voltage VNZQ is not equal to the voltage value of the voltage VZQ (that is, half of the voltage value of the operating voltage VDD) by comparing the voltage VZQ and the voltage VNZQ, It means that the resistance value of transistor M3 is not yet equal (or approximately) to the resistance value of transistor M2. At this time, the operation circuit 133 will perform a binary search based on the comparison result COMP2 to further calculate the generated control signal CODEN that can make the voltage value of voltage VNZQ equal to (or approximate) the voltage value of voltage VZQ.

Specifically, assuming that the control signal CODEN of this embodiment is expressed in a 7-bit binary form, when the comparator 132 generates a comparison result COMP2 indicating that the voltage value of the voltage VNZQ is not equal to the voltage value of the voltage VZQ, the operation circuit 133 can adjust multiple bits of the control signal CODEN bit by bit based on the voltage value of the current comparison result COMP2.

For example, when the impedance correction circuit 100 determines that the voltage difference between the voltage VNZQ and the voltage VZQ is relatively large based on the comparison result COMP2, the operation circuit 133 can adjust the most significant bit of the control signal CODEN, and adjust the adjusted The control signal CODEN is provided to the transistor M3 of the correction circuit 120 . Then, the transistor M3 can adjust the voltage value of the voltage VNZQ with a relatively large adjustment range according to the adjusted control signal CODEN, so that the voltage value of the voltage VNZQ can be close to the voltage value of the voltage VZQ.

In contrast, when the impedance correction circuit 100 determines that the voltage difference between the voltage VNZQ and the voltage VZQ is small based on the comparison result COMP2, the operation circuit 133 can adjust the least significant bit of the control signal CODEN and use the adjusted control signal CODEN is provided to transistor M3 of correction circuit 120 . Then, the transistor M3 can adjust the voltage value of the voltage VNZQ with a relatively small adjustment range according to the adjusted control signal CODEN, so that the voltage value of the voltage VNZQ can be substantially equal to (or approximately) the voltage VZQ. voltage value.

In other words, when the voltage value of voltage VNZQ is not substantially equal (or approximately) to the voltage value of voltage VZQ, the operation circuit 133 of this embodiment can determine the voltage value according to the voltage difference between voltage VNZQ and voltage VZQ. In sequence, the control signal CODEN is adjusted from the high bit to the low bit according to the comparison result COMP2, so that the correction circuit 120 can finely adjust the voltage VNZQ at the point P1 according to the adjusted control signal CODEP and the control signal CODEN, until the correction circuit 120 can adjust the voltage VNZQ at the point P1 according to the adjusted control signal CODEP and the control signal CODEN. The adjusted control signal CODEP and the control signal CODEN make the voltage value of voltage VNZQ substantially equal to (or approximately) the voltage value of voltage VZQ (that is, the resistance value of transistor M3 is adjusted to be substantially equal to (or approximately) equal to that of the transistor M3 up to the resistance value of M2).

In particular, when the voltage value of voltage VNZQ is stably close to the voltage value of voltage VZQ, the operation circuit 133 will fix the control signal CODEN in this state, and provide the corresponding control signal CODEN in this state to the correction The transistor M3 of the circuit 120 fixes the resistance value of the transistor M3, so that the resistance value of the transistor M2 is fixed by the external resistor RZQ.

In this regard, please refer to FIG. 1 and FIG. 2 at the same time. FIG. 2 is a timing diagram of the control signals CODEP and CODEN according to an embodiment of the present invention. In this embodiment, the impedance correction circuit 100 can generate the clock signal ZQCLK through an external clock generator (ClockGenerator) or oscillator (Oscillator) (not shown). Furthermore, the impedance correction circuit 100 can perform the ZQ correction operation according to the timing status of the clock signal ZQCLK.

Specifically, the impedance correction circuit 100 may start the ZQ correction operation after the memory device performs a set period to complete the ZQ correction operation. In the embodiments of FIG. 1 and FIG. 2 , since the first input terminal of the comparator 131 (that is, the non-inverting input terminal) and the second input terminal of the comparator 132 (that is, the inverting input terminal) are common Receive the voltage VZQ on the correction pad ZQPAD. Therefore, under some design requirements (in some embodiments), the comparator 131 and the comparator 132 can simultaneously generate the comparison results COMP1 and the comparison results COMP2, so that the operation circuit 133 can simultaneously rely on the voltage values of the comparison results COMP1 and COMP2 , to adjust multiple bits of the control signals CODEP and CODEN through binary search.

In this case, the impedance correction circuit 100 of this embodiment can perform correction operations on the transistor M1 of the correction circuit 110 and the transistors M2 and M3 of the correction circuit 120 at the same time, so that the resistance values of these transistors M1 to M3 can be adjusted according to the adjusted values. The control signals CODEN and CODEP are substantially equal (or approximately) to the resistance value of the external resistor RZQ, thereby effectively reducing the processing time of the impedance correction circuit 100 . At the same time, the impedance correction circuit 100 can provide the control signals CODEN and CODEP corresponding to the resistance value of the transistors M1 to M3 that are substantially equal (or approximately) to the resistance value of the external resistor RZQ to the output circuit of the memory device for optimization. The output impedance of the output circuit.

FIG. 3 is a timing diagram of control signals CODEP and CODEN according to another embodiment of the present invention. Please refer to FIG. 1 and FIG. 3 at the same time. In this embodiment, since the correction circuit 120 needs to adjust the voltage VNZQ to the voltage value of the voltage VZQ according to the adjusted control signal CODEN, so that the resistance value of the transistor M3 can be substantially the same. Due to the resistance value of transistor M2, therefore, when the voltage value of voltage VZQ is changed, the voltage value of voltage VNZQ is bound to be adjusted to a certain extent.

In this case, in the correction circuit 120, the voltage difference between the second terminal (that is, the drain terminal) and the first terminal (that is, the source terminal) of the transistor M3 may be affected by the voltage value of the voltage VNZQ. This affects the setting value of the voltage difference and causes the transistor M3 to be unable to operate in the linear region.

Therefore, under other design requirements (in other embodiments), the operation circuit 133 of this embodiment can generate the control signal CODEN by delaying (for example, waiting until the most significant bit and the 6th bit of the control signal CODEP are When outputting, the control signal CODEN is continuously generated (but the invention is not limited thereto), and the resistance value of the transistor M1 and M2 is corrected first, and then the resistance value of the transistor M3 is corrected to execute ZQ. Corrective operation.

Similarly, the impedance correction circuit 100 can also provide the control signals CODEN and CODEP corresponding to the resistance value of the transistors M1 to M3 that are substantially equal (or approximately) to the resistance value of the external resistor RZQ to the output circuit of the memory device, so as to optimize the output circuit of the memory device. Optimize the output impedance of the output circuit.

FIG. 4 is a partial circuit diagram illustrating the impedance correction circuit 100 shown in FIG. 1 according to another embodiment of the present invention. Please refer to FIG. 1 and FIG. 4 . The impedance correction circuit 100 shown in FIG. 1 may further include a signal format converter 440 . The signal format converter 440 in this embodiment may be a digital to analog converter (DAC).

In this embodiment, the signal format converter 440 can be coupled to the operation circuit 133 to receive the control signals CODEP and CODEN. What is different from the embodiment of FIG. 1 is that in this embodiment, after the operation circuit 133 completes the binary search, the signal format converter 440 can convert the control signal CODEP in the digital form into the control signal AP in the analog form, and The control signal AP is generated to the transistor M1 of the correction circuit 110 and the transistor M2 of the correction circuit 120 . In contrast, the signal format converter 440 may convert the control signal CODEN in a digital form into a control signal AN in an analog form, and generate the control signal AN to the transistor M3 of the correction circuit 120 .

Therefore, in this embodiment, the correction circuit 110 can adjust the voltage value of the voltage VZQ according to the control signal AP and the resistance value of the external resistor RZQ, and the correction circuit 120 can adjust the voltage value of the voltage VNZQ according to the control signals AP and AN.

Regarding the details of the operation of the operation circuit 133 to adjust the multiple bits of the control signals CODEP and CODEN through binary search, reference can be made to the relevant description of the embodiment in FIG. 1 and will not be described again.

In summary, the impedance correction circuit of the present invention can use the first correction circuit to correct the resistance value of the first transistor according to the first control signal, so that the resistance value of the first transistor is the same as the resistance value of the external resistor, and at the same time The second correction circuit is used to correct the resistance values of the second and third transistors according to the first and second control signals, so that the resistance values of the second and third transistors can also be the same as the resistance value of the external resistor. In this way, the impedance correction circuit can simultaneously provide the first and second control signals corresponding to the resistance values of the first to third transistors that are substantially the same as the resistance values of the external resistor to the output circuit of the memory device, so as to optimally This reduces the output impedance of the output circuit and effectively reduces the processing time of the impedance correction circuit.

Claims (10)

1. An impedance correction circuit, characterized by comprising: The first correction circuit is adapted to be coupled to the external resistor through the correction pad, and generate the first voltage according to the first control signal and the resistance value of the external resistor; A second correction circuit generates a second voltage based on the first control signal and the second control signal; and A control circuit used to compare the first voltage and the reference voltage to obtain a first comparison result, and to compare the first voltage and the second voltage to obtain a second comparison result, and to obtain a second comparison result based on the first comparison result. The first control signal is generated, and the second control signal is generated according to the second comparison result. 2. The impedance correction circuit according to claim 1, wherein the first correction circuit includes: A first transistor has a first terminal coupled to the operating voltage, a second terminal coupled to the correction pad, a control terminal receiving the first control signal, and adjusting the first transistor according to the first control signal. The resistance value of the first transistor. 3. The impedance correction circuit according to claim 2, wherein the second correction circuit includes: A second transistor has a first end coupled to the operating voltage, a control end of which receives the first control signal, and adjusts the resistance value of the second transistor according to the first control signal; and The third transistor has a first terminal coupled to the ground voltage, a second terminal coupled to the second terminal of the second transistor, a control terminal receiving the second control signal, and a control terminal according to the second control signal. to adjust the resistance value of the third transistor. 4. The impedance correction circuit according to claim 3, wherein the first transistor and the second transistor are P-type transistors, and the third transistor is an N-type transistor. 5. The impedance correction circuit according to claim 1, wherein the voltage value of the reference voltage is half of the voltage value of the operating voltage. 6. The impedance correction circuit according to claim 1, wherein the control circuit includes: A first comparator, a first input terminal of which receives the first voltage, and a second input terminal of which receives the reference voltage, so as to generate the first comparison result at the output terminal of the first comparator; a second comparator, the first input terminal of which receives the second voltage, and the second input terminal of which receives the first voltage, so as to generate the second comparison result at the output terminal of the second comparator; An operation circuit receives the first comparison result and the second comparison result, generates the first control signal according to the first comparison result, and generates the second control signal according to the second comparison result. Signal. 7. The impedance correction circuit according to claim 6, wherein the operation circuit is used to perform a binary search to generate the first control signal according to the first comparison result, and to generate the first control signal according to the second comparison result. The result is said second control signal. 8. The impedance correction circuit according to claim 7, wherein the operation circuit sequentially adjusts the plurality of bits of the first control signal bit by bit according to the voltage value of the first comparison result, and according to The voltage value of the second comparison result adjusts a plurality of bits of the second control signal bit by bit. 9. The impedance correction circuit according to claim 1, further comprising: A signal format converter is coupled to the control circuit and used to perform format conversion on the first control signal and the second control signal. 10. The impedance correction circuit according to claim 9, wherein the signal format converter is a digital-to-analog converter.