CN103853226B - Fixed current produces circuit and fixed current production method - Google Patents
Fixed current produces circuit and fixed current production method Download PDFInfo
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- CN103853226B CN103853226B CN201210508870.0A CN201210508870A CN103853226B CN 103853226 B CN103853226 B CN 103853226B CN 201210508870 A CN201210508870 A CN 201210508870A CN 103853226 B CN103853226 B CN 103853226B
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Abstract
The present invention discloses a kind of fixed current and produces circuit and relevant fixed current production method, it is applied in a chip, wherein this chip includes one first current generating circuit and one the 2nd current generating circuit, 2nd current generating circuit includes a transistor and an adjustable resistance, this fixed current production method includes: a non-essential resistance is connected to this first current generating circuit, so that this first current generating circuit uses this non-essential resistance to produce one first electric current; The 2nd current generating circuit is used to produce one the 2nd electric current; Adjust the resistance value of this adjustable resistance according to this first electric current and the 2nd electric current, so that the 2nd electric current substantially equals this first electric current, and the 2nd electric current is as the fixed current used in this chip.
Description
Technical field
The present invention has and produces circuit about a kind of fixed current, espespecially a kind of use chip internal to correct after resistance produce circuit and relevant fixed current production method to produce the fixed current of fixed current.
Background technology
An accurate current source generally all can be needed at chip internal, to provide a fixing electric current for element, but, because the resistance value of chip internal possibly cannot be accomplished very accurate, therefore the mode of the precisely realization of current source typically uses a band gap voltage (bandgapvoltage) and adds that a non-essential resistance produces. As mentioned above, it is necessary, owing to needing an extra non-essential resistance, therefore can cause and chip relevant design increases extra cost.
Summary of the invention
Therefore, an object of the present invention is to provide a kind of fixed current to produce circuit and relevant fixed current production method, it can use the resistance after chip internal correction to produce fixed current, and does not need extra correcting circuit, to solve the above problems.
According to one embodiment of the invention, a kind of fixed current being arranged in a chip produces circuit and includes one first current generating circuit, one the 2nd current generating circuit, an electric current mirror, a switch module and a correcting circuit, wherein this first current generating circuit includes a first crystal pipe, wherein this first crystal pipe is coupled to a contact of this chip, and when a chip testing phase, this contact is used for connecting a non-essential resistance and produces one first electric current for this first current generating circuit; 2nd current generating circuit includes a two-transistor and an adjustable resistance, and is used for producing one the 2nd electric current; This switch module is coupled between this first current generating circuit, the 2nd current generating circuit and this electric current mirror, and in order to optionally this first current generating circuit and the 2nd current generating circuit are connected to this electric current mirror, so that this electric current mirror copies this first electric current or the 2nd electric current; This correcting circuit is coupled to this electric current mirror, and in order to this first electric current of copying according to this electric current mirror and the 2nd electric current to adjust the resistance value of this adjustable resistance, so that the 2nd electric current substantially equals this first electric current, and the 2nd electric current is as the fixed current used in this chip.
According to another embodiment of the present invention, disclose a kind of fixed current production method being applied in a chip, wherein this chip includes one first current generating circuit and one the 2nd current generating circuit, 2nd current generating circuit includes a transistor and an adjustable resistance, this fixed current production method includes: a non-essential resistance is connected to this first current generating circuit, so that this first current generating circuit uses this non-essential resistance to produce one first electric current; The 2nd current generating circuit is used to produce one the 2nd electric current; Adjust the resistance value of this adjustable resistance according to this first electric current and the 2nd electric current, so that the 2nd electric current substantially equals this first electric current, and the 2nd electric current is as the fixed current used in this chip.
Accompanying drawing explanation
Fig. 1 is the schematic diagram producing circuit according to a fixed current of one embodiment of the invention.
Fig. 2 is that fixed current generation circuit produces the first electric current and the schematic diagram of the first corresponding numerical code when a chip testing phase.
Fig. 3 is that fixed current produces the schematic diagram that circuit produces the 2nd electric current and the 2nd corresponding numerical code when a chip testing phase.
Fig. 4 is the schema of the fixed current production method according to one embodiment of the invention.
Wherein, description of reference numerals is as follows:
100 fixed currents produce circuit
102 operational amplifiers
110 first current generating circuits
120 the 2nd current generating circuits
130 electric current mirrors
140 correcting circuits
142 transmission circuit
144 receiving circuits
146 digital signal processors
148 electrical fuses
M1, M2 transistor
Rext non-essential resistance
Rc adjustable resistance
SW1_1, SW1_2, SW2_1, SW2_2 switch
N1, N2 end points
400 ~ 406 steps
Embodiment
Some vocabulary is employed in the middle of right to censure specific element at specification sheets and follow-up applying for a patent. In art, technician should it will be appreciated that hardware manufacturer may call same element with different nouns. This specification sheets and follow-up apply for a patent right not in the way of the difference of title is used as distinguish one element from another, but the criterion distinguished it is used as with element difference functionally. " comprising " mentioned in the middle of specification sheets and follow-up claims in the whole text is an open term, therefore should be construed to " comprise but be not limited to ". In addition, " couple " word and comprise directly any and indirectly electrical connection at this, therefore, if literary composition describing one first device be coupled to a two devices, then represent this first device and can directly be electrically connected in this two devices, or be indirectly electrically connected to this two devices by other devices or connection means.
Please refer to Fig. 1, Fig. 1 is the schematic diagram producing circuit 100 according to a fixed current of one embodiment of the invention. as shown in Figure 1, fixed current produces circuit 100 and is used for producing a fixed current Ic, and include an operational amplifier 102, one first current generating circuit 110, one the 2nd current generating circuit 120, one electric current mirror 130, one switch module is (in the present embodiment, switch module contains switch S W1_1, SW1_2, SW1_3, and a correcting circuit 140 SW1_4), wherein the first current generating circuit 110 includes a transistor M1, 2nd current generating circuit 120 includes an a transistor M2 and adjustable resistance Rc, correcting circuit 140 includes a transmission circuit 142, one receiving circuit 144 and a digital signal processor 146, digital signal processor 146 wherein comprises multiple electrical fuse (Electricalfuse, Efuse) 148.
In the present embodiment, fixed current produces circuit 100 and is arranged in a chip, and the contact N1 shown in Fig. 1 is a contact of this chip, and when a chip testing phase, contact N1 is used for connecting a non-essential resistance Rext and produces one first electric current for the first current generating circuit 110; In addition, the contact N2 shown in Fig. 1 is a signal output contact of this chip, is used for being sent to outside this chip the signal that transmission circuit 142 exports via contact N2.
In one embodiment of the invention, this chip that fixed current generation circuit 100 is applied is a network chip, and sends circuit 142 and simulate front end (AnalogFrontEnd, AFE) circuit with receiving circuit 144 as the one of this chip. In addition, send circuit 142 itself and can use a digital analog converter (Digital-to-AnalogConverter, DAC) actual use is carried out, and be used for receiving from the network data of digital signal processor 146, and by a transmission line through being sent to outside this chip by contact N2 after received network data processing; In addition, receiving circuit 144 itself can use an analog(ue)digital transformer (Analog-to-DigitalConverter, ADC) actual use is carried out, and with from contact N2 receiving network data, and it is sent to digital signal processor 146 after received network data are made Analog-digital Converter and carries out subsequent disposal.
When a chip testing phase, please refer to Fig. 2, first, fixed current produces circuit 100 first can be connected to non-essential resistance Rext via contact N1, and switch S W1_1 and SW1_2 is via control signal VC1Control and conducting, switch S W2_1 and SW2_2 is then via control signal VC2Control and be in non-conducting state, wherein control signal VC1��VC2Can be produced by digital signal processor 146 or other sources. Now, owing to the positive pole of operational amplifier 102 is connected to band gap voltage (bandgapvoltage) Vbg, therefore, the first current generating circuit 110 can produce one first electric current I with current value (Vbg/Rext)1, and electric current mirror 130 copies the first electric current I1To produce a replica current IBX. Afterwards, send circuit 142 according to digital signal processor 146 to a reference data Di replica current IBX to be converted to one first magnitude of voltage Vox, wherein reference data Di be used to determine send circuit 142 in the ratio that replica current IBX is converted to the first magnitude of voltage Vox; Afterwards, the first magnitude of voltage Vox is then converted to one first numerical code Dox by receiving circuit 144 again, and the first numerical code Dox is then sent to digital signal processor 146, and is stored in wherein.
Then, after the first numerical code Dox is stored to digital signal processor 146, please refer to Fig. 3, switch S W1_1 and SW1_2 is via control signal VC1Control and be in non-conducting state, switch S W2_1 and SW2_2 is then via control signal VC2Control and conducting. Now, owing to the positive pole of operational amplifier 102 is connected to band gap voltage (bandgapvoltage) Vbg, therefore, the 2nd current generating circuit 120 can produce one the 2nd electric current I with current value (Vbg/Rc)2, and electric current mirror 130 copies the 2nd electric current I2To produce a replica current IBC. Afterwards, send circuit 142 according to digital signal processor 146 to reference data Di replica current IBC to be converted to one the 2nd magnitude of voltage Voc, 2nd magnitude of voltage Voc is then converted to one the 2nd numerical code Doc by receiving circuit 144 again, and the 2nd numerical code Doc is then sent to digital signal processor 146, and it is stored in wherein.
Then, it is used for respectively representing the first electric current I due to the first numerical code Dox stored in digital signal processor 146 and the 2nd numerical code Doc1With the 2nd electric current I2Size, therefore, digital signal processor 146 can according to the first numerical code Dox and the 2nd numerical code Doc to produce a correcting code Dcc to adjust the resistance value of adjustable resistance Rc so that the electric current that the electric current that the 2nd current generating circuit 120 produces can produce close to the first current generating circuit 110 as much as possible. For example, digital signal processor 146 according to the code value of the first numerical code Dox and the 2nd numerical code Doc or difference value, can correcting code Dcc to adjust the resistance value of adjustable resistance Rc to determine in comparison list; Or digital signal processor 146 can produce different correcting code Dcc to adjust the resistance value of adjustable resistance Rc lastingly, so that the electric current I that the 2nd current generating circuit 120 produces2The change continued with the 2nd corresponding numerical code Doc is until the 2nd numerical code Doc is very close to the first numerical code Dox.
Via above-mentioned adjustment, the resistance value of adjustable resistance Rc can very close to the resistance value of non-essential resistance Rext, therefore, the electric current I that the 2nd current generating circuit 120 produces2Also the electric current I that can produce close to the first current generating circuit 110 very much1Now, digital signal processor 146 can use electrical fuse 148 to record correcting code Dcc now, therefore, in the use that chip is follow-up, owing to correcting code Dcc is secured by electrical fuse 148, therefore the resistance value of adjustable resistance Rc also can be fixing, and chip just can utilize the 2nd current generating circuit 120 to produce a required fixed current Ic. Owing to no longer needing to use non-essential resistance in follow-up use, follow-up manufacturing cost therefore can be reduced.
In addition, the correcting circuit 140 produced in circuit 100 due to fixed current carrys out implementation with the transmission circuit 142 of chip itself with receiving circuit 144, does not therefore need to increase extra correcting circuit in the chips, it is possible to the cost on saving chip design and making.
However, it is to be noted that, although in the embodiment shown in Fig. 2, correcting circuit 140 carrys out implementation with the transmission circuit 142 of chip itself, receiving circuit 144, but the present invention is not as limit. In other embodiments of the present invention, but correcting circuit 140 can also be correcting circuit independent in chip, and can have the design of other patterns, and and the transmission circuit 142 of non-usage chip itself and receiving circuit 144, the change in these designs all should be under the jurisdiction of the category of the present invention.
Please refer to Fig. 4, Fig. 4 is the schema of fixed current production method according to one embodiment of the invention, and with reference to figure 1��4 and there is the disclosure about Fig. 1��3 above, flow process is described below:
Step 400: provide a chip, wherein this chip includes one first current generating circuit and one the 2nd
Current generating circuit, the 2nd current generating circuit includes a transistor and an adjustable resistance;
Step 402 a: non-essential resistance is connected to this first current generating circuit, so that this first current generating circuit uses this non-essential resistance to produce one first electric current;
Step 404: use the 2nd current generating circuit to produce one the 2nd electric current;
Step 406: the resistance value adjusting this adjustable resistance according to this first electric current and the 2nd electric current, so that the 2nd electric current substantially equals this first electric current, and the 2nd electric current is as the fixed current used in this chip.
Briefly conclude the present invention, fixed current in the present invention produces circuit to relevant fixed current production method, the resistance value of one adjustable resistance of chip internal is corrected to the resistance value close to a non-essential resistance, so that chip can use the resistance after internal calibrations to produce a reliable fixed current, owing to not needing non-essential resistance, therefore can really reduce follow-up manufacturing cost. In addition, the correcting circuit that the fixed current of the present invention produces in circuit can use the transmission circuit of chip itself and receiving circuit to carry out implementation, does not therefore need to design extra correcting circuit, with the cost saved further in chip design and manufacturing.
The foregoing is only the better embodiment of the present invention, all impartial changes done according to the present patent application Patent right requirement scope, with modifying, all should belong to the covering scope of the present invention.
Claims (11)
1. fixed current produces a circuit, is arranged in a chip, includes:
One first current generating circuit, include a first crystal pipe, wherein this first crystal pipe is coupled to a contact of this chip, and when a chip testing phase, this contact is used to connect a non-essential resistance and produces one first electric current for this first current generating circuit;
One the 2nd current generating circuit, includes a two-transistor and an adjustable resistance, is used for producing one the 2nd electric current;
One electric current mirror;
One switch module, it is coupled between this first current generating circuit, the 2nd current generating circuit and this electric current mirror, in order to optionally this first current generating circuit and the 2nd current generating circuit are connected to this electric current mirror, so that this electric current mirror copies this first electric current or the 2nd electric current; And
One correcting circuit, it is coupled to this electric current mirror, in order to this first electric current of copying according to this electric current mirror and the 2nd electric current to adjust the resistance value of this adjustable resistance, so that the 2nd electric current is as much as possible close to this first electric current, and the 2nd electric current is as the fixed current used in this chip;
Wherein, this correcting circuit includes:
One transmission circuit, is used for receiving this first electric current that this electric current mirror copies to produce one first magnitude of voltage, and receives the 2nd electric current that this electric current mirror copies to produce one the 2nd magnitude of voltage;
One receiving circuit, is coupled to this transmission circuit, in order to receive this first magnitude of voltage to produce one first numerical code, and receives the 2nd magnitude of voltage to produce one the 2nd numerical code; And
One digital signal processor, it is coupled to this receiving circuit, include multiple electrical fuse, and this digital signal processor according to this first numerical code and the 2nd numerical code, to control, the plurality of electrical fuse produces a correcting code, and this correcting code is used for adjusting the resistance value of this adjustable resistance.
2. fixed current as claimed in claim 1 produces circuit, and wherein this correcting circuit comprises an analog front circuit of this chip.
3. fixed current as claimed in claim 1 produces circuit, wherein when this chip testing phase, this first current generating circuit is connected to this electric current mirror by this switch module, and make the 2nd current generating circuit be not attached to this electric current mirror, and this correcting circuit receives this first electric current that this electric current mirror copies; And the 2nd current generating circuit is separately connected to this electric current mirror by this switch module, and this first current generating circuit is made to be not attached to this electric current mirror, and this correcting circuit receives the 2nd electric current that this electric current mirror copies; And this first electric current of copying according to this electric current mirror of this correcting circuit and the 2nd electric current are to adjust the resistance value of this adjustable resistance, so that the 2nd electric current is as much as possible close to this first electric current.
4. fixed current as claimed in claim 1 produces circuit, and wherein this chip is a network chip, and this transmission circuit is respectively in this network chip with this receiving circuit to be used for sending and the circuit of reception network coherent signal.
5. fixed current as claimed in claim 1 produces circuit, and this digital signal processor, according to the difference value of this first numerical code and the 2nd numerical code, determines a correcting code, to adjust the resistance value of this adjustable resistance in comparison list.
6. fixed current as claimed in claim 4 produces circuit, and wherein this transmission circuit is a digital analog converter, is used for receiving the network data from this digital signal processor.
7. fixed current as claimed in claim 1 produces circuit, also comprise operational amplifier, the positive pole of this operational amplifier is connected to a band gap voltage, and the negative pole of this operational amplifier is coupled to this first current generating circuit, the 2nd current generating circuit by this switch module.
8. fixed current as claimed in claim 7 produces circuit, and this switch module comprises:
First switch, is coupled between this first current generating circuit and this electric current mirror;
2nd switch, be coupled to the 2nd current generating circuit and and this electric current mirror between;
3rd switch, is coupled between the negative pole of this operational amplifier and the first current generating circuit;
4th switch, is coupled between the negative pole of this operational amplifier and the 2nd current generating circuit.
9. a fixed current production method, it is applied in a chip, wherein this chip includes one first current generating circuit and one the 2nd current generating circuit, and the 2nd current generating circuit includes a transistor and an adjustable resistance, and this fixed current production method includes:
One non-essential resistance is connected to this first current generating circuit, so that this first current generating circuit uses this non-essential resistance to produce one first electric current;
The 2nd current generating circuit is used to produce one the 2nd electric current;
Adjust the resistance value of this adjustable resistance according to this first electric current and the 2nd electric current, so that the 2nd electric current is as much as possible close to this first electric current, and the 2nd electric current is as the fixed current used in this chip;
Wherein, adjust the resistance value of this adjustable resistance according to this first electric current and the 2nd electric current, so that the 2nd electric current includes close to the step of this first electric current as much as possible:
Receive this first electric current to produce one first magnitude of voltage;
Receive this first magnitude of voltage to produce one first numerical code;
Receive the 2nd electric current to produce one the 2nd magnitude of voltage;
Receive the 2nd magnitude of voltage to produce one the 2nd numerical code; And
According to this first numerical code and the 2nd numerical code to adjust the resistance value of this adjustable resistance, include: produce a correcting code according to this first numerical code and the 2nd numerical code with the multiple electrical fuses controlling in this chip, and this correcting code is used for adjusting the resistance value of this adjustable resistance.
10. fixed current production method as claimed in claim 9, the step wherein producing this first magnitude of voltage, this first numerical code, the 2nd magnitude of voltage and the 2nd numerical code includes:
Use an analog front circuit of this chip to produce this first magnitude of voltage, this first numerical code, the 2nd magnitude of voltage and the 2nd numerical code.
11. fixed current production methods as claimed in claim 10, the step wherein producing this first magnitude of voltage, this first numerical code, the 2nd magnitude of voltage and the 2nd numerical code includes:
Use a transmission circuit of this chip to receive this first electric current to produce this first magnitude of voltage, and receive the 2nd electric current to produce the 2nd magnitude of voltage;
Use a receiving circuit of this chip to receive this first magnitude of voltage to produce this first numerical code, and receive the 2nd magnitude of voltage to produce the 2nd numerical code;
Wherein this chip is a network chip, and this transmission circuit and this receiving circuit are respectively in this network chip to be used for the circuit sending with receiving network coherent signal.
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| CN104181473A (en) * | 2014-08-25 | 2014-12-03 | 长沙瑞达星微电子有限公司 | Current source calibrating circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6747508B2 (en) * | 2002-01-25 | 2004-06-08 | Richtek Technology Corp. | Resistance mirror circuit |
| CN1900923A (en) * | 2005-08-19 | 2007-01-24 | 威盛电子股份有限公司 | Adjustable termination resistor for integrated circuit chip |
| US7345503B2 (en) * | 2006-06-30 | 2008-03-18 | International Business Machines Corporation | Method and apparatus for impedance matching in transmission circuits using tantalum nitride resistor devices |
| CN101630170A (en) * | 2009-08-18 | 2010-01-20 | 上海艾为电子技术有限公司 | Adaptive control device internally and externally set with constant current and method thereof |
| CN102183989A (en) * | 2011-04-14 | 2011-09-14 | 上海艾为电子技术有限公司 | Self-adaptive current control device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6373266B1 (en) * | 2000-03-31 | 2002-04-16 | Agere Systems Guardian Corp. | Apparatus and method for determining process width variations in integrated circuits |
| US6590441B2 (en) * | 2001-06-01 | 2003-07-08 | Qualcomm Incorporated | System and method for tuning a VLSI circuit |
| TW538602B (en) * | 2001-10-24 | 2003-06-21 | Realtek Semi Conductor Co Ltd | Circuit and method for automatically changing matching resistance |
| US6862714B2 (en) * | 2002-04-19 | 2005-03-01 | Intel Corporation | Accurately tuning resistors |
| US6836170B2 (en) * | 2003-04-17 | 2004-12-28 | Kabushiki Kaisha Toshiba | Impedance trimming circuit |
| KR100545711B1 (en) * | 2003-07-29 | 2006-01-24 | 주식회사 하이닉스반도체 | Reference voltage generator that can output various levels of reference voltage using fuse trimming |
| JP4095987B2 (en) * | 2004-12-16 | 2008-06-04 | 富士通株式会社 | Clock generating circuit, signal multiplexing circuit, optical transmitter, and clock generating method |
| US7514954B2 (en) * | 2006-05-10 | 2009-04-07 | Micron Technology, Inc. | Method and apparatus for output driver calibration |
| US20080246537A1 (en) * | 2007-04-03 | 2008-10-09 | Broadcom Corporation | Programmable discontinuity resistors for reference ladders |
| TWI469512B (en) * | 2010-12-20 | 2015-01-11 | Ic Plus Corp | Impendence tuning apparatus |
-
2012
- 2012-11-30 CN CN201210508870.0A patent/CN103853226B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6747508B2 (en) * | 2002-01-25 | 2004-06-08 | Richtek Technology Corp. | Resistance mirror circuit |
| CN1900923A (en) * | 2005-08-19 | 2007-01-24 | 威盛电子股份有限公司 | Adjustable termination resistor for integrated circuit chip |
| US7345503B2 (en) * | 2006-06-30 | 2008-03-18 | International Business Machines Corporation | Method and apparatus for impedance matching in transmission circuits using tantalum nitride resistor devices |
| CN101630170A (en) * | 2009-08-18 | 2010-01-20 | 上海艾为电子技术有限公司 | Adaptive control device internally and externally set with constant current and method thereof |
| CN102183989A (en) * | 2011-04-14 | 2011-09-14 | 上海艾为电子技术有限公司 | Self-adaptive current control device |
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