CN113765507A - Radio frequency switch circuit - Google Patents
Radio frequency switch circuit Download PDFInfo
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- CN113765507A CN113765507A CN202111038540.5A CN202111038540A CN113765507A CN 113765507 A CN113765507 A CN 113765507A CN 202111038540 A CN202111038540 A CN 202111038540A CN 113765507 A CN113765507 A CN 113765507A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/44—Transmit/receive switching
Abstract
The invention provides a radio frequency switch circuit, which comprises a transmitting loop, a receiving loop, an antenna loop, a first grounding loop, a second grounding loop and a grid voltage bias circuit, wherein the transmitting loop, the receiving loop and the antenna loop are all connected in a converging way at a general node; the other end of the transmitting loop is connected with the input node and is provided with a first series switch; the other end of the receiving loop is connected with the output node and is provided with a second series switch; the other end of the antenna loop is connected with an antenna node; one end of the first grounding loop is connected to the transmitting loop, the other end of the first grounding loop is grounded, and a first parallel switch is arranged; one end of the second grounding loop is connected to the receiving loop, the other end of the second grounding loop is grounded, and a second parallel switch is arranged; the transmitting loop and the receiving loop are connected with the antenna loop by controlling the conduction and the closing of the first series switch, the second series switch, the first parallel switch and the second parallel switch through the grid voltage bias circuit. The radio frequency switch circuit shortens the switching time and reduces the loss.
Description
Technical Field
The invention belongs to the field of radio frequency switches, and particularly relates to a radio frequency switch circuit.
Background
In the rf front-end circuit, an rf switch is an indispensable part. The radio frequency switch can be selectively connected with the antenna end and the input end or connected with the antenna end and the output end, so that two modes of signal transmitting and receiving are realized, and the radio frequency switch is widely applied to mobile phones. Usually, a plurality of transistors are stacked to improve the power handling capability of the rf switch. However, in the rf switch, the larger the number of stacked transistors, the larger the impedance in the on state of the switch, and the larger the loss of the signal flowing through the switch. The switching time between the transmitting and receiving states of the rf switch is also important for the rf front-end of the handset.
Disclosure of Invention
In view of the above, the present invention is directed to a radio frequency switch circuit, so as to solve the problem of increased loss caused by the number of stacked transistors, reduce the waste of switching time of the radio frequency switch, and improve the switching efficiency of the transmitting and receiving states.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a radio frequency switch circuit comprises a transmitting loop, a receiving loop, an antenna loop, a first grounding loop, a second grounding loop and a grid voltage bias circuit, wherein the transmitting loop, the receiving loop and the antenna loop are all connected in a converging way at a general node;
the other end of the transmitting loop is connected with the input node, and a first series switch is arranged on the transmitting loop;
the other end of the receiving loop is connected with the output node, and a second series switch is arranged on the receiving loop;
the other end of the antenna loop is connected with an antenna node;
one end of the first grounding loop is connected to one end, close to the input node, of the first series switch of the transmitting loop, the other end of the first grounding loop is grounded, and a first parallel switch is arranged on the first grounding loop;
one end of the second grounding loop is connected to one end, close to the output node, of the second series switch of the receiving loop, and the other end of the second grounding loop is grounded;
the transmitting loop and the receiving loop are connected with the antenna loop by controlling the conduction and the closing of the first series switch, the second series switch, the first parallel switch and the second parallel switch through a grid voltage bias circuit.
The first series switch and the second parallel switch are both conducted, the second series switch and the first parallel switch are both closed, the transmitting loop is conducted with the antenna loop, and a signal transmitting task is executed; the second series switch and the first parallel switch are both conducted, the first series switch and the second parallel switch are both closed, the receiving and transmitting loop is conducted with the antenna loop, and a signal receiving task is executed.
Further, the first series switch comprises N1 transistors, the N1 transistors are sequentially connected in series, the N1 transistors which are sequentially connected in series are respectively connected with a capacitor in series at the front end of the first transistor and the rear end of the last transistor, and N1 is larger than or equal to 1;
the second series switch comprises N2 transistors, N2 transistors are sequentially connected in series, N2 transistors which are sequentially connected in series are respectively connected with a capacitor in series at the front end of the first transistor and the rear end of the last transistor, and N2 is more than or equal to 1;
the first parallel switch comprises N3 transistors, N3 transistors are sequentially connected in series, N3 transistors which are sequentially connected in series are respectively connected with a capacitor in series at the front end of the first transistor and the rear end of the last transistor, and N3 is more than or equal to 1;
the second parallel switch comprises N4 transistors, N4 transistors are sequentially connected in series, N4 transistors which are sequentially connected in series are also respectively connected with a capacitor in series at the front end of the first transistor and the rear end of the last transistor, and N4 is more than or equal to 1;
two transistors connected in series are connected through a source electrode and a drain electrode, and two capacitors are respectively connected in series.
Furthermore, the body end of the transistor is connected with a resistor, the other end of the resistor is connected with the ground end, and the resistance value of the resistor is 30K ohms.
Furthermore, the gate voltage bias circuit is a level shift circuit and comprises a control signal end, a VTR control voltage end and a VTR-control voltage end, wherein the control signal end is used for receiving signals of the switch state information, and the VTR control voltage end and the VTR-control voltage end are matched to output control voltages of '0 and 1' or '1 and 0' opposite directions;
the grid voltage bias circuit controls the VTR control voltage end and the VTR-control voltage end to be matched and switched to obtain opposite control voltage.
Furthermore, the first series switch also comprises a first resistor, a second resistor and a third resistor, the grid electrodes of the transistors in the first series switch are connected to the VTR control voltage end after being connected with the first resistor, the source electrodes of the transistors in the first series switch are connected to the VTR-control voltage end after being connected with the second resistor, and the drain electrodes connected with the capacitor in the first series switch are connected to the VTR-control voltage end after being connected with the third resistor;
the second series switch also comprises a resistor IV, a resistor V and a resistor VI, the grid electrodes of the transistors in the second series switch are connected with the VTR-control voltage end after being connected with the resistor IV, the source electrodes of the transistors in the second series switch are connected with the VTR-control voltage end after being connected with the resistor V, and the drain electrodes connected with the capacitor in the second series switch are connected with the VTR-control voltage end after being connected with the resistor VI;
the first parallel switch further comprises a resistor seventh, a resistor eighth and a resistor ninth, the grid electrodes of the transistors in the first parallel switch are connected with the VTR-control voltage end after being connected with the resistor seventh, the source electrodes of the transistors in the first parallel switch are connected with the VTR-control voltage end after being connected with the resistor eighth, and the drain electrodes connected with the capacitor in the first parallel switch are connected with the VTR-control voltage end after being connected with the resistor ninth;
the second parallel switch further comprises a resistor ten, a resistor eleven and a resistor twelve, the grid electrodes of the transistors in the second parallel switch are connected to the VTR control voltage end after being connected with the resistor ten, the source electrodes of the transistors in the second parallel switch are connected to the VTR-control voltage end after being connected with the resistor eleven, and the drain electrodes connected with the capacitor in the second parallel switch are connected to the VTR-control voltage end after being connected with the resistor twelve.
Further, the first resistor, the second resistor, the fourth resistor, the fifth resistor, the seventh resistor, the eighth resistor, the tenth resistor and the eleventh resistor are all greater than 20K ohms, and the third resistor, the sixth resistor, the ninth resistor and the twelfth resistor are all less than 10K ohms.
Further, the transistors are all silicon-on-insulator type MOS transistors.
Furthermore, a first capacitance resonance element is arranged between the antenna node and the general node of the antenna loop, and a second capacitance resonance element is arranged between the intersection point of the second grounding loop and the receiving node of the receiving loop; and a third capacitive resonant element is arranged in the transmitting loop between the intersection point of the first grounding loop and the transmitting node.
Further, the first capacitive resonance element, the second capacitive resonance element and the third capacitive resonance element are inductors or bonding wires.
Compared with the prior art, the radio frequency switch circuit has the following beneficial effects:
(1) the gate voltage bias circuit relieves the compromise relation between insertion loss and switching time, so that the radio frequency switch can complete the switching of the transmitting mode and the receiving mode in a short time while achieving lower insertion loss, and time and efficiency are saved.
(2) The grid voltage bias circuit can enable the transistor to work in a state of relative negative voltage, so that a common negative voltage generating device of a radio frequency switch is omitted, and the power loss of the part is omitted. Meanwhile, the relative negative pressure state of the source and the drain of the transistor also improves the performance of the radio frequency switch to a certain extent. The relative positive pressure/negative pressure is formed between the grid electrode and the source drain electrode of the transistor, so that the on-off state of the transistor is more thorough.
(3) The inductors connected with the antenna node, the input node and the output node can be replaced by the bonding wire, the length of the bonding wire is adjusted, and the insertion loss of the radio frequency switch is optimized.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a circuit diagram of an rf switch according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a gate voltage bias circuit according to an embodiment of the present invention;
FIG. 3 is a diagram of a level shift circuit according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a transistor according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a first series switch circuit according to an embodiment of the present invention.
Description of reference numerals:
100-a radio frequency switch; 101-antenna node; 102-an input node; 103-output node; 104-a first series switch; 105-a second series switch; 106-a first parallel switch; 107-a second parallel switch; 108-a master node; 109-inductance one; 120-inductance two; 121-inductance three; 201-gate voltage bias circuit; 202-first large resistance; 203-second excess resistance; 204-third excess resistance; 205-fourth excess resistance; 206-fifth excess resistance; 207-sixth excess resistance; 301-transistor one; 302-eleventh resistance; 303-twelfth resistance; 304-a thirteenth resistance; 305-a fourteenth resistance; 401-a first transistor; 402-a second transistor; 403-nth transistor; 404-a first resistance; 405-a second resistance; 407-a third resistance; 408-a fourth resistance; 410-a fifth resistance; 411 — sixth resistance; 412-a seventh resistance; 413-an eighth resistance; 414-ninth resistance; 415-tenth resistance; 416-capacitance one; 417-capacitance two.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
As shown in fig. 1, the rf switch 100 includes an antenna node 101, an input node 102, an output node 103, a first series switch 104, a second series switch 105, a first parallel switch 106, a second parallel switch 107, and a gate bias circuit. The first series switch 104 and the second series switch 105 intersect at a common node 108. An inductor one 109 is arranged between the antenna node 101 and the total node 108, an inductor two 120 is arranged between the input node 102 and the first series switch 104, and an inductor three 121 is arranged between the output node 103 and the second series switch 105. The gate voltage bias circuit supplies a gate control voltage to the first series circuit 104, the second series circuit 105, the first parallel circuit 106, and the second parallel circuit 107.
When the control voltage VTR provided by the bias circuit is a positive voltage, VTR is a zero voltage opposite to the positive voltage, and then 104 and 107 are in an on state and 105 and 106 are in an off state, the rf switch 100 turns on a path between the antenna node and the input node and turns off a path between the antenna node and the output node, the rf signal is transmitted from the input node to the antenna node, and the rf switch operates in a transmitting mode.
When the control voltage VTR provided by the bias circuit is zero voltage, VTR is a positive voltage opposite to VTR, and at this time 105 and 106 are in on state, 104 and 107 are in off state, the rf switch 100 turns on the path between the antenna node and the output node, turns off the path between the antenna node and the input node, the rf signal is transmitted from the antenna node to the output node, and the rf switch operates in a receiving mode.
As shown in fig. 2 and fig. 3, a control signal of zero voltage or positive voltage is input to the gate bias circuit 201, the gate bias circuit 201 has two control voltage output terminals, and can output two opposite control voltages VTR and VTR-, which are respectively positive voltage or zero voltage, and the output of the two voltages of positive voltage or zero voltage is realized by a level shifter circuit.
VTR and VTR-are applied to the gate or source and drain of the transistor through a first large resistor 202, a second excessive resistor 203, a third excessive resistor 204, a fourth excessive resistor 205, a fifth excessive resistor 206, and a sixth excessive resistor 207. The control voltage applied to the source and the drain is the same, and the control voltage applied to the gate and the source and the drain is opposite. By adopting the mode, relative positive pressure/negative pressure can be formed between the grid electrode and the source drain electrode of the transistor, and the on and off of the transistor are controlled.
The special bias mode does not need to generate negative voltage, and simultaneously, the transistor can work in a state of relative negative voltage, thereby omitting a common negative voltage generating device of a radio frequency switch and saving the power loss of the part. Meanwhile, the relative negative pressure state of the source and the drain of the transistor also improves the performance of the radio frequency switch to a certain extent.
As shown in fig. 4, a circuit connection diagram of a transistor is shown, an eleventh resistor 302, a twelfth resistor 303, a thirteenth resistor 304 and a fourteenth resistor 305 are all connected to a first transistor 301, a body of the first transistor 301 is grounded through the eleventh resistor 302, a gate of the first transistor 301 is connected to one control voltage output terminal of the gate control circuit through the thirteenth resistor 304, a source of the first transistor 301 is connected to the twelfth resistor 303, and a drain of the first transistor 301 is connected to the fourteenth resistor 305 and then connected to the other control voltage output terminal of the gate control circuit.
When the first transistor 301 is in the conducting state, VTR is a positive voltage, VTR-is a zero voltage, and the gate-source voltage of the first transistor 301 becomes a relative positive voltage. When the eleventh resistor 302 is in the off state, VTR is a zero voltage, VTR-is a positive voltage, and the gate-source voltage of the eleventh resistor 302 is a relatively negative voltage. The resistance values of the eleventh resistor 302 and the thirteenth resistor 304 may be relatively large, so as to reduce leakage of the rf signal to the body and the gate of the first transistor 301, thereby reducing insertion loss when the rf switch is in an on state.
As shown in fig. 5, the first series switch is formed by stacking N1 transistors in series, N1 is an integer greater than or equal to one, the body terminal of the first transistor 401 is connected to the eighth resistor 413, the body terminal of the second transistor 402 is connected to the ninth resistor 414, the body terminal of the nth transistor 403 is connected to the tenth resistor 415, and then grounded, the gate of the first transistor 401 is connected to the second resistor 405, the gate of the second transistor 402 is connected to the fourth resistor 408, the gate of the third transistor 403 is connected to the sixth resistor 411, and then both connected to the VTR terminal of the gate control circuit,
the source of the first transistor 401 is connected to the first resistor 404, the source of the second transistor 402 is connected to the third resistor 407, the source of the nth transistor 403 is connected to the fifth resistor 410, and the drain of the nth transistor 403 is connected to the seventh resistor 412.
The source of the first transistor is connected to the first capacitor 416, and the drain of the nth transistor is connected to the second capacitor 417.
The first transistor 401, the second transistor 402 and the nth transistor 403 are connected in series in sequence, that is, the drain of the first transistor 401 is connected to the source of the second transistor 402, the drain of the second transistor 402 is connected to the source of the next transistor, and the drain of the (N-1) th transistor is connected to the source of the nth transistor 403.
The first capacitor 416 and the second capacitor 417 are essential to isolate the dc voltages, so that the dc voltages do not affect each other. When the gate bias circuit applies a voltage to the source and drain of the transistor, for the second capacitor 417, the control voltage charges the second capacitor 417 through the seventh resistor 412, so that the resistance of the seventh resistor 412 determines the charging time of the second capacitor 417, and the charging time of the second capacitor 417 also determines the charging time between different operation modes of the rf switch. Reducing the resistance of the seventh resistor 412 can reduce the switching time of the rf switch to some extent, without causing an excessive influence on the insertion loss of the rf switch.
Meanwhile, in fig. 1, the first inductor 109, the second inductor 120, and the third inductor 121 may be replaced by bonding wires, and the lengths of the bonding wires are adjusted to generate resonance with the capacitors in the series switches/parallel switches, so that the rf switches resonate at a target frequency, thereby further reducing the insertion loss in the on mode.
When the first capacitance resonant element, the second capacitance resonant element and the third capacitance resonant element are bonding wires,
resonance of the bonding wire and the capacitor:
the bond wire can be regarded as an inductor with a certain inductance value, and assuming that the inductance value of the bond wire is L, when the bond wire and the capacitor C resonate at the center frequency f of the target frequency range, the following relationship is given:
at this time, the process of the present invention,
when the series inductor and the capacitor generate resonance, the impedance is as follows:
the impedance R can be found to be zero in connection with equation (2).
Therefore, when the bonding wire and the capacitor are in series resonance, the impedance is minimum, the loss of the radio frequency signal is minimum, and the conduction loss of the switch is also minimum.
The inductance of the bonding wire can be changed by changing the length of the bonding wire, so that the bonding wire and the capacitor can resonate at a specific central frequency by controlling the length of the bonding wire, and the effect of minimizing the insertion loss of the switch is achieved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (9)
1. A radio frequency switch circuit, characterized by: the circuit comprises a transmitting loop, a receiving loop, an antenna loop, a first grounding loop, a second grounding loop and a grid voltage bias circuit, wherein the transmitting loop, the receiving loop and the antenna loop are all connected in a converging manner at a general node;
the other end of the transmitting loop is connected with the input node, and a first series switch is arranged on the transmitting loop;
the other end of the receiving loop is connected with the output node, and a second series switch is arranged on the receiving loop;
the other end of the antenna loop is connected with an antenna node;
one end of the first grounding loop is connected to one end, close to the input node, of the first series switch of the transmitting loop, the other end of the first grounding loop is grounded, and a first parallel switch is arranged on the first grounding loop;
one end of the second grounding loop is connected to one end, close to the output node, of the second series switch of the receiving loop, and the other end of the second grounding loop is grounded;
the transmitting loop and the receiving loop are connected with the antenna loop by controlling the conduction and the closing of the first series switch, the second series switch, the first parallel switch and the second parallel switch through a grid voltage bias circuit.
2. A radio frequency switch circuit according to claim 1, wherein: the first series switch comprises N1 transistors, N1 transistors are sequentially connected in series, N1 transistors which are sequentially connected in series are respectively connected with a capacitor in series at the front end of the first transistor and the rear end of the last transistor, and N1 is more than or equal to 1;
the second series switch comprises N2 transistors, N2 transistors are sequentially connected in series, N2 transistors which are sequentially connected in series are respectively connected with a capacitor in series at the front end of the first transistor and the rear end of the last transistor, and N2 is more than or equal to 1;
the first parallel switch comprises N3 transistors, N3 transistors are sequentially connected in series, N3 transistors which are sequentially connected in series are respectively connected with a capacitor in series at the front end of the first transistor and the rear end of the last transistor, and N3 is more than or equal to 1;
the second parallel switch comprises N4 transistors, N4 transistors are sequentially connected in series, N4 transistors which are sequentially connected in series are also respectively connected with a capacitor in series at the front end of the first transistor and the rear end of the last transistor, and N4 is more than or equal to 1;
two transistors connected in series are connected through a source electrode and a drain electrode, and two capacitors are respectively connected in series.
3. A radio frequency switch circuit according to claim 2, wherein: the body end of the transistor is connected with a resistor thirteen, the other end of the resistor thirteen is connected with the ground end, and the resistance value of the resistor thirteen is larger than 20K ohms.
4. A radio frequency switch circuit according to claim 2, wherein: the gate voltage bias circuit is a level switching circuit and comprises a control signal end, a VTR control voltage end and a VTR-control voltage end, wherein the gate voltage bias circuit receives a signal of switching state information through the control signal end, and the VTR control voltage end and the VTR-control voltage end are matched to output control voltages of '0 and 1' or '1 and 0' opposite directions;
the grid voltage bias circuit controls the VTR control voltage end and the VTR-control voltage end to be matched and switched to obtain opposite control voltage.
5. The radio frequency switch circuit according to claim 4, wherein: the first series switch also comprises a first resistor, a second resistor and a third resistor, wherein the grid electrodes of transistors in the first series switch are connected with the VTR control voltage end after being connected with the first resistor, the source electrodes of the transistors in the first series switch are connected with the VTR-control voltage end after being connected with the second resistor, and the drain electrodes connected with the capacitor in the first series switch are connected with the VTR-control voltage end after being connected with the third resistor;
the second series switch also comprises a resistor IV, a resistor V and a resistor VI, the grid electrodes of the transistors in the second series switch are connected with the VTR-control voltage end after being connected with the resistor IV, the source electrodes of the transistors in the second series switch are connected with the VTR-control voltage end after being connected with the resistor V, and the drain electrodes connected with the capacitor in the second series switch are connected with the VTR-control voltage end after being connected with the resistor VI;
the first parallel switch further comprises a resistor seventh, a resistor eighth and a resistor ninth, the grid electrodes of the transistors in the first parallel switch are connected with the VTR-control voltage end after being connected with the resistor seventh, the source electrodes of the transistors in the first parallel switch are connected with the VTR-control voltage end after being connected with the resistor eighth, and the drain electrodes connected with the capacitor in the first parallel switch are connected with the VTR-control voltage end after being connected with the resistor ninth;
the second parallel switch further comprises a resistor ten, a resistor eleven and a resistor twelve, the grid electrodes of the transistors in the second parallel switch are connected to the VTR control voltage end after being connected with the resistor ten, the source electrodes of the transistors in the second parallel switch are connected to the VTR-control voltage end after being connected with the resistor eleven, and the drain electrodes connected with the capacitor in the second parallel switch are connected to the VTR-control voltage end after being connected with the resistor twelve.
6. The radio frequency switch circuit according to claim 5, wherein: the first resistor, the second resistor, the fourth resistor, the fifth resistor, the seventh resistor, the eighth resistor, the tenth resistor and the eleventh resistor are all larger than 20K ohms, and the third resistor, the sixth resistor, the ninth resistor and the twelfth resistor are all smaller than 10K ohms.
7. The radio frequency switch circuit according to claim 5, wherein: the transistors are all silicon-on-insulator type MOS transistors.
8. A radio frequency switch circuit according to claim 1, wherein: the antenna loop is provided with a first capacitive resonance element between an antenna node and a main node, and the receiving loop is provided with a second capacitive resonance element between a second grounding loop and a receiving loop intersection point and a receiving node; and a third capacitive resonant element is arranged in the transmitting loop between the intersection point of the first grounding loop and the transmitting node.
9. A radio frequency switch circuit according to claim 8, wherein: the first capacitance resonance element, the second capacitance resonance element and the third capacitance resonance element are inductors or bonding wires.
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| CN202111038540.5A CN113765507A (en) | 2021-09-06 | 2021-09-06 | Radio frequency switch circuit |
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| CN202111038540.5A CN113765507A (en) | 2021-09-06 | 2021-09-06 | Radio frequency switch circuit |
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