CN113765065A - Backflow prevention switch circuit and chip - Google Patents
Backflow prevention switch circuit and chip Download PDFInfo
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- CN113765065A CN113765065A CN202111019368.9A CN202111019368A CN113765065A CN 113765065 A CN113765065 A CN 113765065A CN 202111019368 A CN202111019368 A CN 202111019368A CN 113765065 A CN113765065 A CN 113765065A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
- H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
- H02H7/1213—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for DC-DC converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/3353—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having at least two simultaneously operating switches on the input side, e.g. "double forward" or "double (switched) flyback" converter
Abstract
The application relates to a prevent flowing backward switch circuit and chip, should prevent flowing backward switch circuit includes: the controllable switch unit comprises a first switch subunit and a second switch subunit which are connected in parallel, wherein the first end of the first switch subunit and the first end of the second switch subunit are electrically connected and are used as first signal ends; the control signal processing unit is electrically connected with the control end of the first switch subunit and the first boosting unit respectively, and is used for outputting a first voltage control signal to the control end of the first switch subunit according to an input external control signal and outputting a first voltage signal and a second voltage control signal to the first boosting unit respectively; the first voltage boosting unit is electrically connected with the control end and the first signal end of the second switch subunit and used for controlling the second switch subunit to be switched off according to the first voltage control signal and the second voltage control signal when the first voltage control signal is a preset level signal, and the anti-backflow switch circuit improves the anti-backflow capacity of the circuit.
Description
Technical Field
The application relates to the technical field of electronics, concretely relates to prevent flowing backward switch circuit and chip.
Background
In an MCU (micro controller Unit) and a system on a chip, an analog switch is used as a core control component of an analog signal path, and is used for controlling the on-off of an analog signal and the selection of multiple analog signal paths. Among them, the simplest analog switch is implemented using a transmission gate.
However, when a commonly used transmission gate structure is used, if the signal voltage to be transmitted is higher than the power voltage of the control signal inside the chip, a certain switch tube constituting the transmission gate cannot be completely closed, and at this time, as the signal voltage input from the outside rises, the backward current flowing from the outside to the inside becomes larger and larger, so that the power consumption of the whole chip system rises, and the analog circuit structure inside the chip is further affected or damaged.
Disclosure of Invention
In view of this, the present application provides a back-flow prevention switch circuit and a chip to solve the technical problem that a certain switch tube in the existing transmission gate circuit structure cannot be closed to generate a back-flow of current.
A prevent flowing backward switch circuit, prevent flowing backward switch circuit includes:
the controllable switch unit comprises a first switch subunit and a second switch subunit which are connected in parallel, wherein a first end of the first switch subunit and a first end of the second switch subunit are electrically connected and serve as a first signal end, and a second end of the first switch subunit and a second end of the second switch subunit are electrically connected and serve as a second signal end;
the control signal processing unit is electrically connected with the control end of the first switch subunit, is respectively provided with a first electrical connection and a second electrical connection with the first boosting unit, and is used for outputting a first voltage control signal to the control end of the first switch subunit according to an input external control signal, outputting a first voltage control signal to the first boosting unit through the first electrical connection, and outputting a second voltage control signal to the first boosting unit through the second electrical connection, wherein the first voltage control signal and the second voltage control signal have opposite electrical properties;
and the first boosting unit is electrically connected with the control end of the second switch subunit and the first signal end and is used for adjusting the voltage of the control end of the second switch subunit to be the same as the voltage of the first signal end so as to turn off the second switch subunit according to the first voltage control signal and the second voltage control signal when the first voltage control signal is a preset level signal.
In one embodiment, the controllable switch unit further includes a third switch subunit and a fourth switch subunit connected in parallel, the third switch subunit has the same circuit structure as the first switch subunit, the fourth switch subunit has the same circuit structure as the second switch subunit, the first terminals of the third switch subunit and the fourth switch subunit are both electrically connected to the second signal terminal, the second terminal of the third switch subunit and the second terminal of the fourth switch subunit are electrically connected to each other and serve as a third signal terminal, the control signal processing unit is electrically connected to the control terminal of the third switch subunit to output the first voltage control signal, and the control signal processing unit is further configured to establish electrical connection with the control terminal of the fourth switch subunit to output the second voltage control signal;
the backflow prevention switch circuit further comprises an isolation unit, a first end of the isolation unit is electrically connected with the second signal end, a second end of the isolation unit is grounded, and the control signal processing unit is electrically connected with a control end of the isolation unit to output a second voltage control signal.
In one embodiment, the anti-backflow switch circuit further comprises a second boosting unit;
the control signal processing unit is also used for disconnecting the electrical connection with the control end of the fourth switch subunit and establishing electrical connection with the second boosting unit so as to respectively output a first voltage control signal and a second voltage control signal to the second boosting unit;
and the control signal processing unit is also used for disconnecting the electrical connection with the control end of the fourth switch subunit, establishing a third electrical connection and a fourth electrical connection with the second boosting unit respectively, outputting a first voltage control signal to the second boosting unit through the third electrical connection, and outputting a second voltage control signal to the second boosting unit through the fourth electrical connection.
In one embodiment, the first boosting unit includes: the first ends of the fifth switch subunit and the sixth switch subunit are electrically connected with the first signal end, the second end of the fifth switch subunit is electrically connected with the control end of the second switch subunit, the control end of the sixth switch subunit and the first end of the seventh switch subunit respectively, the second end of the sixth switch subunit is electrically connected with the control end of the fifth switch subunit and the first end of the eighth switch subunit respectively, the control end of the seventh switch subunit is electrically connected with the control signal processing unit, the control end of the eighth switch subunit is electrically connected with the control signal processing unit, the first electrical connection is established between the control end of the eighth switch subunit and the control signal processing unit, and the second ends of the seventh switch subunit and the eighth switch subunit are grounded.
In one embodiment, the second boosting unit has the same circuit structure as the first boosting unit.
In one embodiment, the fifth switch subunit and the sixth switch subunit both use PMOS transistors, and the seventh switch subunit and the eighth switch subunit both use NMOS transistors.
In one embodiment, the fifth switch subunit and the sixth switch subunit both use PNP transistors, and the seventh switch subunit and the eighth switch subunit both use NPN transistors.
In one embodiment, the isolation unit adopts NMOS tubes.
In one embodiment, the control signal processing unit includes a first inverter and a second inverter electrically connected to each other, the first inverter is configured to receive a first voltage control signal generated by an external control terminal to generate a second voltage control signal, and output the second voltage control signal to the first voltage boosting unit;
the second inverter is used for outputting a first voltage control signal to the control end of the first switch subunit and the first boosting unit.
In one embodiment, the first switch subunit adopts an NMOS transistor, and the second switch subunit adopts a PMOS transistor.
In addition, a chip is also provided, the chip comprises an analog circuit unit, at least one anti-backflow switch circuit and at least one input/output interface, wherein each input/output interface is correspondingly connected with the anti-backflow switch circuit to form a passage with the analog circuit unit, and the anti-backflow switch circuit is used for switching off when the analog function of at least one input/output interface is not used, so as to isolate the analog circuit unit.
Above-mentioned prevent flowing backward switch circuit, prevent flowing backward switch circuit includes: the controllable switch unit comprises a first switch subunit and a second switch subunit which are connected in parallel, wherein a first end of the first switch subunit and a first end of the second switch subunit are electrically connected and used as a first signal end, a second end of the first switch subunit and a second end of the second switch subunit are electrically connected and used as a second signal end, the control signal processing unit is electrically connected with a control end of the first switch subunit and the first boosting unit and used for outputting a first voltage control signal to the control end of the first switch subunit and outputting a first voltage control signal and a second voltage control signal to the first boosting unit according to an input external control signal, the first voltage control signal and the second voltage control signal are opposite in electrical property, the first boosting unit is electrically connected with the control end of the second switch subunit and the first signal end, the voltage of the control end of the second switch subunit is adjusted to be the first preset voltage signal to turn off the second switch subunit when the first voltage control signal is the preset level signal according to the first voltage control signal and the second voltage control signal, and the voltage of the control end of the second switch subunit is adjusted to be the same as the voltage of the first signal end when the second switch subunit in the controllable switch unit is the preset level signal through the cooperation of the control signal processing unit and the first boosting unit, so that the second switch subunit is turned off, the influence of an external input signal is isolated, and the technical problem of current backflow is solved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of a first circuit structure of a back-flow prevention switch circuit according to an embodiment of the present application;
fig. 2 is a schematic circuit diagram of a second circuit structure of a back-flow prevention switch circuit according to an embodiment of the present application;
fig. 3 is a schematic diagram of a third circuit structure of a backflow prevention switch circuit according to an embodiment of the present application;
fig. 4 is a schematic diagram of a fourth circuit structure of a backflow prevention switch circuit according to an embodiment of the present application;
fig. 5 is a schematic diagram of a fifth circuit structure of a back-flow prevention switch circuit according to an embodiment of the present application;
fig. 6 is a schematic diagram of a sixth circuit structure of a back-flow prevention switch circuit according to an embodiment of the present application;
fig. 7 is a schematic diagram of a seventh circuit structure of a back-flow prevention switch circuit according to an embodiment of the present application;
fig. 8 is a block diagram of a chip according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.
As shown in fig. 1, a back-flow prevention switch circuit 100 is provided, where the back-flow prevention switch circuit 100 includes:
the controllable switch unit 110 includes a first switch subunit 111 and a second switch subunit 112 connected in parallel, a first end 11 of the first switch subunit 111 and a first end 21 of the second switch subunit 112 are electrically connected and serve as a first signal end a1, and a second end 12 of the first switch subunit 111 and a second end 22 of the second switch subunit 112 are electrically connected and serve as a second signal end a 2;
the control signal processing unit 120 is electrically connected to the control terminal 13 of the first switch subunit 111, and is respectively electrically connected to the first boosting unit 130 to output a first voltage control signal to the control terminal 13 of the first switch subunit 111 according to an input external control signal, output a first voltage control signal to the first boosting unit 130 through the first electrical connection, and output a second voltage control signal to the first boosting unit 130 through the second electrical connection, where the first voltage control signal and the second voltage control signal are opposite in electrical property;
the first voltage boosting unit 130 is electrically connected to the control terminal 23 of the second switch subunit 112 and the first signal terminal a1, and is configured to adjust the voltage of the control terminal 23 of the second switch subunit 112 to be the same as the voltage of the first signal terminal a1 according to the first voltage control signal and the second voltage control signal when the first voltage control signal is a predetermined level signal, so as to turn off the second switch subunit 112.
In one embodiment, the controllable switch unit 110 adopts a transmission gate structure, the predetermined level signal is a low level signal, that is, the first voltage control signal is a low level signal, the second voltage control signal is a high level signal, the control terminal 13 of the first switch subunit 111 can be turned on only when the control terminal 13 is a high level signal and can be turned off only when the control terminal 23 of the corresponding second switch subunit 112 is a low level signal, and can be turned on only when the control terminal 23 of the first switch subunit 111 and can be turned off only when the control terminal 23 of the second switch subunit 112 are high level signals, in other words, the level signals of the control terminal 13 of the first switch subunit 111 and the level signal of the control terminal 23 of the second switch subunit 112 are opposite.
Since the first voltage boosting unit 130 is electrically connected to the control terminal 23 of the second switch subunit 112 and the first signal terminal a1, the second switch subunit 112 can be controlled to be turned off by adjusting the voltage of the control terminal 23 of the second switch subunit 112 to be the same as the voltage of the first signal terminal a1, so that when the predetermined level signal is a low level signal, the signal voltage is input to the first signal terminal a1, the voltage of the control terminal of the second switch subunit 112 is boosted to a high level signal by the voltage of the first signal terminal a1, and the second switch subunit 112 is completely turned off.
In this embodiment, when the first voltage control signal is a high level signal, the control terminal 13 of the first switch subunit 111 is a high level signal, the control terminal 23 of the second switch subunit 112 is a low level signal, both the first switch subunit 111 and the second switch subunit 112 can be turned on, and the current direction is from the first signal terminal a1 to the second signal terminal a 2.
In this embodiment, the current direction is from the first signal terminal a1 to the second signal terminal a2, and at this time, the anti-backflow switch circuit 100 only isolates the influence of the external input signal of the first signal terminal a1 to overcome the technical problem of current backflow of the first signal terminal a1, wherein the voltage of the first signal terminal a1 should be greater than the voltage of the second signal terminal, and the anti-backflow switch circuit 100 is only a unidirectional switch circuit.
The first switch subunit 111 usually employs an NMOS switch tube, and may also employ an NPN transistor, and the second switch subunit 112 usually employs a PMOS switch tube, and may also employ a PNP transistor.
In one embodiment, as shown in fig. 2, the first switch subunit 111 adopts an NMOS switch tube, the first terminal 11 of the first switch subunit 111 is a drain of the NMOS switch tube, the second terminal 12 of the first switch subunit 111 is a source of the NMOS switch tube, and the third terminal 13 of the first switch subunit 111 is a gate of the NMOS switch tube, and similarly, the second switch subunit 112 adopts a PMOS switch tube, the first terminal 21 of the second switch subunit 112 is a source of the PMOS switch tube, the second terminal 22 of the second switch subunit 112 is a drain of the PMOS switch tube, and the third terminal 23 of the second switch subunit 112 is a gate of the PMOS switch tube, wherein a substrate voltage of the PMOS switch tube is directly electrically connected to the first signal terminal a1, so that, when the predetermined level signal is a low level signal, the first signal terminal a1 inputs a signal voltage, the gate voltage of the PMOS tube in the second switch subunit 112 is pulled up to a high level signal by a voltage of the first signal terminal a1 and is the same as the corresponding substrate voltage, the PMOS switch in the second switch subunit 112 will be completely turned off.
In the anti-backflow switch circuit 100, by matching the control signal processing unit 120 and the first voltage boosting unit 130, when the first voltage control signal of the second switch subunit 112 in the controllable switch unit 110 is a preset level signal, the voltage of the control terminal 23 of the second switch subunit 112 is adjusted to be the same as the voltage of the first signal terminal a1, so that the second switch subunit 112 is turned off, thereby isolating the influence of the external input signal of the first signal terminal a1 and overcoming the technical problem of current backflow.
In one embodiment, as shown in fig. 3, the controllable switch unit 110 further includes a third switch subunit 113 and a fourth switch subunit 114 connected in parallel, the third switch subunit 113 and the first switch subunit 111 have the same circuit structure, the fourth switch subunit 114 and the second switch subunit 112 have the same circuit structure, the first terminal 31 of the third switch subunit 113 and the first terminal 41 of the fourth switch subunit 114 are both electrically connected to the second signal terminal a2, the second terminal 32 of the third switch subunit 113 and the second terminal 42 of the fourth switch subunit 114 are electrically connected to serve as a third signal terminal A3, the control signal processing unit 120 is electrically connected to the control terminal 33 of the third switch subunit 113 to output the first voltage control signal, and the control signal processing unit 120 is further configured to establish electrical connection with the control terminal 43 of the fourth switch subunit 114 to output the second voltage control signal;
the anti-backflow switch circuit 100 further includes an isolation unit 140, a first end of the isolation unit 140 is electrically connected to the second signal end a2, a second end of the isolation unit 140 is grounded, and the control signal processing unit 120 is electrically connected to the control end of the isolation unit 140 to output a second voltage control signal.
In the embodiment shown in fig. 1, the anti-backflow switch circuit 100 is a unidirectional switch circuit, so as to be shown in fig. 3, in the controllable switch unit 110, the third switch subunit 113 and the fourth switch subunit 114 connected in parallel are further disposed, and the anti-backflow switch circuit 100 is modified into a bidirectional switch circuit, at this time, the first terminal 31 of the third switch subunit 113 and the first terminal 41 of the fourth switch subunit 114 are both electrically connected to the second signal terminal a2, the second terminal 32 of the third switch subunit 113 and the second terminal 42 of the fourth switch subunit 114 are both electrically connected to serve as the third signal terminal A3, at this time, since the third switch subunit 113 and the first switch subunit 111 have the same circuit structure, and the fourth switch subunit 114 and the second switch subunit 112 have the same circuit structure, the anti-backflow switch circuit 100 becomes a bidirectional switch circuit, the external input signal can also be input from the third signal terminal A3, and the first signal terminal A1 can output.
In the embodiment shown in fig. 3, the controllable switch unit 110 adopts a transmission gate structure, the first switch subunit 111 and the second switch subunit 112 form a transmission gate circuit, the third switch subunit 113 and the fourth switch subunit 114 form another transmission gate circuit, the first switch subunit 111, the second switch subunit 112, the third switch subunit 113 and the fourth switch subunit 114 all adopt MOS switch tubes, and due to parasitic capacitances existing in the MOS switch tubes, when an external input signal is a high-frequency signal, a current flows from the first signal terminal a1 to the second signal terminal a2 through the parasitic capacitances or from the second signal terminal a2 to the first signal terminal a1 through the parasitic capacitances, so that the isolation unit 140 is further provided, the first terminal of the isolation unit 140 is electrically connected to the second signal terminal a2, the second terminal of the isolation unit 140 is grounded, the control signal processing unit 120 is electrically connected to the control terminal of the isolation unit 140 to output a second voltage control signal, when the second switch subunit 112 is turned off, a current path is formed between the isolation unit 140 and the first signal terminal a1, so that the correspondingly generated parasitic current flows directly to the ground; similarly, when the fourth switch subunit 114 is turned off, a current path is formed between the isolation unit 140 and the third signal terminal A3, so that the correspondingly generated parasitic current also flows to the ground directly, in other words, by providing the isolation unit 140, the potential of the second signal terminal a2 in the transmission gate structure is pulled to the ground level, thereby achieving a good isolation effect.
In one embodiment, as shown in fig. 4, the anti-backflow switching circuit 100 further includes a second boosting unit 150;
the control signal processing unit 120 is further configured to disconnect an electrical connection with the control terminal 43 of the fourth switch subunit 114, and establish a third electrical connection and a fourth electrical connection with the second voltage boosting unit 150, so as to output the first voltage control signal to the second voltage boosting unit 150 through the third electrical connection and output the second voltage control signal to the second voltage boosting unit 150 through the fourth electrical connection;
the second voltage boost unit 150 is electrically connected to the third signal terminal A3 and the control terminal 43 of the fourth switch subunit 114, and is configured to adjust the voltage of the control terminal 43 of the fourth switch subunit 114 to be the same as the voltage of the third signal terminal A3 according to the first voltage control signal and the second voltage control signal when the first voltage control signal is the preset level signal, so as to turn off the fourth switch subunit 114.
In the embodiment shown in fig. 2, since the anti-backflow switch circuit 100 is a bidirectional switch circuit, at this time, if an external input signal can be input from the third signal terminal A3, the first signal terminal a1 outputs, at this time, if the fourth switch subunit cannot be completely turned off, the problem of current backflow from the third signal terminal A3 still exists, at this time, the second voltage boosting unit 150 needs to be further disposed to prevent the current backflow from the third signal terminal A3, at this time, the control signal processing unit 120 is further configured to disconnect the electrical connection with the control terminal 43 of the fourth switch subunit 114, establish the third electrical connection and the fourth electrical connection with the second voltage boosting unit 150, so as to output the first voltage control signal through the third electrical connection and output the second voltage control signal to the second voltage boosting unit 150 through the fourth electrical connection, when the first voltage control signal is a predetermined level signal, according to the first voltage control signal and the second voltage control signal, the voltage of the control terminal 43 of the fourth switch subunit 114 is adjusted to the same voltage of the third signal terminal a3 so that the fourth switch subunit 114 is completely turned off. In this embodiment, the anti-backflow switch circuit 100 is used as a bidirectional switch, and the first voltage boosting unit 130 and the second voltage boosting unit 150 are simultaneously arranged, so that when the first voltage control signal is a preset level signal, the second switch subunit 112 and the fourth switch subunit 114 can be completely turned off, and therefore, when an external signal is input to the first signal terminal a1 or the third signal terminal A3, the current can be prevented from flowing backwards.
In one embodiment, as shown in fig. 5, the first boosting unit 130 includes: a fifth switching sub-unit 131, a sixth switching sub-unit 132, the seventh switch subunit 133 and the eighth switch subunit 134, the first end 51 of the fifth switch subunit 131 and the first end 61 of the sixth switch subunit 132 are both electrically connected to the first signal end a1, the second end 52 of the fifth switch subunit 131 is respectively electrically connected to the control end 23 of the second switch subunit 112, the control end 63 of the sixth switch subunit 132, and the first end 71 of the seventh switch subunit 133, the second end 62 of the sixth switch subunit 132 is respectively electrically connected to the control end 53 of the fifth switch subunit 131 and the first end 81 of the eighth switch subunit 134, the control signal processing unit 120 and the control end 73 of the seventh switch subunit 133 have a second electrical connection, the control signal processing unit 120 and the control end 83 of the eighth switch subunit 134 have a first electrical connection, and the second end 72 of the seventh switch subunit 133 and the second end 82 of the eighth switch subunit 134 are both grounded.
Preferably, PMOS transistors are used for the fifth switching subunit 131 and the sixth switching subunit 132, and NMOS transistors are used for the seventh switching subunit 133 and the eighth switching subunit 134.
The first end 51 of the fifth switch subunit 131 is a source corresponding to a PMOS switch transistor, the second end 52 of the fifth switch subunit 131 is a drain corresponding to a PMOS switch transistor, the control end 53 of the fifth switch subunit 131 is a gate corresponding to a PMOS switch transistor, the first end 61 of the sixth switch subunit 132 is a source corresponding to a PMOS switch transistor, the second end 62 of the sixth switch subunit 132 is a drain corresponding to a PMOS switch transistor, and the control end 63 of the sixth switch subunit 132 is a gate corresponding to a PMOS switch transistor.
The first end 71 of the seventh switch subunit 133 is a drain corresponding to the NMOS switch transistor, the second end 72 of the seventh switch subunit 133 is a source corresponding to the NMOS switch transistor, the control end 73 of the seventh switch subunit 134 is a gate corresponding to the NMOS switch transistor, the first end 81 of the eighth switch subunit 134 is a drain corresponding to the NMOS switch transistor, the second end 82 of the eighth switch subunit 134 is a source corresponding to the NMOS switch transistor, and the control end 83 of the eighth switch subunit 134 is a gate corresponding to the NMOS switch transistor.
In the fifth, sixth, seventh and eighth switching subunits 131, 132, 133 and 134, the substrate voltage of each switching tube is usually directly connected to the source.
In the first voltage boosting unit 130, the control signal processing unit 120 outputs the second voltage control signal to the control terminal 73 of the seventh switch subunit 133, outputs the first voltage control signal to the control terminal 83 of the eighth switch subunit 134, because the first voltage control signal and the second voltage control signal are opposite in electrical property, when the first voltage control signal is a low level signal, the second voltage control signal is a high level signal, at this time, the control terminal 83 of the eighth switch subunit 134 is a gate of an NMOS transistor, and is correspondingly turned off because of being in a low level state, the control terminal 73 of the seventh switch subunit 133 is a gate of an NMOS transistor and is correspondingly in a high level state, the seventh switch subunit 133 is naturally turned on, the voltage of the first terminal 71 corresponding to the seventh switch subunit 133 is pulled down to a ground voltage and is in a low level state, the control terminal 63 of the sixth switch subunit 132 is correspondingly turned on because of a low level signal, since the first terminal of the sixth switch subunit 132 is connected to the first signal terminal a1, the second terminal of the sixth switch subunit 132 is pulled up to the same voltage as the first signal terminal a1, and is in a high state, and the control terminal of the second switch subunit 112 is completely turned off due to the high signal.
In the embodiment shown in fig. 5, the second switch subunit 112 is a PMOS switch transistor, and since the substrate voltage and the gate voltage of the PMOS switch transistor are both the same as the voltage of the first signal terminal a1, the second switch subunit 112 is completely turned off.
In another embodiment, as shown in fig. 6, the fifth switch subunit 131 and the sixth switch subunit 132 may also adopt PNP transistors, the seventh switch subunit 133 and the eighth switch subunit 134 may also adopt NPN transistors, where the first end 51 of the fifth switch subunit 131 corresponds to an emitter of the PNP transistor, the second end 52 of the fifth switch subunit 131 corresponds to a collector of the PNP transistor, the control end 53 of the fifth switch subunit 131 corresponds to a base of the PNP transistor, the first end 61 of the sixth switch subunit 132 corresponds to an emitter of the PNP transistor, the second end 62 of the sixth switch subunit 132 corresponds to a collector of the PNP transistor, and the control end 63 of the sixth switch subunit 132 corresponds to a base of the PNP transistor.
The first end 71 of the seventh switch subunit 133 is a collector corresponding to the NPN type transistor, the second end 72 of the seventh switch subunit 133 is an emitter corresponding to the NPN type transistor, the control end 73 of the seventh switch subunit 133 is a base corresponding to the NPN type transistor, the first end 81 of the eighth switch subunit 134 is a collector corresponding to the NPN type transistor, the second end 82 of the eighth switch subunit 134 is an emitter corresponding to the NPN type transistor, and the control end 83 of the eighth switch subunit 134 is a base corresponding to the NPN type transistor.
In the first boosting unit 130, the control signal processing unit 120 outputs the second voltage control signal to the control terminal 73 of the seventh switch subunit 133, outputs the first voltage control signal to the control terminal 83 of the eighth switch subunit 134, because the first voltage control signal and the second voltage control signal are opposite in electrical property, when the first voltage control signal is a low level signal, the second voltage control signal is a high level signal, at this time, the control terminal 83 of the eighth switch subunit 134 is a base of an NPN type triode, and is correspondingly disconnected because of being in a low level state, the control terminal 73 of the seventh switch subunit 133 is a base of an NPN type triode and is correspondingly in a high level state, the seventh switch subunit 133 is naturally turned on, the voltage of the first terminal 71 corresponding to the seventh switch subunit 133 is pulled down to a ground voltage and is in a low level state, the control terminal 63 of the sixth switch subunit 132 is correspondingly turned on because of a low level signal, since the first terminal of the sixth switch subunit 132 is connected to the first signal terminal a1, the second terminal of the sixth switch subunit 132 is pulled up to the same voltage as the first signal terminal a1, and is in a high state, and the control terminal of the second switch subunit 112 is completely turned off due to the high signal.
In one embodiment, the second boosting unit 150 has the same circuit structure as the first boosting unit 130.
For example, as shown in fig. 7, each switch subunit in the first voltage boosting unit 130 adopts a MOS transistor circuit, the second voltage boosting unit 150 and the first voltage boosting unit 130 have the same circuit structure, the second voltage boosting unit 150 includes a ninth switch subunit 151, a tenth switch subunit 152, an eleventh switch subunit 153 and a twelfth switch subunit 154, wherein the ninth switch subunit 151 and the tenth switch subunit 152 both adopt PMOS transistors, the eleventh switch subunit 153 and the twelfth switch subunit 154 both adopt NMOS transistors, wherein the ninth switch subunit 151 corresponds to the fifth switch subunit 131, the eleventh switch subunit 153 corresponds to the sixth switch subunit 132, the eleventh switch subunit 153 corresponds to the seventh switch transistor 133, the twelfth switch subunit 154 corresponds to the eighth switch subunit 134, and wherein a fourth electrical connection is provided between gates of the NMOS switches in the control signal processing unit 120 and the eleventh switch subunit 153 to receive the corresponding switch transistors The second voltage control signal, the control signal processing unit 120, and the gates of the NMOS switch tubes in the twelfth switch subunit 154 are electrically connected to receive the corresponding first voltage control signal, and since the circuit structure of the second voltage boost circuit 150 is the same as that of the first voltage boost unit 130, the corresponding working process and principle are the same, and are not repeated here.
When the first voltage control signal is a low level signal, the second voltage control signal is a high level signal, the second boosting unit 150 works to boost the voltage of the control end of the fourth switch subunit 114 to be the same as the voltage of the third signal end A3, so that the control end 43 of the fourth switch subunit 114 is in a high level state, the fourth switch subunit 114 is completely turned off, and the technical disadvantage of current backflow of the third signal end A3 is overcome.
In another embodiment, when each switch subunit in the second voltage boosting unit 150 is a triode, each switch subunit in the first voltage boosting unit 130 may also be a MOS transistor; similarly, when the switch subunits in the second boosting unit 150 are MOS transistors, the switch subunits in the first boosting unit 130 may also be triodes, and the circuit structures of the corresponding first boosting unit 130 and the corresponding second boosting unit 150 refer to the circuit structures of the corresponding boosting units in the above corresponding embodiments.
In one embodiment, as shown in any one of fig. 5 to 7, the isolation unit 140 is an NMOS transistor, wherein a first end of the isolation unit 140 is a drain of the NMOS transistor and is connected to the second signal terminal a2, a second end of the isolation unit 140 is a source of the NMOS transistor and is grounded, a control end of the isolation unit 140 is a gate of the NMOS transistor and is connected to the control signal processing unit 120, the isolation unit 140 receives the second voltage control signal output by the control signal processing unit 120 through the control end, and is turned on when the second voltage control signal is a high-level signal, so that a current path is formed between the isolation unit 140 and the first signal terminal a1 when the second switch subunit 112 is turned off, and a parasitic current generated correspondingly flows to the ground directly; similarly, when the fourth switch subunit 114 is turned off, a current path is formed between the isolation unit 140 and the third signal terminal a3, so that the correspondingly generated parasitic current also flows to the ground directly.
In one embodiment, as shown in any one of fig. 5 to 7, the control signal processing unit 120 includes a first inverter D1 and a second inverter D2 electrically connected to each other, wherein the first inverter D1 is configured to receive a first voltage control signal generated by an external control terminal to generate a second voltage control signal, and output the second voltage control signal to the first voltage boosting unit 130;
the second inverter D2 is used for outputting the first voltage control signal to the control terminal 13 of the first switch subunit 111 and the first voltage boosting unit 130 according to the second voltage control signal output by the first inverter D1.
In addition, as shown in fig. 8, a chip 200 is further provided, where the chip 200 includes an analog circuit unit 210, at least one of the anti-backflow switch circuits 100 and at least one input/output interface I/O, where each input/output interface I/O is correspondingly connected to one of the anti-backflow switch circuits 100 to form a path with the analog circuit unit 210, and the anti-backflow switch circuit 100 is configured to be turned off when an analog function of the at least one input/output interface I/O is not used, so as to perform an isolation process on the analog circuit unit 210.
For simplicity, only one anti-backflow switch circuit 100 and a corresponding input/output interface I/O are shown in fig. 8.
When the analog function of any input/output interface I/O is not used, the current path between the input/output interface I/O and the analog circuit unit 210 can be completely closed by the corresponding anti-backflow switch circuit 100, so as to achieve a good isolation effect.
That is, the above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by using the contents of the specification and the drawings, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are included in the scope of the present application.
In addition, structural elements having the same or similar characteristics may be identified by the same or different reference numerals. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, the word "for example" is used to mean "serving as an example, instance, or illustration". Any embodiment described herein as "for example" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make and use the present application. In the foregoing description, various details have been set forth for the purpose of explanation.
It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes are not shown in detail to avoid obscuring the description of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Claims (11)
1. The utility model provides a prevent flowing backward switch circuit which characterized in that, prevent flowing backward switch circuit includes:
the controllable switch unit comprises a first switch subunit and a second switch subunit which are connected in parallel, wherein a first end of the first switch subunit and a first end of the second switch subunit are electrically connected and serve as a first signal end, and a second end of the first switch subunit and a second end of the second switch subunit are electrically connected and serve as a second signal end;
the control signal processing unit is electrically connected with the control end of the first switch subunit, is respectively provided with a first electrical connection and a second electrical connection with the first boosting unit, and is used for outputting a first voltage control signal to the control end of the first switch subunit according to an input external control signal, outputting the first voltage control signal to the first boosting unit through the first electrical connection, and outputting a second voltage control signal to the first boosting unit through the second electrical connection, wherein the first voltage control signal and the second voltage control signal are opposite in electrical property;
the first boosting unit is electrically connected with the control end of the second switch subunit and the first signal end, and is used for adjusting the voltage of the control end of the second switch subunit to be the same as the voltage of the first signal end so as to turn off the second switch subunit according to the first voltage control signal and the second voltage control signal when the first voltage control signal is a preset level signal.
2. The anti-backflow switching circuit of claim 1, wherein the controllable switching unit further comprises a third switching sub-unit and a fourth switching sub-unit connected in parallel, the third switch subunit has the same circuit structure as the first switch subunit, the fourth switch subunit has the same circuit structure as the second switch subunit, the first ends of the third switch subunit and the fourth switch subunit are electrically connected with the second signal end, the second end of the third switch subunit and the second end of the fourth switch subunit are electrically connected and used as a third signal end, the control signal processing unit is electrically connected with the control end of the third switch subunit to output the first voltage control signal, the control signal processing unit is also used for establishing electrical connection with the control end of the fourth switch subunit so as to output the second voltage control signal;
the backflow prevention switch circuit further comprises an isolation unit, a first end of the isolation unit is electrically connected with the second signal end, a second end of the isolation unit is grounded, and the control signal processing unit is electrically connected with a control end of the isolation unit to output the second voltage control signal.
3. The anti-backflow switch circuit according to claim 2, further comprising a second boost unit;
the control signal processing unit is further configured to disconnect an electrical connection with the control terminal of the fourth switch subunit, and establish a third electrical connection and a fourth electrical connection with the second boosting unit, respectively, so as to output the first voltage control signal to the second boosting unit through the third electrical connection, and output the second voltage control signal to the second boosting unit through the fourth electrical connection;
the second boosting unit is electrically connected with the third signal end and the control end of the fourth switch subunit respectively, and is used for adjusting the voltage of the control end of the fourth switch subunit to be the same as the voltage of the third signal end so as to turn off the fourth switch subunit according to the first voltage control signal and the second voltage control signal when the first voltage control signal is a preset level signal.
4. The anti-backflow switch circuit according to claim 3, wherein the first boosting unit comprises: a fifth switch subunit, a sixth switch subunit, a seventh switch subunit and an eighth switch subunit, the first ends of the fifth switch subunit and the sixth switch subunit are electrically connected with the first signal end, the second end of the fifth switch subunit is electrically connected with the control end of the second switch subunit, the control end of the sixth switch subunit and the first end of the seventh switch subunit respectively, the second end of the sixth switch subunit is electrically connected with the control end of the fifth switch subunit and the first end of the eighth switch subunit respectively, the control end of the control signal processing unit and the control end of the seventh switch subunit are electrically connected, the control signal processing unit is electrically connected with the control end of the eighth switch subunit, and the second ends of the seventh switch subunit and the eighth switch subunit are both grounded.
5. The anti-backflow switch circuit according to claim 4, wherein the second boosting unit and the first boosting unit have the same circuit structure.
6. The anti-backflow switch circuit according to claim 4, wherein the fifth switch subunit and the sixth switch subunit both use PMOS transistors, and the seventh switch subunit and the eighth switch subunit both use NMOS transistors.
7. The anti-backflow switch circuit according to claim 4, wherein the fifth switch subunit and the sixth switch subunit both employ PNP type triodes, and the seventh switch subunit and the eighth switch subunit both employ NPN type triodes.
8. The anti-backflow switch circuit according to claim 2, wherein the isolation unit adopts an NMOS tube.
9. The anti-backflow switch circuit according to claim 1, wherein the control signal processing unit comprises a first inverter and a second inverter electrically connected to each other, the first inverter is configured to receive a first voltage control signal generated by an external control terminal to generate a second voltage control signal, and output the second voltage control signal to the first boosting unit;
the second inverter is used for outputting the first voltage control signal to the control end of the first switch subunit and the first boosting unit.
10. The anti-backflow switch circuit according to claim 1, wherein the first switch subunit is an NMOS transistor, and the second switch subunit is a PMOS transistor.
11. A chip, comprising an analog circuit unit, at least one anti-backflow switch circuit according to any one of claims 1 to 10, and at least one input/output interface, wherein each input/output interface is correspondingly connected to an anti-backflow switch circuit to form a path with the analog circuit unit, and the anti-backflow switch circuit is configured to be turned off when the analog function of at least one input/output interface is not used, so as to perform isolation processing on the analog circuit unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111019368.9A CN113765065A (en) | 2021-08-31 | 2021-08-31 | Backflow prevention switch circuit and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111019368.9A CN113765065A (en) | 2021-08-31 | 2021-08-31 | Backflow prevention switch circuit and chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113765065A true CN113765065A (en) | 2021-12-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111019368.9A Pending CN113765065A (en) | 2021-08-31 | 2021-08-31 | Backflow prevention switch circuit and chip |
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| Country | Link |
|---|---|
| CN (1) | CN113765065A (en) |
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2021
- 2021-08-31 CN CN202111019368.9A patent/CN113765065A/en active Pending
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