CN113761826A - Method, system, terminal and storage medium for correcting PCB design lamination updating data - Google Patents
Method, system, terminal and storage medium for correcting PCB design lamination updating data Download PDFInfo
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- 238000013461 design Methods 0.000 title claims abstract description 214
- 238000003475 lamination Methods 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000003860 storage Methods 0.000 title claims abstract description 34
- 230000008676 import Effects 0.000 claims abstract description 12
- 238000012163 sequencing technique Methods 0.000 claims description 7
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- 238000011156 evaluation Methods 0.000 abstract description 13
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- 238000007689 inspection Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
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- 239000011810 insulating material Substances 0.000 description 1
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- 239000002184 metal Substances 0.000 description 1
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
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Abstract
The invention discloses a method, a system, a terminal and a storage medium for correcting PCB design lamination updating data, comprising the following steps: importing first version PCB design data and second version PCB design data; analyzing the lamination information of the first version PCB design data and the second version PCB design data, and storing the first version PCB design data and the second version PCB design data in groups according to respective laminations; and acquiring a first version data group and a second version data group corresponding to the target lamination, comparing the consistency of the first version data group and the second version data group, and marking inconsistent data items and then outputting and displaying. The invention can quickly realize the comparison between the quick import of the laminated data and the new and old versions. The work of setting and searching and checking with naked eyes by a large amount of manpower is reduced, the comparison of new and old versions in the evaluation stage is improved, and the period of the whole research and development team is shortened.
Description
Technical Field
The invention relates to the technical field of PCB design, in particular to a method, a system, a terminal and a storage medium for correcting PCB design lamination update data.
Background
The printed circuit board is designed based on a circuit schematic diagram to realize functions required by a circuit designer. The design of the printed circuit board mainly refers to layout design, and the layout of external connection needs to be considered. Optimized layout of internal electronic components, optimized layout of metal lines and vias, electromagnetic protection, heat dissipation, and the like. Excellent layout design can save production cost and achieve good circuit performance and heat dissipation performance. Simple layout design can be realized manually, and complex layout design needs to be realized by means of Computer Aided Design (CAD). At present, a plurality of PCB design software exist in the market, Cadence is used as the most widely applied software in the industry, not only is the Cadence provided with strong functions and a plurality of related software to support, but also because the Cadence provides an open secondary development interface and a more perfect development language library, a user can develop the Cadence according to the own needs. The speaker language is a high-level programming language which is built in Cadence software and is based on a C language and an LISP language, the Cadence provides rich interactive functions for the speaker language, and the work efficiency can be greatly improved by researching the speaker language and then writing tools.
With the increase of the integration level of the chip, the design of the PCB board is more and more complex, the number of layers of the PCB board is more and more, and the corresponding lamination data analyzed and output by the signal integrity is more and more. The laminated information needs a Layout engineer to manually input the laminated information into the Allegro PCB software little by little, and the manual input still has the risk of missing and filling errors, so before the circuit board is drawn, the Layout engineer needs to carefully correct whether the data is consistent with the data provided by the signal integrity analysis, the files are output to a board factory, and in order to ensure the circuit performance provided by the printed circuit board, the signal is not reflected in the transmission process, the signal is complete, the transmission loss is low, and the impedance matching effect is achieved. In order to ensure low signal distortion, low interference, low crosstalk and no electromagnetic interference of the PCB board, a reasonable impedance design is required in the PCB design. At present, competition is fierce, the updating and upgrading of electronic products are fast, the density requirement is higher and higher, the early evaluation of PCB layout is more and more important, how to quickly improve the early evaluation speed is more and more important, the bolt program is used for solving the comparison of new and old versions, the difference of lamination information is quickly and accurately compared, a research and development team can timely and accurately judge a problem point, a solution is found, and the research and development period is greatly shortened. For the Layout engineer, in addition to ensuring the short and open circuit qualification of the PCB, the impedance value is also ensured to be within a specified range, the period of the whole project is shortened by applying the professional rapid evaluation feasibility of the Layout engineer, the risk of missing and filling errors is certainly caused by visual inspection, and the skip program is designed for ensuring the performance of the PCB. Therefore, the working time of one-by-one inspection of the PCB Layout engineers can be reduced, omission of inspection by the Layout engineers is avoided, the evaluation time is shortened, the working efficiency of the whole research and development team is accelerated, and trouble of a factory end is avoided.
The existing PCB design has the following problems: the Allegro software cannot check whether the lamination information input by the layout engineer is accurate, the layout engineer must check whether the lamination information is correct by naked eyes, and when the number of laminations is large, the error probability is high and the time consumption is long; the number of laminated layers of the boards is increased from the boards with small number of laminated layers, the laminated information is increased, and the layout engineer can only correct and input the information one by one, thereby wasting too much time; the Allegro software cannot quickly finish the difference of the laminated plates after the line sequence sequencing is adjusted, which is proposed by a research and development team in the evaluation stage, and only can be used for correcting and comparing one by naked eyes. This can increase the time to evaluate and delay the development time of the entire development.
Disclosure of Invention
Aiming at the technical problem that the data difference of PCB layout patterns of different versions cannot be automatically compared in the prior art, so that the PCB design is easy to make mistakes, the invention provides a method, a system, a terminal and a storage medium for correcting the PCB design lamination updating data, and aims to solve the technical problem.
In a first aspect, the present invention provides a method for calibrating update data of a PCB design stack, including:
importing first version PCB design data and second version PCB design data;
analyzing the lamination information of the first version PCB design data and the second version PCB design data, and storing the first version PCB design data and the second version PCB design data in groups according to respective laminations;
and acquiring a first version data group and a second version data group corresponding to the target lamination, comparing the consistency of the first version data group and the second version data group, and marking inconsistent data items and then outputting and displaying.
Further, importing the first version PCB design data and the second version PCB design data includes:
designating a first storage path of the first version PCB design data, and designating a second storage path of the second version PCB design data;
the first version of PCB design data is read from the first memory path and the second version of PCB design data is read from the second memory path.
Further, analyzing the lamination information of the first version PCB design data and the second version PCB design data, and storing the first version PCB design data and the second version PCB design data in groups according to their respective laminations, including:
analyzing the number of the laminated layers, the laminated layer number and the data under each laminated layer number of the first version PCB design data, and analyzing the number of the laminated layers, the laminated layer number and the data under each laminated layer number of the second version PCB design data;
and grouping the first version PCB design data and the second version PCB design data according to the stack numbers to which the data belong respectively.
Further, a first version data group and a second version data group corresponding to the target lamination are collected, the consistency of the first version data group and the second version data group is compared, and inconsistent data items are marked and then output and displayed, wherein the method comprises the following steps:
comparing the consistency of all the lamination numbers of the first version PCB design data and the second version PCB design data, and outputting inconsistent lamination numbers;
respectively collecting the lamination completion time of the first version PCB design data and the second version PCB design data, and taking the lamination numbers with inconsistent completion time as target laminations;
traversing the data items of the first version data group and the second version data group, and comparing the data value consistency of each data item of the first version data group and the second version data group;
and sorting the inconsistent data items according to the priority of the data items, and marking the inconsistent data items according to the sorting and then outputting and displaying the inconsistent data items.
In a second aspect, the present invention provides a PCB design stack update data checking system, comprising:
the data import unit is used for importing the first version PCB design data and the second version PCB design data;
the laminated analysis unit is used for analyzing the laminated information of the first version PCB design data and the second version PCB design data and storing the first version PCB design data and the second version PCB design data in groups according to respective laminated layers;
and the mark display unit is used for acquiring the first version data group and the second version data group corresponding to the target lamination, comparing the consistency of the first version data group and the second version data group, and outputting and displaying the inconsistent data items after marking.
Further, the data import unit includes:
the path specifying module is used for specifying a first storage path of the first version PCB design data and specifying a second storage path of the second version PCB design data;
and the data reading module is used for reading the first version PCB design data from the first storage path and reading the second version PCB design data from the second storage path.
Further, the stack parsing unit includes:
the laminated analysis module is used for analyzing the laminated quantity, the laminated number and the data under each laminated number of the first version of PCB design data and analyzing the laminated quantity, the laminated number and the data under each laminated number of the second version of PCB design data;
and the lamination grouping module is used for grouping the first version PCB design data and the second version PCB design data according to the lamination numbers to which the data belong respectively.
Further, the mark display unit includes:
the laminated comparison module is used for comparing the consistency of all laminated numbers of the first version PCB design data and the second version PCB design data and outputting inconsistent laminated numbers;
the target selection module is used for respectively acquiring the lamination completion time of the first version PCB design data and the second version PCB design data, and taking the lamination numbers with inconsistent completion time as target laminations;
the data traversing module is used for traversing the data items of the first version data group and the second version data group and comparing the data value consistency of the data items of the first version data group and the second version data group;
and the difference display module is used for sequencing the inconsistent data items according to the priority of the data items and marking the inconsistent data items according to the sequencing and then outputting and displaying the inconsistent data items.
In a third aspect, a terminal is provided, including:
a processor, a memory, wherein,
the memory is used for storing a computer program which,
the processor is used for calling and running the computer program from the memory so as to make the terminal execute the method of the terminal.
In a fourth aspect, a computer storage medium is provided having stored therein instructions that, when executed on a computer, cause the computer to perform the method of the above aspects.
The beneficial effect of the invention is that,
the PCB design lamination updating data checking method provided by the invention is characterized in that first version PCB design data and second version PCB design data are imported, then lamination information of the first version PCB design data and the second version PCB design data is analyzed, the first version PCB design data and the second version PCB design data are stored in groups according to respective laminations, after the first version PCB design data and the second version PCB design data are grouped, a first version data group and a second version data group corresponding to a modified target lamination are collected, the consistency of the first version data group and the second version data group is compared, and inconsistent data items are marked and then output and displayed. The invention can quickly realize the comparison between the quick import of the laminated data and the new and old versions. The work of setting and searching and checking with naked eyes by a large amount of manpower is reduced, the comparison of new and old versions in the evaluation stage is improved, and the period of the whole research and development team is shortened.
The PCB design lamination updating data proofreading system provided by the invention is characterized in that first version PCB design data and second version PCB design data are imported through a data import unit, then a lamination analysis unit analyzes lamination information of the first version PCB design data and the second version PCB design data, the first version PCB design data and the second version PCB design data are stored in groups according to respective laminations, after the groups are grouped, a marking display unit collects a first version data group and a second version data group corresponding to a modified target lamination, the consistency of the first version data group and the second version data group is compared, and inconsistent data items are marked and output for display. The invention can quickly realize the comparison between the quick import of the laminated data and the new and old versions. The work of setting and searching and checking with naked eyes by a large amount of manpower is reduced, the comparison of new and old versions in the evaluation stage is improved, and the period of the whole research and development team is shortened.
The terminal provided by the invention comprises a processor for operating the PCB design lamination updating data checking method, and can quickly realize the comparison of the lamination data quick import and the new and old versions. The work of setting and searching and checking with naked eyes by a large amount of manpower is reduced, the comparison of new and old versions in the evaluation stage is improved, and the period of the whole research and development team is shortened.
The storage medium provided by the invention stores a program for executing the method for checking the PCB design laminated updating data, and the invention can quickly realize the comparison between the laminated data and the new and old versions. The work of setting and searching and checking with naked eyes by a large amount of manpower is reduced, the comparison of new and old versions in the evaluation stage is improved, and the period of the whole research and development team is shortened.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention.
FIG. 2 is a schematic block diagram of a system of one embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a terminal according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The technical problem solved by the invention is to adopt the Skill program in the PCB design to solve the problem that a PCB Layout engineer spends a great deal of time to input and check the accuracy of the set lamination information and the comparison of new and old versions by naked eyes. Therefore, the working efficiency of layout engineers is improved, the feasibility of evaluating the PCB in the shortest time is achieved, and the period of the whole research and development team is shortened.
Based on the defects of the prior art background and the prior art scheme, the invention provides the method for checking the updated data of the PCB design lamination, which improves a plurality of defects of the prior art scheme, can be used for setting and checking quickly by a layout engineer, is convenient for a signal integrity analysis engineer to check the accuracy quickly, shortens the period of an evaluation stage, and improves the work efficiency of the whole research and development team. The invention greatly improves the working efficiency and accuracy and is beneficial to improving the design quality.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention. The implementation body of fig. 1 may update the data verification system for a PCB design stack.
As shown in fig. 1, the method includes:
importing the PCB design data of the two versions needing to be compared.
the two versions of PCB design data are grouped by stack number.
And step 130, acquiring a first version data group and a second version data group corresponding to the target lamination, comparing the consistency of the first version data group and the second version data group, and marking inconsistent data items and then outputting and displaying.
In order to facilitate understanding of the present invention, the PCB design stack update data verification method provided by the present invention is further described below with reference to the principle of the PCB design stack update data verification method of the present invention and the process of verifying PCB design stack update data in the embodiments.
In this embodiment, the rapid import of the overlay information and the comparison between the new version and the old version are realized. The Cadence Allegro design software and Cadence Skill development language design is completed, a Skill program is written by using Cadence Skill language, the Skill program is put into a design software installation file, the Skill program is executed, and a PCB designer selects whether the version is a new version or a modified version in a popup menu. The PCB is a laminated structure and is mainly formed by laminating copper foil and insulating materials. In Allegro, the stack Setup is performed by selecting Setup-Cross-Section, and the stack Setup is managed in the form of a spreadsheet.
Specifically, the method for correcting the PCB design lamination updating data comprises the following steps:
and S1, importing the first version PCB design data and the second version PCB design data.
If the first version PCB design data and the second version PCB design data are locally stored, a first storage path of the first version PCB design data is appointed, and a second storage path of the second version PCB design data is appointed; the first version of PCB design data is read from the first memory path and the second version of PCB design data is read from the second memory path.
If the first version of PCB design data and the second version of PCB design data are not stored locally, the first version of PCB design data and the second version of PCB design data need to be stored locally.
The first version of PCB design data and the second version of PCB design data refer to different versions of the same PCB layout, assuming that the first version of PCB design data is an initial version and the second version of PCB design data is a modified version.
S2, analyzing the lamination information of the first version PCB design data and the second version PCB design data, and storing the first version PCB design data and the second version PCB design data in groups according to respective laminations.
Analyzing the number of the laminated layers, the laminated layer number and the data under each laminated layer number of the first version PCB design data, and analyzing the number of the laminated layers, the laminated layer number and the data under each laminated layer number of the second version PCB design data; and grouping the first version PCB design data and the second version PCB design data according to the stack numbers to which the data belong respectively.
For example, the analyzed first version PCB design data has 5 layers, which are a, b, c, d, and e, respectively, a page table is created for each layer, and the first version PCB design data is stored in the corresponding table according to the layer number to which the first version PCB design data belongs.
S3, collecting a first version data group and a second version data group corresponding to the target stack, comparing the consistency of the first version data group and the second version data group, and marking inconsistent data items for output and display.
Comparing the consistency of all the lamination numbers of the first version PCB design data and the second version PCB design data, and outputting inconsistent lamination numbers; respectively collecting the lamination completion time of the first version PCB design data and the second version PCB design data, and taking the lamination numbers with inconsistent completion time as target laminations; traversing the data items of the first version data group and the second version data group, and comparing the data value consistency of each data item of the first version data group and the second version data group; and sorting the inconsistent data items according to the priority of the data items, and marking the inconsistent data items according to the sorting and then outputting and displaying the inconsistent data items.
Firstly, whether the laminates of the two versions are consistent or not is checked, if the laminates of the PCB design data of the first version are a, b, c, d and e, and the laminates of the PCB design data of the second version are a, b, d and e, the modified version is explained to delete one laminate c.
For matching stacks, e.g. stacks a, b, d, e for both versions, the alignment targets are further determined: and each stack is marked with the last completion time, and the fact that the completion time of the layer a in the two versions is inconsistent is assumed, and the completion time of the second version is later, the modified version is explained to modify the content of the layer a. And if the completion time of the two versions of the b layer is consistent, the b layer data is not modified. At this time, layer a is determined as the target stack.
After the target lamination a is determined, reading a-layer table data of first version PCB design data and a-layer table data of second version PCB design data, wherein the a-layer table data of the two versions are divided into a plurality of data items, and comparing the data values of the data items of the first version data group and the second version data group to obtain inconsistent data items by traversing the data items of the first version data group and the second version data group. When the inconsistent data items are multiple, the inconsistent data items are sorted according to the priority of the data items prestored in the system, and the inconsistent data items are marked according to the sorting and then output and displayed, wherein the marks can be in a highlight format.
In other embodiments of the present invention, only the first version of PCB design data may be imported, and then the second version of PCB design data may be obtained by modifying the first version of PCB design data.
Specifically, after the first version PCB design data is imported, the first version PCB design data is parsed by the parsing method in step S2 to obtain 5 stack lists with the numbers a, b, c, d, and e, and the first version PCB design data is stored in the corresponding table according to the layer number to which the first version PCB design data belongs to obtain the PCB parameter table. If other departments need to modify the PCB design data, copying a PCB parameter table, and if the modification of the department is to change the lamination position, for example, changing the parameters of a and d, backing up the a table and the d table to obtain an a ' table and a d ' table, emptying the a table and the d table, importing the data in the a ' table into the d table, and importing the data in the d ' table into the a ' table, thereby realizing the lamination change. The parameter items and the specific parameter values of the parameter items may be modified in each stack table. The overlay list may also be deleted or added. And saving the file after the modification is completed, and naming the saved file as a second version (or naming the saved file by a department name or a completion time). The saved files are shared to the original department, and the original department can compare the first version PCB design data with the modified second version PCB data by using the step S3.
The embodiment can quickly realize the comparison between the stack data and the old and new versions. The work of setting and searching and checking with naked eyes by a large amount of manpower is reduced, the comparison of new and old versions in the evaluation stage is improved, and the period of the whole research and development team is shortened.
As shown in fig. 2, the system 200 includes:
a data import unit 210 for importing the first version PCB design data and the second version PCB design data;
a stack parsing unit 220, configured to parse stack information of the first version PCB design data and the second version PCB design data, and store the first version PCB design data and the second version PCB design data in groups according to respective stacks;
and the mark display unit 230 is configured to collect the first version data group and the second version data group corresponding to the target stack, compare consistency of the first version data group and the second version data group, and mark inconsistent data items for output and display.
Optionally, as an embodiment of the present invention, the data importing unit includes:
the path specifying module is used for specifying a first storage path of the first version PCB design data and specifying a second storage path of the second version PCB design data;
and the data reading module is used for reading the first version PCB design data from the first storage path and reading the second version PCB design data from the second storage path.
Optionally, as an embodiment of the present invention, the stack parsing unit includes:
the laminated analysis module is used for analyzing the laminated quantity, the laminated number and the data under each laminated number of the first version of PCB design data and analyzing the laminated quantity, the laminated number and the data under each laminated number of the second version of PCB design data;
and the lamination grouping module is used for grouping the first version PCB design data and the second version PCB design data according to the lamination numbers to which the data belong respectively.
Optionally, as an embodiment of the present invention, the mark display unit includes:
the laminated comparison module is used for comparing the consistency of all laminated numbers of the first version PCB design data and the second version PCB design data and outputting inconsistent laminated numbers;
the target selection module is used for respectively acquiring the lamination completion time of the first version PCB design data and the second version PCB design data, and taking the lamination numbers with inconsistent completion time as target laminations;
the data traversing module is used for traversing the data items of the first version data group and the second version data group and comparing the data value consistency of the data items of the first version data group and the second version data group;
and the difference display module is used for sequencing the inconsistent data items according to the priority of the data items and marking the inconsistent data items according to the sequencing and then outputting and displaying the inconsistent data items.
Fig. 3 is a schematic structural diagram of a terminal 300 according to an embodiment of the present invention, where the terminal 300 may be used to execute a PCB design stack update data calibration method according to the embodiment of the present invention.
Among them, the terminal 300 may include: a processor 310, a memory 320, and a communication unit 330. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not intended to be limiting, and may be a bus architecture, a star architecture, a combination of more or less components than those shown, or a different arrangement of components.
The memory 320 may be used for storing instructions executed by the processor 310, and the memory 320 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The executable instructions in memory 320, when executed by processor 310, enable terminal 300 to perform some or all of the steps in the method embodiments described below.
The processor 310 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or modules stored in the memory 320 and calling data stored in the memory. The processor may be composed of an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs connected with the same or different functions. For example, the processor 310 may include only a Central processing Unit (Central processing Unit). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.
A communication unit 330, configured to establish a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.
The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
Therefore, the method comprises the steps of importing the first version PCB design data and the second version PCB design data, analyzing the lamination information of the first version PCB design data and the second version PCB design data, storing the first version PCB design data and the second version PCB design data in a grouping mode according to respective laminations, collecting the first version data group and the second version data group corresponding to the modified target lamination after grouping, comparing the consistency of the first version data group and the second version data group, and outputting and displaying the inconsistent data items after marking. The invention can quickly realize the comparison between the quick import of the laminated data and the new and old versions. The work of setting and searching and checking with naked eyes by a large amount of manpower is reduced, the comparison of the evaluation stage to the new version and the old version is improved, and the period of the whole research and development team is shortened.
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in the form of a software product, where the computer software product is stored in a storage medium, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like, and the storage medium can store program codes, and includes instructions for enabling a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, and the like) to perform all or part of the steps of the method in the embodiments of the present invention.
The same and similar parts in the various embodiments in this specification may be referred to each other. Especially, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.
In the embodiments provided in the present invention, it should be understood that the disclosed system and method can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method for correcting PCB design lamination updating data is characterized by comprising the following steps:
importing first version PCB design data and second version PCB design data;
analyzing the lamination information of the first version PCB design data and the second version PCB design data, and storing the first version PCB design data and the second version PCB design data in groups according to respective laminations;
and acquiring a first version data group and a second version data group corresponding to the target lamination, comparing the consistency of the first version data group and the second version data group, and marking inconsistent data items and then outputting and displaying.
2. The method of claim 1, wherein importing the first and second versions of PCB design data comprises:
designating a first storage path of the first version PCB design data, and designating a second storage path of the second version PCB design data;
the first version of PCB design data is read from the first memory path and the second version of PCB design data is read from the second memory path.
3. The method of claim 1, wherein parsing stack information of the first version PCB design data and the second version PCB design data and storing the first version PCB design data and the second version PCB design data in groups of respective stacks comprises:
analyzing the number of the laminated layers, the laminated layer number and the data under each laminated layer number of the first version PCB design data, and analyzing the number of the laminated layers, the laminated layer number and the data under each laminated layer number of the second version PCB design data;
and grouping the first version PCB design data and the second version PCB design data according to the stack numbers to which the data belong respectively.
4. The method of claim 3, wherein the steps of collecting a first version data set and a second version data set corresponding to the target stack, comparing the consistency of the first version data set and the second version data set, and marking inconsistent data items for output and display comprise:
comparing the consistency of all the lamination numbers of the first version PCB design data and the second version PCB design data, and outputting inconsistent lamination numbers;
respectively collecting the lamination completion time of the first version PCB design data and the second version PCB design data, and taking the lamination numbers with inconsistent completion time as target laminations;
traversing the data items of the first version data group and the second version data group, and comparing the data value consistency of each data item of the first version data group and the second version data group;
and sorting the inconsistent data items according to the priority of the data items, and marking the inconsistent data items according to the sorting and then outputting and displaying the inconsistent data items.
5. A PCB design stack update data proofing system, comprising:
the data import unit is used for importing the first version PCB design data and the second version PCB design data;
the laminated analysis unit is used for analyzing the laminated information of the first version PCB design data and the second version PCB design data and storing the first version PCB design data and the second version PCB design data in groups according to respective laminated layers;
and the mark display unit is used for acquiring the first version data group and the second version data group corresponding to the target lamination, comparing the consistency of the first version data group and the second version data group, and outputting and displaying the inconsistent data items after marking.
6. The system of claim 5, wherein the data import unit comprises:
the path specifying module is used for specifying a first storage path of the first version PCB design data and specifying a second storage path of the second version PCB design data;
and the data reading module is used for reading the first version PCB design data from the first storage path and reading the second version PCB design data from the second storage path.
7. The system of claim 5, wherein the stack parsing unit comprises:
the laminated analysis module is used for analyzing the laminated quantity, the laminated number and the data under each laminated number of the first version of PCB design data and analyzing the laminated quantity, the laminated number and the data under each laminated number of the second version of PCB design data;
and the lamination grouping module is used for grouping the first version PCB design data and the second version PCB design data according to the lamination numbers to which the data belong respectively.
8. The system of claim 7, wherein the indicia display unit comprises:
the laminated comparison module is used for comparing the consistency of all laminated numbers of the first version PCB design data and the second version PCB design data and outputting inconsistent laminated numbers;
the target selection module is used for respectively acquiring the lamination completion time of the first version PCB design data and the second version PCB design data, and taking the lamination numbers with inconsistent completion time as target laminations;
the data traversing module is used for traversing the data items of the first version data group and the second version data group and comparing the data value consistency of the data items of the first version data group and the second version data group;
and the difference display module is used for sequencing the inconsistent data items according to the priority of the data items and marking the inconsistent data items according to the sequencing and then outputting and displaying the inconsistent data items.
9. A terminal, comprising:
a processor;
a memory for storing instructions for execution by the processor;
wherein the processor is configured to perform the method of any one of claims 1-4.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-4.
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|---|---|---|---|
| CN202111005456.3A CN113761826A (en) | 2021-08-30 | 2021-08-30 | Method, system, terminal and storage medium for correcting PCB design lamination updating data |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111005456.3A CN113761826A (en) | 2021-08-30 | 2021-08-30 | Method, system, terminal and storage medium for correcting PCB design lamination updating data |
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Application publication date: 20211207 |