CN113746464A - Self-adaptive substrate voltage regulating circuit with optimized LDMOS (laterally diffused metal oxide semiconductor) performance - Google Patents
Self-adaptive substrate voltage regulating circuit with optimized LDMOS (laterally diffused metal oxide semiconductor) performance Download PDFInfo
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- CN113746464A CN113746464A CN202111035555.6A CN202111035555A CN113746464A CN 113746464 A CN113746464 A CN 113746464A CN 202111035555 A CN202111035555 A CN 202111035555A CN 113746464 A CN113746464 A CN 113746464A
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- 238000005468 ion implantation Methods 0.000 description 2
- 239000003381 stabilizer Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Abstract
The invention provides a self-adaptive substrate voltage regulating circuit with optimized LDMOS performance, which controls the substrate voltage of an LDMOS off state and an LDMOS on state through a voltage comparator and a single-input double-output direct-current stabilized power supply converter, improves the breakdown voltage of the off state, ensures the on state performance to be unchanged, and improves the compromise relationship of the two. In the actual manufacturing process, the technology can be realized by adopting the conventional CMOS process without adding extra mask plates and process flows, and the preparation is simple and the cost is low.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to an adaptive substrate voltage regulating circuit with optimized LDMOS performance.
Background
The LDMOS (lateral diffusion field effect transistor) has the advantages of high gain, high transconductance, high output power, high linearity, easiness in integration with a CMOS (complementary metal oxide semiconductor) and the like, and is widely applied to power amplifiers of wireless communication base stations, power amplifiers of radar transmitters and the like. It has two forms: fully depleted and not fully depleted, and currently, the non-fully depleted technology (channel length from 130nm to 45nm) is the mainstream technology for radio frequency integrated circuits. Although the non-fully depleted LDMOS has higher drive current and radio frequency characteristics, the breakdown voltage is lower because the RESURF effect of the drift region is weakened due to partial depletion of the drift region. The drift region can be completely depleted by techniques such as linear Doping (VLD), variable Thickness (VLT), Field Plate (Field Plate, FP), and the like, so as to increase the breakdown voltage, but the on-state performance of the device, such as on-resistance, transconductance, and the like, can also be sacrificed, and further the radio frequency performance, the switching performance, and the like of the device can be deteriorated. Therefore, how to maintain good on-state performance while increasing the breakdown voltage is one of the hot spots studied by experts.
Sithanandam et al, in the document "Linear and Speed Optimization in SOI LDMOS using Gate Engineering", propose a dual material Gate LDMOS structure, as shown in FIG. 2, which introduces three stepped field plates in the Gate oxide. The first gate field plate 11 is p + poly, and the other two gate field plates 12 are n + poly. And as the drift region is added with a new electric field peak value, the electric field is uniform, and the breakdown voltage is improved. The grid field plate adopts two materials, the difference of the work functions of the two materials causes the change of surface potential, the concentration of a drift region is increased, and therefore the on-state performance is optimized. But this structure introduces three stepped gate field plates, increasing process complexity and device cost.
Luo et al, in the document "A High Performance RF LDMOSFET in Thin Film SOI Technology with Step Drift Profile", propose a Drift region Step-doped LDMOS structure, which is formed by performing ion implantation several times through different windows in a semiconductor region 3 as a Drift region, as shown in FIG. 3. A new peak value is introduced into the electric field of the drift region, so that the breakdown voltage is improved; and as the concentration of the step doping is gradually increased, the concentration of a drift region is optimized, namely the on-state performance is optimized. But the realization of the doping of the stepped drift region of the structure increases the mask plate and the ion implantation, and greatly increases the complexity and the cost of the process.
Disclosure of Invention
In order to solve the technical problem, the invention provides the self-adaptive substrate voltage regulating circuit with the optimized LDMOS performance, which can ensure the good on-state performance of the device while improving the breakdown voltage and improve the compromise relationship between the breakdown voltage and the on-state performance.
An adaptive substrate voltage regulating circuit with optimized LDMOS performance comprises an LDMOS and a peripheral circuit, wherein,
the channel region and the drift region of the LDMOS are not fully depleted;
the peripheral circuit comprises a voltage comparator and a single-input double-output direct-current stabilized power supply converter;
the positive power output end of the single-input double-output direct-current stabilized power supply converter is connected with the inverting input end of the voltage comparator;
the negative power supply output end of the single-input double-output direct-current stabilized power supply converter is connected with the low-level end of the voltage comparator;
the grid electrode of the LDMOS is connected with the non-inverting input end of the voltage comparator;
the substrate of the LDMOS is connected with the output end of the voltage comparator;
the high-level end of the voltage comparator is grounded;
the positive output power supply voltage of the single-input double-output direct-current stabilized power supply converter is not greater than the threshold voltage of the LDMOS;
and the negative output power supply voltage of the single-input double-output direct-current stabilized power supply converter is equal to the optimal substrate voltage of the LDMOS.
Further, when the LDMOS is in the on state, the substrate voltage is the high level terminal voltage of the voltage comparator, i.e., ground voltage (0V).
When the LDMOS is in an off state, the substrate voltage is the low-level terminal voltage of the voltage comparator, namely the optimal substrate voltage of the LDMOS.
Go toStep (b), said optimum substrate voltage Vsb *The value is a negative value and is determined by the concentration of a drift region, the length of the drift region, the thickness of an epitaxial layer, the thickness of a buried oxide layer and the like of the LDMOS, and the value is as follows:
wherein the content of the first and second substances,
tsand tiIs the thickness of the epitaxial layer and the buried oxide layer, εsAnd εiIs the dielectric constant of the epitaxial layer and the buried oxide layer, EcIs the critical electric field, LdIs the drift region length, q is the amount of charge, NdIs the drift region concentration.
The invention has the beneficial effects that: according to the self-adaptive substrate voltage regulating circuit with the optimized LDMOS performance, disclosed by the invention, when the LDMOS is in an off state, a negative voltage is applied to the substrate of the LDMOS, the depletion of a drift region is improved, the breakdown voltage and the FOM value are improved, and in addition, the leakage current is also reduced; when the substrate voltage of the LDMOS is grounded in the on state, namely the negative voltage in the off state is removed, the on-state performance is not deteriorated due to the influence of the negative voltage, and therefore the compromise relation between the off-state performance and the on-state performance is improved. In addition, the technology can be realized by adopting the conventional CMOS process, additional mask plates and process flows are not required to be added, the preparation is simple, and the cost is low.
Drawings
In order that the present invention may be more readily and clearly understood, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings.
FIG. 1 is a schematic diagram in accordance with the principles of the present invention;
FIG. 2 is a schematic diagram of a prior art dual material gate LDMOS structure;
FIG. 3 is a schematic diagram of a prior art LDMOS structure with a step-doped drift region;
FIG. 4 is a circuit schematic of a single input dual output DC-regulated power converter;
FIG. 5 is a current-voltage curve for the off-state and on-state of the LDMOS with no substrate voltage applied;
FIG. 6 is a current-voltage curve for the off-state and on-state of the LDMOS with a negative substrate voltage applied;
FIG. 7 is a current-voltage curve for the off-state and on-state of an LDMOS device, according to an embodiment of the invention.
The structure comprises a semiconductor substrate 1, a buried oxide layer 2, a semiconductor region 3, a semiconductor drain region 4, a semiconductor body 5, a semiconductor source region 6, a gate oxide layer 7, drain metal 8, source metal 9, a gate electrode 10, a first gate field plate 11, a second gate field plate 12 and a third gate field plate 13.
Detailed Description
As shown in fig. 1, the schematic diagram of an adaptive substrate voltage regulation circuit for LDMOS performance optimization according to the present invention includes a conventional LDMOS and peripheral circuits (in dashed box), wherein,
the channel region and the drift region of the conventional LDMOS are not fully depleted;
the peripheral circuit comprises a voltage comparator and a single-input double-output direct-current stabilized power supply converter. The single-input double-output direct-current stabilized power supply can realize a double-output integrated stabilized power supply, wherein one path is adjustable positive voltage, and the other path is adjustable negative voltage. Fig. 4 shows an embodiment of a single-input dual-output dc voltage-stabilized power converter. The three-terminal adjustable direct current power supply is mainly realized by a direct current power supply, an operational amplifier, a three-terminal adjustable positive voltage stabilizer, a three-terminal adjustable negative voltage stabilizer, a resistor, a capacitor and a diode. The positive power supply voltage output by the embodiment is not less than the threshold voltage of the lateral diffusion field effect transistor, and the negative voltage output by the embodiment is the optimal substrate voltage of the LDMOS.
The positive power output end of the single-input double-output direct-current stabilized power supply converter is connected with the inverting input end of the voltage comparator;
the negative power supply output end of the single-input double-output direct-current stabilized power supply converter is connected with the low-level end of the voltage comparator;
the grid electrode of the transverse diffusion field effect transistor is connected with the non-inverting input end of the voltage comparator;
the substrate of the transverse diffusion field effect transistor is connected with the output end of the voltage comparator;
the high-level end of the voltage comparator is grounded.
The structure on the right in fig. 1 is a schematic two-dimensional structure of a conventional LDMOS, and the conventional LDMOS is composed of a semiconductor substrate 1, a buried oxide layer 2, an epitaxial layer, which includes a semiconductor region 3 as a drift region, a semiconductor drain region 4, a semiconductor body region 5, a semiconductor source region 6, a gate oxide layer 7, a drain metal 8, a source metal 9, and a gate electrode 10.
The self-adaptive substrate voltage regulation process of the LDMOS in this embodiment is as follows:
case 1: when the LDMOS is turned off, namely the grid voltage of the LDMOS is smaller than the positive power supply voltage Vout + output by the single-input double-output direct-current stabilized power supply converter, the voltage comparator outputs low level. Because the low level of the voltage comparator is connected with the negative power supply output end of the single-input double-output direct-current stabilized power supply converter, the substrate of the LDMOS is connected with the negative voltage at the moment.
Case 2: when the LDMOS is started, namely the grid voltage of the LDMOS is larger than the positive power supply voltage Vout + output by the single-input double-output direct-current stabilized voltage supply converter, the voltage comparator outputs high level. Since the high level of the voltage comparator is grounded, the substrate of the LDMOS is grounded at this time.
To verify the beneficial effects of embodiments of the present invention, fig. 5-7 show the off-state and on-state current-voltage curves of LDMOS for three cases: (1) no substrate voltage is applied; (2) applying a negative substrate voltage; (3) the embodiment of the invention is adopted. The drift region concentration for these three cases was 1.8 × 1017cm-3The length of the drift region is 5 μm, and the thicknesses of the top silicon layer and the buried oxide layer are both 0.2 μm.
As can be seen from FIG. 5, the off-state breakdown voltage of the LDMOS with no substrate voltage applied is lower, 23.74V; when a negative substrate voltage is applied, the off-state breakdown voltage is increased, as shown in fig. 6, the breakdown voltage is 50.19V, which is increased by 111%. This is because when the substrate voltage is not applied, the drift region has a high concentration and is not completely depleted, and the potential line is concentrated at the source terminal, and PN junction breakdown occurs, so that the breakdown voltage is low. When the substrate applies negative breakdown voltage, depletion is gradually enhanced along with the increase of the negative substrate voltage until the drift region is completely depleted, N + N junction breakdown occurs, and the breakdown voltage is greatly improved. When the breakdown of the N + N junction just occurs, the substrate voltage for realizing the optimal LDMOS performance, namely the optimal substrate voltage, can be obtained through numerical solution. The LDMOS is determined by the concentration of a drift region, the length of the drift region, the thickness of an epitaxial layer, the thickness of a buried oxide layer and the like of the LDMOS, and the LDMOS has the following values:
wherein the content of the first and second substances,
tsand tiIs the thickness of the epitaxial layer and the buried oxide layer, εsAnd εiIs the dielectric constant of the epitaxial layer and the buried oxide layer, EcIs the critical electric field, LdIs the drift region length, q is the amount of charge, NdIs the drift region concentration.
However, the on-state performance of the device must be sacrificed for the improvement of the off-state breakdown voltage, and it is obvious that the leakage current is reduced under the same gate voltage, and therefore the on-state on-resistance, transconductance and the like are also reduced, compared with the on-state output characteristic curves in fig. 5 and fig. 6. In addition, when the gate voltage is less than 2V, the kink effect is enhanced and the performance of the device is degraded. This is because the presence of the negative substrate voltage modulates the charge in the drift region, affecting the electric field in the drift region and the channel region, resulting in a decrease in leakage current and an increase in the kink effect, deteriorating the on-state performance of the LDMOS.
By adopting the embodiment of the invention, as shown in fig. 7, the substrate is connected with the optimal substrate voltage in the off state and is a negative voltage, so that the improvement maximization of the off-state breakdown voltage is realized; when the switch is in the on state, the substrate is grounded, namely the substrate voltage is removed, and the switch is ensured to have good on-state performance. In addition, the FOM value of the LDMOS in the embodiment is also improved by 3 times due to the improvement of the breakdown voltage in the off state. Off-state leakage current is also reduced due to the modulation of charge in the channel and drift regions by the negative substrate voltage, and is less sensitive to temperature, exhibiting better reliability and stability. The embodiment does not need to add extra mask plates and process steps, can optimize the compromise relation of off-state performance and on-state performance by using a conventional CMOS process, and is simple to prepare and low in cost.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and all equivalent variations made by using the contents of the present specification and the drawings are within the protection scope of the present invention.
Claims (4)
1. An adaptive substrate voltage regulating circuit with optimized LDMOS performance is characterized by comprising an LDMOS and a peripheral circuit, wherein,
the channel region and the drift region of the LDMOS are not fully depleted;
the peripheral circuit comprises a voltage comparator and a single-input double-output direct-current stabilized power supply converter;
the positive power output end of the single-input double-output direct-current stabilized power supply converter is connected with the inverting input end of the voltage comparator;
the negative power supply output end of the single-input double-output direct-current stabilized power supply converter is connected with the low-level end of the voltage comparator;
the grid electrode of the LDMOS is connected with the non-inverting input end of the voltage comparator;
the substrate of the LDMOS is connected with the output end of the voltage comparator;
the high-level end of the voltage comparator is grounded;
the positive output power supply voltage of the single-input double-output direct-current stabilized power supply converter is not greater than the threshold voltage of the LDMOS;
and the negative output power supply voltage of the single-input double-output direct-current stabilized power supply converter is equal to the optimal substrate voltage of the LDMOS.
2. The adaptive substrate voltage regulating circuit for LDMOS performance optimization of claim 1, wherein the substrate voltage is a high-level terminal voltage of the voltage comparator when the LDMOS is in an on state, i.e., the ground voltage is 0V.
3. The adaptive substrate voltage regulator circuit for LDMOS device performance optimization of claim 1, wherein the substrate voltage is the low level terminal voltage of the voltage comparator, i.e., the optimal substrate voltage of the LDMOS device, when the LDMOS device is in the off state.
4. The LDMOS performance optimized adaptive substrate voltage regulation circuit of claim 3, wherein the optimal substrate voltage Vsb *Is negative and has the following values:
wherein the content of the first and second substances,
tsand tiIs the thickness of the epitaxial layer and the buried oxide layer, εsAnd εiIs the dielectric constant of the epitaxial layer and the buried oxide layer, EcIs the critical electric field, LdIs the drift region length, q is the amount of charge, NdIs the drift region concentration.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007015442A1 (en) * | 2005-08-02 | 2007-02-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit |
| WO2012055225A1 (en) * | 2010-10-28 | 2012-05-03 | 电子科技大学 | High voltage ldmos device |
| CN102790088A (en) * | 2012-07-20 | 2012-11-21 | 昆山华太电子技术有限公司 | Breakdown voltage-adjustable RF-LDMOS device |
| WO2015021927A1 (en) * | 2013-08-13 | 2015-02-19 | 无锡华润上华半导体有限公司 | Laterally double-diffused metal-oxide-semiconductor field effect transistor |
| WO2020228202A1 (en) * | 2019-05-16 | 2020-11-19 | 东南大学 | Gate electrode driving circuit for reducing reverse recovery current of power component |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007015442A1 (en) * | 2005-08-02 | 2007-02-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit |
| WO2012055225A1 (en) * | 2010-10-28 | 2012-05-03 | 电子科技大学 | High voltage ldmos device |
| CN102790088A (en) * | 2012-07-20 | 2012-11-21 | 昆山华太电子技术有限公司 | Breakdown voltage-adjustable RF-LDMOS device |
| WO2015021927A1 (en) * | 2013-08-13 | 2015-02-19 | 无锡华润上华半导体有限公司 | Laterally double-diffused metal-oxide-semiconductor field effect transistor |
| WO2020228202A1 (en) * | 2019-05-16 | 2020-11-19 | 东南大学 | Gate electrode driving circuit for reducing reverse recovery current of power component |
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