CN113746453A

CN113746453A - Frequency adjustment circuit, method and communication equipment

Info

Publication number: CN113746453A
Application number: CN202111307933.1A
Authority: CN
Inventors: 王本川
Original assignee: Beijing Thinking Semiconductor Technology Co ltd
Current assignee: Beijing Thinking Semiconductor Technology Co ltd
Priority date: 2021-11-05
Filing date: 2021-11-05
Publication date: 2021-12-03

Abstract

The disclosure relates to a frequency adjustment circuit, a method and a communication device, which solve the technical problem of data packet receiving errors caused by sampling frequency deviation between a transmitter and a receiver. The circuit comprises a crystal resonator, a start-oscillation circuit and a programmable capacitor array, wherein the crystal resonator is connected with the start-oscillation circuit in parallel, the programmable capacitor array is connected with the crystal resonator and comprises a plurality of capacitor arrays which are sequentially connected in parallel, each capacitor array can independently output codes, and a target capacitor array used for coding each time is determined according to the value of part of bits in the codes to be output. The method and the device perform piecewise fitting on straight lines through the programmable capacitor array, linearize the traction sensitivity of the crystal resonator, ensure the frequency of the crystal resonator to control monotonicity along with control coding, realize accurate calibration of frequency step length, and ensure normal transmission of data between a transmitter and a receiver.

Description

Frequency adjustment circuit, method and communication equipment

Technical Field

The present disclosure relates to the field of power line communication, and in particular, to a frequency adjustment circuit, a method, and a communication device.

Background

The crystal resonator has high precision and high stability, and is widely applied to the technical fields of communication transmission and the like. In the power line communication process, because the frequencies of the crystal resonators between the transmitter and the receiver are not completely synchronized, a sampling frequency deviation exists between a signal received by the receiver and a signal sent by the transmitter, and the accumulation of the sampling frequency deviation along with time causes an error in a data packet received by the receiver.

In the related art, the invention patent applications with application publication numbers (CN 113037219A) and (CN 113037215A) both provide a crystal oscillator control circuit, and a signal processing module of the crystal oscillator control circuit provided in the invention patent application (CN 113037219A) performs preset processing on a received first clock signal to obtain a second clock signal, and outputs the second clock signal to a capacitor array control module; the capacitor array control module generates a first control signal under the control of the second clock signal and outputs the first control signal to the capacitor array module; the capacitor array module sets an initial capacitance value of the crystal oscillator under the control of the first control signal, and when the crystal oscillator waveform reaches a preset amplitude, the load capacitor is controlled to reach a target capacitance value by increasing the set capacitance value every time, so that the oscillation starting waveform and the oscillation frequency of the crystal oscillator are adjusted. The crystal oscillator driving module of the crystal oscillator control circuit provided by the invention patent application (CN 113037215A) provides driving energy for a crystal oscillator and outputs a first clock signal generated by the crystal oscillator to the frequency output module and the capacitor array control module; the capacitor array control module generates a control signal under the control of the first clock signal, and the control signal is used for adjusting the capacitance value of the capacitor array module, so that the output frequency and the power consumption of the crystal oscillator are smoothly controlled. The invention patent with the publication number of (CN 101924534B) provides a monotonous tuning method for a digitally controlled capacitor switch array of a crystal oscillator, in which a digital decoding circuit directly converts an input digital control bit into an actual control signal of the switch array, each switch in the switch array correspondingly controls one capacitor unit of a multilayer metal interdigital capacitor array, and the number of the capacitor units connected to the crystal oscillator in the multilayer metal interdigital capacitor array is adjusted by turning on and off each switch in the switch array, that is, the total capacitance of the crystal oscillator is adjusted, thereby realizing monotonous tuning of the crystal oscillator. It can be seen that in the related art, the control of the crystal oscillator frequency is mostly realized by adjusting the capacitance of the capacitance array module, but with the continuous increase of the load capacitance of the crystal oscillator, the step length of the crystal oscillator frequency is inconsistent, so that the adjustable range of the crystal oscillator is limited, the frequency consistency of the transmitter and the receiver cannot be ensured, the decrease of the load capacitance leads to the increase of the frequency, and otherwise, the increase of the load capacitance leads to the decrease of the frequency.

In the related technology, a square wave with standard frequency can be input through a chip IO, the deviation between the crystal oscillator frequency and the standard frequency is calculated by using a digital algorithm, and the load resonance frequency of the crystal oscillator is finely adjusted by adjusting the load capacitance of the crystal resonator. However, the square wave of the standard frequency has a frequency deviation of (-2 ppm-2 ppm), and frequency modulation according to the standard frequency is difficult to perform, so that accurate frequency calibration is realized, and thus, a sampling frequency deviation still exists between a transmitter and a receiver, and data transmission errors are caused.

Disclosure of Invention

The present disclosure provides a frequency adjustment circuit, a method and a communication device, which solve the technical problem of data packet reception errors caused by sampling frequency deviation between a transmitter and a receiver in the related art.

In order to achieve the above object, in a first aspect, the present disclosure provides a frequency adjustment circuit, where the circuit includes a crystal resonator, a start-up circuit, and a programmable capacitor array, the crystal resonator is connected in parallel with the start-up circuit, the programmable capacitor array is connected to the crystal resonator, the programmable capacitor array includes a plurality of capacitor arrays connected in parallel in sequence, each capacitor array is capable of operating independently, and a target capacitor array for encoding each time in the programmable capacitor array is determined according to values of part of bits in a code to be output.

Optionally, when the circuit includes two programmable capacitor arrays, one end of a first programmable capacitor array is connected to a crystal oscillator input pin of the crystal resonator, and the other end of the first programmable capacitor array is grounded;

one end of the second programmable capacitor array is connected with a crystal oscillator output pin of the crystal resonator, and the other end of the second programmable capacitor array is grounded.

Optionally, when the circuit includes more than two programmable capacitor arrays, each of the programmable capacitor arrays is sequentially connected in series and then is connected between a crystal oscillator input pin and a crystal oscillator output pin of the crystal resonator.

Optionally, the programmable capacitor array comprises a coarse tuning sub-circuit and a fine tuning sub-circuit connected in parallel with the coarse tuning sub-circuit;

the fine tuning sub-circuit comprises a segmented thermometer code decoder and a segmented thermometer code fine tuning capacitor array connected with the segmented thermometer code decoder, and the coarse tuning sub-circuit comprises a segmented binary code decoder and a segmented binary code coarse tuning capacitor array connected with the segmented binary code decoder;

the fine tuning sub-circuit and the coarse tuning sub-circuit can output independent codes, and the target capacitor array used for coding in each time in the segmented thermometer code fine tuning capacitor array and the segmented binary code coarse tuning capacitor array is determined according to values of part of bits in the codes to be output.

Optionally, the segmented thermometer code fine tuning capacitor array includes a plurality of first capacitor sub-circuits connected in parallel in sequence, and each of the first capacitor sub-circuits includes a capacitor and a control switch connected in series in sequence.

Optionally, the segmented binary code coarse tuning capacitor array includes a plurality of capacitor arrays connected in parallel in sequence, and the unit capacitance of each capacitor array increases in sequence.

Optionally, the capacitor array in the segmented binary code coarse tuning capacitor array includes a plurality of second capacitor sub-circuits connected in parallel in sequence, and each second capacitor sub-circuit includes a capacitor and a control switch connected in series in sequence.

Optionally, the opening and closing of the control switch is determined according to values of a part of bits in the code to be output.

In a second aspect, the present disclosure provides a frequency adjustment method, performed by the frequency adjustment circuit of the first aspect, the method comprising:

acquiring the frequency deviation between the frequency of each crystal resonator to be adjusted at the receiver and the transmitting end and a preset standard frequency, and performing factory calibration on the frequency of each crystal resonator according to the frequency deviation;

and acquiring the sampling frequency deviation between the receiver and the crystal resonator at the transmitting end after factory calibration, and performing communication calibration on the frequency of each crystal resonator according to the sampling frequency deviation.

In a third aspect, the present disclosure provides a communication device comprising the frequency adjustment circuit of the first aspect.

By the technical scheme, the programmable capacitor array is controlled by the codes to perform piecewise fitting on straight lines, the traction sensitivity of the crystal resonator is linearized, the monotonicity of the frequency of the crystal resonator along with control codes is guaranteed, the frequency step size is accurately calibrated, and correct transmission of data between a transmitter and a receiver is guaranteed.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:

FIG. 1 is a schematic diagram of a frequency adjustment circuit shown in accordance with an exemplary embodiment;

FIG. 2 is a schematic diagram illustrating a related art frequency adjustment circuit in accordance with an exemplary embodiment;

FIG. 3 is a schematic diagram illustrating a programmable capacitor array in a frequency adjustment circuit in accordance with an exemplary embodiment;

FIG. 4 is a schematic diagram illustrating a segmented thermometer code fine tuning capacitor array in a frequency adjustment circuit in accordance with an exemplary embodiment;

FIG. 5 is a schematic diagram illustrating a segmented binary coarse tuning capacitor array in a frequency tuning circuit according to an exemplary embodiment;

FIG. 6 is a graph illustrating simulated effects from a frequency adjustment circuit according to an exemplary embodiment;

FIG. 7 is a flow chart illustrating a method of frequency adjustment according to an example embodiment;

fig. 8 is a block diagram illustrating a communication device according to an example embodiment.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure.

It should be noted that in the present disclosure, the terms "S101", "S102" and the like in the description and claims and the drawings are used for distinguishing the steps, and are not necessarily to be construed as performing the method steps in a specific order or sequence.

The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.

As background art, in the related art, the load capacitance of a crystal resonator (hereinafter referred to as a crystal oscillator) is adjusted by binary coding to fine-tune the load resonant frequency of the crystal oscillator in a transmitter and a receiver, so that the frequencies of the transmitter and the receiver are consistent to perform data transmission, or a square wave with a standard frequency is input through IO, the deviation between the frequency of the crystal oscillator and the standard frequency is calculated by using a digital algorithm, and the load capacitance of the crystal resonator is adjusted to fine-tune the load resonant frequency of the crystal oscillator.

Wherein, when the load capacitance of the crystal oscillator is adjusted through binary coding, the load capacitance C is finely adjusted_LResulting in a load resonant frequency F_LThe frequency change of (a) can be expressed by the pulling sensitivity, and the specific calculation formula is as follows:

however, when the binary code is the minimum, the crystal oscillator frequency pulling sensitivity is the maximum, but as the binary code increases, the more capacitors selected in the capacitor array, the smaller the crystal oscillator frequency pulling sensitivity, and referring to fig. 2, the capacitor array includes: one end of the switch S0 is grounded, the other end is connected with the lower end of a capacitor C, and the upper end of the capacitor C is connected with a crystal oscillator output pin XOUT (hereinafter referred to as XOUT); one end of the switch S1 is grounded, the other end is connected with the lower end of the capacitor 2C, and the upper end of the capacitor 2C is connected with XOUT; one end of the switch S2 is grounded, the other end is connected with the lower end of the capacitor 4C, and the upper end of the capacitor 4C is connected with XOUT; one end of the switch S3 is grounded, the other end is connected with the lower end of the capacitor 8C, and the upper end of the capacitor 8C is connected with XOUT; one end of the switch S4 is grounded, one end of the switch is connected with the lower end of the capacitor 16C, and the upper end of the capacitor 16C is connected with XOUT; one end of the switch S5 is grounded, the other end is connected with the lower end of the capacitor 32C, and the upper end of the capacitor 32C is connected with XOUT; one end of the switch S6 is grounded, the other end is connected with the lower end of the capacitor 64C, and the upper end of the capacitor 64C is connected with XOUT; one end of the switch S7 is grounded, the other end is connected with the lower end of the capacitor 128C, and the upper end of the capacitor 128C is connected with XOUT; one end of the switch S8 is grounded, the other end is connected to the lower end of the capacitor 256C, and the upper end of the capacitor 256C is connected to XOUT.

With the minimum binary code, switch S0 in the capacitor array is closed, capacitor C is selected, with the closing of the plurality of switches in the capacitor array connected to the crystal output pin XOUT, the more capacitors in the capacitor column are selected, if as the binary code increases, the switches S0, S1, S2 are closed, the capacitors C, 2C, 4C are selected, the switches S0, · S5 are closed, the capacitors C,. cndot.. 32C are selected, the switches S0,. cndot.. S7 are closed, the capacitors C,. cndot.. 128C are selected, and each additional binary code will make the adjustable crystal frequency step inconsistent, which will result in that only smaller unit capacitance can be used when fine control frequency is needed, so that the frequency adjustable range is limited, and the frequencies of crystal oscillators of the transmitter and the receiver are different, which results in data transmission errors between the transmitter and the receiver.

When the load resonant frequency of the crystal oscillator is finely adjusted by adjusting the load capacitance of the crystal oscillator through the square wave of the standard frequency, the reduction of the load capacitance can cause the increase of the frequency, otherwise, the increase of the load capacitance can cause the reduction of the frequency, and the square wave of the standard frequency has a frequency deviation of (-2 ppm-2 ppm), so that the frequency modulation is difficult to be performed according to the standard frequency, and the accurate frequency calibration is realized, so that the sampling frequency deviation still exists between the transmitter and the receiver, and the data transmission error between the transmitter and the receiver is caused.

In view of the above, the present disclosure provides a frequency adjustment circuit, a method and a communication device, which perform piecewise linear fitting by encoding a programmable capacitor array, linearize the pulling sensitivity of a crystal resonator, perform multiple adjustments on the frequency of the crystal resonator, ensure that the frequency of the crystal resonator is monotonous along with control encoding, implement accurate calibration of a frequency step, and ensure correct transmission of data between a transmitter and a receiver.

Fig. 1 is a schematic diagram of a frequency adjustment circuit according to an exemplary embodiment, and referring to fig. 1, the circuit includes a crystal resonator 100, a start-up circuit 200, and a programmable capacitor array, the crystal resonator 100 is connected in parallel with the start-up circuit 200, and the programmable capacitor array is connected to the crystal resonator 100;

the programmable capacitor array comprises a plurality of capacitor arrays which are connected in parallel in sequence, each capacitor array can work independently, and the target capacitor array used for coding in each time in the programmable capacitor array is determined according to the value of part of bits in the code to be output.

The code to be output may be determined according to the frequency modulation requirement, which is not specifically limited by the present disclosure.

According to the method, the programmable capacitor array is controlled through coding, the capacitor array in the frequency adjusting circuit needs to be connected, the plurality of capacitor arrays in the programmable capacitor array are used for conducting piecewise fitting straight line, the traction sensitivity of the crystal resonator is linearized, the frequency adjustable range of the crystal resonator is expanded, the frequency of the crystal resonator of the transmitter and the frequency of the crystal resonator of the receiver are adjusted to be consistent, and correct transmission of data between the transmitter and the receiver is guaranteed.

Referring to fig. 1, the crystal resonator XTAL100 includes a dynamic equivalent sub-circuit and a static equivalent capacitor C0, and the dynamic equivalent sub-circuit is connected in parallel with the static equivalent capacitor C0 and then connected between the crystal oscillator input pin XIN and the crystal oscillator output pin XOUT of the crystal resonator.

The dynamic equivalent sub-circuit comprises a dynamic equivalent inductor L1, a dynamic equivalent capacitor C1 and a dynamic equivalent resistor R1, wherein the dynamic equivalent inductor L1, the dynamic equivalent capacitor C1 and the dynamic equivalent resistor R1 are sequentially connected in series, then connected with the static equivalent capacitor C0 in parallel, and then connected between the crystal oscillator input pin XIN and the crystal oscillator output pin XOUT to form the crystal resonator.

The crystal resonator provided by the present disclosure is an existing crystal resonator, and the working principle thereof is not explained herein.

Referring to fig. 1, the oscillation starting circuit includes a feedback resistor Rf and an inverter a0, and the feedback resistor Rf and the inverter a0 are connected in parallel and then connected between the crystal oscillator input pin XIN and the crystal oscillator output pin XOUT.

The oscillation starting circuit provided by the present disclosure is the prior art, and the specific working principle thereof is not explained herein.

In order to make the frequency adjustment circuit provided by the present disclosure more understandable to those skilled in the art, each part of the above-mentioned circuit is exemplified in detail below.

The frequency adjustment circuit may have different numbers of programmable capacitor arrays, for example, a frequency adjustment circuit having only two programmable capacitor arrays, or a frequency adjustment circuit having more than two programmable capacitor arrays, where the specific connection modes of the parts in the frequency adjustment circuit corresponding to the programmable capacitor arrays in different numbers are different.

In a possible embodiment, in the case that the circuit includes two programmable capacitor arrays, one end of the first programmable capacitor array is connected to the crystal oscillator input pin of the crystal resonator 100, and the other end of the first programmable capacitor array is grounded;

one end of the second programmable capacitor array is connected to the crystal oscillator output pin of the crystal resonator 100, and the other end of the second programmable capacitor array is grounded.

As shown in fig. 1, in the case that the circuit includes two programmable capacitor arrays, one end of the first programmable capacitor array 300 is connected to the crystal oscillator input pin XIN, and the other end of the first programmable capacitor array 300 is grounded; one end of the second programmable capacitor array 400 is connected to the crystal oscillator output pin XOUT, and the other end of the second programmable capacitor array 400 is grounded, where the specific configurations of the first programmable capacitor array 300 and the second programmable capacitor array 400 are completely the same.

In a possible embodiment, when the circuit includes more than two programmable capacitor arrays, the programmable capacitor arrays are sequentially connected in series and then connected between the crystal oscillator input pin and the crystal oscillator output pin of the crystal resonator 100.

In one embodiment, the programmable capacitor array comprises a coarse tuning sub-circuit and a fine tuning sub-circuit connected in parallel with the coarse tuning sub-circuit;

the fine tuning sub-circuit comprises a segmented thermometer code decoder 401 and a segmented thermometer code fine tuning capacitor array 402 connected with the segmented thermometer code decoder 401, and the coarse tuning sub-circuit comprises a segmented binary code decoder 403 and a segmented binary code coarse tuning capacitor array 404 connected with the segmented binary code decoder 403;

the fine tuning sub-circuit and the coarse tuning sub-circuit can output independent codes, and each time the target capacitor array used for coding in the segmented thermometer code fine tuning capacitor array 402 and the segmented binary code coarse tuning capacitor array 404 is determined according to the value of part of bits in the codes to be output.

Further, referring to fig. 3, the fine tuning sub-circuit and the coarse tuning sub-circuit are connected through the first interface and the second interface.

The frequency of the crystal resonator is roughly adjusted through a rough adjusting sub-circuit (comprising a segmented binary code decoder and a segmented binary code rough adjusting capacitor array) in a coding control programmable circuit, and is finely adjusted through a fine adjusting sub-circuit (comprising a segmented thermometer code decoder and a segmented thermometer code fine adjusting capacitor array) in the coding control programmable circuit, so that the monotonicity of the frequency of the crystal resonator is controlled along with control coding, the precise calibration of the frequency step is realized, and the correct transmission of data between a transmitter and a receiver is ensured.

In one embodiment, the segmented thermometer code fine tuning capacitor array 402 comprises a plurality of sequentially connected first capacitor sub-circuits, each of which comprises a capacitor and a control switch sequentially connected in series.

Referring to fig. 4, the segmented thermometer code fine tuning capacitor array 402 includes four sequentially parallel first capacitor subcircuits a, B, C and D, the first capacitor subcircuit a including sequentially series connected capacitors CTA < 30: 0> and control switch STA < 30: 0 >; the first capacitive sub-circuit B comprises a capacitor CTB < 30: 0> and control switch STB < 30: 0 >; the first capacitive sub-circuit C comprises a capacitor CTC < 30: 0> and control switch STC < 30: 0 >; the first capacitive sub-circuit D comprises a capacitor CTD < 30: 0> and control switch STD < 30: 0 >.

Taking a 31Bit segmented thermometer code programmable capacitor array as an example, the specific connection form is as follows: control switch STA < 30: 0> one terminal connected to ground, and one terminal connected to a capacitor CTA < 30: lower end of 0>, capacitance CTA < 30: 0> upper terminal XOUT; control switch STB < 30: 0> one end is grounded, and the other end is connected with a capacitor CTB < 30: lower end of 0>, capacitance CTB < 30: 0> upper terminal XOUT; control switch STC < 30: 0> one end connected to ground and one end connected to capacitor CTC < 30: lower end of 0>, capacitance CTC < 30: 0> upper terminal XOUT; control switch STD < 30: 0> one end is grounded, and the other end is connected with a capacitor CTD < 30: lower end of 0>, capacitance CTD < 30: 0> has an upper terminal XOUT.

Referring to fig. 3 and 4, the specific operation of the segmented thermometer code decoder is as follows:

segmented binary decoder (COARSE binary) D _ COARSE < 8: 0> is 00, control switch STA < 30: 0> is encoded by a 5Bit segmented thermometer code decoder (FINE binary) D _ FINE < 4: 0> converted 31Bit thermometer code control, control switch STB < 30: 0>, STC < 30: 0>, STD < 30: 0> are both 0; COARSE binary code D _ COARSE < 8: 0> is 01, the switch STB < 30: 0> FINE-tuning the binary code D _ FINE <4 by 5 Bit: 0> converted 31Bit thermometer code control, control switch STA < 30: 0>, STC < 30: 0>, STD < 30: 0> are both 0; COARSE binary code D _ COARSE < 8: 0> is 10, control switch STC < 30: 0> FINE-tuning the binary code D _ FINE <4 by 5 Bit: 0> converted 31Bit thermometer code control, control switch STA < 30: 0>, STB < 30: 0>, STD < 30: 0> are both 0; COARSE binary code D _ COARSE < 8: 0> is 11, control switch STD < 30: 0> FINE-tuning the binary code D _ FINE <4 by 5 Bit: 0> converted 31Bit thermometer code control, control switch STA < 30: 0>, STB < 30: 0>, STC < 30: 0> are both 0; wherein, the control switch is 1, which means that the capacitor connected in series with the control switch is connected between XOUT and ground, and the control switch is 0, which means that the capacitor connected in series with the control switch is not connected between XOUT and ground.

Taking the fine tuning of the segmented thermometer code converted from 5Bit binary as an example: segmented binary code decoder D _ COARSE < 8: the four states 00, 01, 10, 11 when 0> is high 2Bit divide the 5Bit segmented thermometer code into 4 segments; at 00, in the segmented thermometer code fine tuning capacitor array 402, the control switch STA < 30: 0> FINE-tuning the binary code D _ FINE <4 by 5 Bit: 0> converted 31Bit thermometer code control, connected between XOUT and ground, controlling switch STB < 30: 0>, control switch STC < 30: 0>, control switch STD < 30: 0> is 0, and the fine tuning capacitor arrays connected in series are not accessed; 01, control switch STB < 30: 0> FINE-tuning the binary code D _ FINE <4 by 5 Bit: 0> 31Bit thermometer code control of conversion, insert between XOUT and ground, control switch STA < 30: 0>, control switch STC < 30: 0>, control switch STD < 30: 0> is 0, and the fine tuning capacitor arrays connected in series are not accessed; at 10, control switch STC < 30: 0> FINE-tuning the binary code D _ FINE <4 by 5 Bit: 0> 31Bit thermometer code control of conversion, insert between XOUT and ground, control switch STA < 30: 0>, control switch STB < 30: 0>, control switch STD < 30: 0> is 0, and the fine tuning capacitor arrays connected in series are not accessed; at time 11, control switch STD < 30: 0> FINE-tuning the binary code D _ FINE <4 by 5 Bit: 0> 31Bit thermometer code control of conversion, insert between XOUT and ground, control switch STA < 30: 0>, control switch STB < 30: 0>, control switch STC < 30: 0> is 0, and the fine tuning capacitor arrays connected in series are not connected.

The unit capacitance in the first capacitor sub-circuit a is CTA, the unit capacitance in the first capacitor sub-circuit B is CTB, the unit capacitance in the first capacitor sub-circuit C is CTC, the unit capacitance in the first capacitor sub-circuit D is CTD, CTA < CTB < CTC < CTD, and the unit capacitance is the capacitance of the capacitor array after all capacitors in the capacitor array are connected to the frequency adjusting circuit.

In one embodiment, the segmented binary coarse tuning capacitor array 404 comprises a plurality of capacitor arrays connected in parallel in sequence, and the unit capacitance of each capacitor array increases in sequence.

The unit capacitor is the capacitance of the capacitor array after all the capacitors in the capacitor array are connected to the frequency adjusting circuit.

Referring to fig. 5, the segmented binary code coarse tuning capacitor array 404 includes four capacitor arrays a, B, C and D connected in parallel in sequence, where a unit capacitor of the capacitor array a is CA, a unit capacitor of the capacitor array B is CB, a unit capacitor of the capacitor array C is CB, a unit capacitor of the capacitor array D is CD, and CA < CB < CC < CD.

By arranging the sequentially increased unit capacitors and performing piecewise fitting on straight lines through the capacitor arrays, the traction sensitivity of the crystal oscillator is linearized, and the adjustable range of the frequency of the crystal oscillator is expanded.

In one embodiment, the capacitor array in the segmented binary code coarse tuning capacitor array comprises a plurality of second capacitor sub-circuits connected in parallel in sequence, and each second capacitor sub-circuit comprises a capacitor and a control switch connected in series in sequence.

Referring to fig. 5, the segmented binary code coarse tuning capacitor array 404 includes four capacitor array a, capacitor array B, capacitor array C, and capacitor array D rows connected in parallel in sequence, where the capacitor array a includes: one end of the switch SA is grounded, the other end of the switch SA is connected with the lower end of the capacitor CA, and the upper end of the capacitor CA is connected with XOUT; one end of the switch SA0 is grounded, one end of the switch SA0 is connected with the lower end of the capacitor 1CA, and the upper end of the capacitor 1CA is connected with XOUT; one end of the switch SA1 is grounded, the other end of the switch SA1 is connected with the lower end of the capacitor 2CA, and the upper end of the capacitor 2CA is connected with XOUT; one end of the switch SA2 is grounded, the other end of the switch SA2 is connected with the lower end of the capacitor 4CA, and the upper end of the capacitor 4CA is connected with XOUT; one end of the switch SA3 is grounded, the other end of the switch SA3 is connected with the lower end of the capacitor 8CA, and the upper end of the capacitor 8CA is connected with XOUT; one end of the switch SA4 is grounded, one end of the switch SA4 is connected with the lower end of the capacitor 16CA, and the upper end of the capacitor 16CA is connected with XOUT; one end of the switch SA5 is grounded, the other end of the switch SA5 is connected with the lower end of the capacitor 32CA, and the upper end of the capacitor 32CA is connected with XOUT; one end of the switch SA6 is grounded, the other end of the switch SA6 is connected with the lower end of the capacitor 64CA, and the upper end of the capacitor 64CA is connected with XOUT; the switch SA and the capacitor CA are pseudo switch capacitor units and are used for ensuring monotonicity before and after segmentation;

the capacitor array B includes: one end of the switch SB is grounded, the other end of the switch SB is connected with the lower end of the capacitor CB, and the upper end of the capacitor CB is connected with XOUT; one end of the switch SB0 is grounded, one end of the switch SB0 is connected with the lower end of the capacitor 1CB, and the upper end of the capacitor 1CB is connected with XOUT; one end of the switch SB1 is grounded, the other end is connected with the lower end of the capacitor 2CB, and the upper end of the capacitor 2CB is connected with XOUT; one end of the switch SB2 is grounded, the other end is connected with the lower end of the capacitor 4CB, and the upper end of the capacitor 4CB is connected with XOUT; one end of the switch SB3 is grounded, the other end is connected with the lower end of the capacitor 8CB, and the upper end of the capacitor 8CB is connected with XOUT; one end of the switch SB4 is grounded, one end of the switch SB4 is connected with the lower end of the capacitor 16CB, and the upper end of the capacitor 16CB is connected with XOUT; one end of the switch SB5 is grounded, the other end is connected with the lower end of the capacitor 32CB, and the upper end of the capacitor 32CB is connected with XOUT; one end of the switch SB6 is grounded, the other end is connected with the lower end of the capacitor 64CB, and the upper end of the capacitor 64CB is connected with XOUT;

the capacitor array C includes: one end of the switch SC is grounded, the other end of the switch SC is connected with the lower end of the capacitor CC, and the upper end of the capacitor CC is connected with XOUT; one end of the switch SC0 is grounded, one end of the switch is connected with the lower end of the capacitor 1CC, and the upper end of the capacitor 1CC is connected with XOUT; one end of the switch SC1 is grounded, the other end is connected with the lower end of the capacitor 2CC, and the upper end of the capacitor 2CC is connected with XOUT; one end of the switch SC2 is grounded, the other end is connected with the lower end of the capacitor 4CC, and the upper end of the capacitor 4CC is connected with XOUT; one end of the switch SC3 is grounded, the other end is connected with the lower end of the capacitor 8CC, and the upper end of the capacitor 8CC is connected with XOUT; one end of the switch SC4 is grounded, one end of the switch is connected with the lower end of the capacitor 16CC, and the upper end of the capacitor 16CC is connected with XOUT; one end of the switch SC5 is grounded, the other end is connected with the lower end of the capacitor 32CC, and the upper end of the capacitor 32CC is connected with XOUT; one end of the switch SC6 is grounded, the other end is connected with the lower end of the capacitor 64CC, and the upper end of the capacitor 64CC is connected with XOUT;

the capacitor array D includes: one end of the switch SD is grounded, the other end of the switch SD is connected with the lower end of the capacitor CD, and the upper end of the capacitor CD is connected with XOUT; one end of the switch SD0 is grounded, one end of the switch SD0 is connected with the lower end of the capacitor 1CD, and the upper end of the capacitor 1CD is connected with XOUT; one end of the switch SD1 is grounded, the other end is connected with the lower end of the capacitor 2CD, and the upper end of the capacitor 2CD is connected with XOUT; one end of the switch SD2 is grounded, the other end is connected with the lower end of the capacitor 4CD, and the upper end of the capacitor 4CD is connected with XOUT; one end of the switch SD3 is grounded, the other end is connected with the lower end of the capacitor 8CD, and the upper end of the capacitor 8CD is connected with XOUT; one end of the switch SD4 is grounded, one end of the switch SD4 is connected with the lower end of the capacitor 16CD, and the upper end of the capacitor 16CD is connected with XOUT; one end of the switch SD5 is grounded, the other end is connected with the lower end of the capacitor 32CD, and the upper end of the capacitor 32CD is connected with XOUT; one end of the switch SD6 is grounded, the other end is connected to the lower end of the capacitor 64CD, and the upper end of the capacitor 64CD is connected to XOUT.

In one embodiment, the opening and closing of the control switch is determined according to the values of a part of bits in the code to be output.

The code to be output comprises a binary code and a thermometer code, the on and off of a control switch are controlled through the value of part of bits in the binary code and the thermometer code, and the control switch is 1 and represents a capacitor connected in series with the control switch to a frequency adjusting circuit; the control switch is 0, which means that the capacitor connected in series with the control switch is not connected into the frequency adjusting circuit to control the realization of the capacitor array to realize the piecewise fitting straight line, thereby linearizing the traction sensitivity of the crystal oscillator.

Referring to fig. 3 and 5, the specific operation process of the segmented binary decoder is as follows:

take coarse tuning of a 9Bit binary code as an example: the 9Bit binary code is divided into 4 sections by the four states of 00, 01, 10 and 11 with the height of 2 bits, and the capacitor array A is controlled by the binary code with the height of 7 bits at the time of 00 and is connected between XOUT and the ground; when 01, the capacitor array A and the capacitor array B are connected between XOUT and ground, wherein the capacitor array B is controlled by a low 7Bit binary system, and all capacitors in the capacitor array A are connected between XOUT and ground; when 10 hours, the capacitor array A, the capacitor array B and the capacitor array C are connected between XOUT and ground, wherein the capacitor array C is controlled by a low 7-Bit binary system, and all capacitors in the capacitor array A and the capacitor array B are connected between XOUT and ground; and when 11, the capacitor array A, the capacitor array B, the capacitor array C and the capacitor array D are connected between XOUT and ground, wherein the capacitor array D is controlled by a low 7-Bit binary system, and all capacitors in the capacitor array A, the capacitor array B and the capacitor array C are connected between XOUT and ground. For example, a segmented binary decoder (COARSE binary) D _ COARSE < 8: when the high 2Bit of 0> is 00, in the capacitor array a, the control switches SA =1, the control switches SA6, SA5, SA4, SA3, SA2, SA1, and SA0 are respectively controlled by the low 7Bit binary code, the control switch SA6 is MSB (Most Significant Bit), and the control switch SA0 is LSB (Least Significant Bit); in the capacitor array B, the control switches SB =0, and the control switches SB6, SB5, SB4, SB3, SB2, SB1, and SB0 are all 0; in the capacitor array C, the control switches SC =0, and the control switches SC6, SC5, SC4, SC3, SC2, SC1, and SC0 are all 0; in the capacitor array D, the control switches SD =0, and the control switches SD6, SD5, SD4, SD3, SD2, SD1, and SD0 are all 0.

COARSE binary code D _ COARSE < 8: when the high 2Bit of 0> is 01, in the capacitor array B, the control switch SB =1, the control switches SB6, SB5, SB4, SB3, SB2, SB1, SB0 are controlled by the low 7Bit binary code, SB6 is MSB, and SB0 is LSB; in the capacitor array a, control switches SA =1, control switches SA6, SA5, SA4, SA3, SA2, SA1, and SA0 are all 1; in the capacitor array C, the control switches SC =0, and the control switches SC6, SC5, SC4, SC3, SC2, SC1, and SC0 are all 0; in the capacitor array D, the control switch SD =0, and the switches SD6, SD5, SD4, SD3, SD2, SD1, and SD0 are all 0.

COARSE binary code D _ COARSE < 8: when the high 2Bit of 0> is 10, in the capacitor array C, the control switches SC =1, the control switches SC6, SC5, SC4, SC3, SC2, SC1, and SC0 are controlled by the low 7Bit binary code, SC6 is MSB, and SC0 is LSB, respectively; in the capacitor array a, control switches SA =1, control switches SA6, SA5, SA4, SA3, SA2, SA1, and SA0 are all 1; in the capacitor array B, the control switches SB =1, the control switches SB6, SB5, SB4, SB3, SB2, SB1, and SB0 are all 1; in the capacitor array D, the control switches SD =0, and the control switches SD6, SD5, SD4, SD3, SD2, SD1, and SD0 are all 0.

COARSE binary code D _ COARSE < 8: when the high 2Bit of 0> is 11, in the capacitor array D, the control switches SD =1, the control switches SD6, SD5, SD4, SD3, SD2, SD1, and SD0 are controlled by the low 7Bit binary code, respectively, SD6 is MSB, and SD0 is LSB; in the capacitor array a, control switches SA =1, control switches SA6, SA5, SA4, SA3, SA2, SA1, and SA0 are all 1; in the capacitor array B, the control switches SB =1, the control switches SB6, SB5, SB4, SB3, SB2, SB1, and SB0 are all 1; in the capacitor array C, the control switches SC =1, and the control switches SC6, SC5, SC4, SC3, SC2, SC1, and SC0 are all 1.

Wherein, the control switch is 1, which means that the capacitor connected in series with the control switch is connected between XOUT and ground, and the control switch is 0, which means that the capacitor connected in series with the control switch is not connected between XOUT and ground.

The above logical relationships can be seen in the following truth table:

referring to fig. 6, a dotted line is a simulation result obtained by adjusting the load capacitance of the crystal resonator by using binary coding, and it can be determined that when the binary coding is the minimum, the crystal oscillator frequency pulling sensitivity is the maximum, but as the binary coding increases, the more capacitors selected in the programmable capacitor array increase, the smaller the crystal oscillator frequency pulling sensitivity is, and the adjustable crystal oscillator frequency step length is inconsistent when one binary coding is added; the solid line is a simulation result obtained by adopting the frequency adjusting circuit provided by the disclosure, and the pulling sensitivity of the crystal oscillator can be determined to be linearized by means of piecewise fitting of a straight line.

In addition, the coding mode of the segmented binary code coarse tuning capacitor array and the segmented thermometer code fine tuning capacitor array is adopted, so that the monotonicity of the crystal oscillator frequency along with the binary code control is ensured, and the purpose of finely controlling the adjustable frequency step length is achieved. And the crystal oscillator frequency adjusting circuit can realize the adjustment precision of 0.1 ppm.

Based on the same inventive concept, the present disclosure further provides a frequency adjustment method, executed by the frequency adjustment circuit described above, with reference to fig. 7, the method including:

in step S101, a frequency deviation between the frequency of each crystal resonator to be adjusted at the receiver and the transmitter and a preset standard frequency is obtained, and the frequency of each crystal resonator is factory calibrated according to the frequency deviation.

In step S102, a sampling frequency deviation between the receiver and the crystal resonator at the transmitting end after factory calibration is acquired, and communication calibration is performed on the frequency of each crystal resonator according to the sampling frequency deviation.

The preset standard frequency may be preset according to a frequency in a specific communication process between the transmitter and the receiver, which is not specifically limited in this disclosure.

The frequency adjusting method comprises two steps of factory calibration and communication calibration, wherein in the first step, when a product (such as a chip and the like) comprising a frequency adjusting circuit is in factory, the frequency deviation between a crystal resonator and a preset standard frequency in the product is compared, a segmented binary code coarse tuning capacitor array in the frequency adjusting circuit is adjusted firstly, a segmented thermometer code fine tuning capacitor array in the frequency adjusting circuit is adjusted secondly, and the frequency of the crystal resonator is adjusted to be close to the preset standard frequency; and secondly, acquiring the sampling frequency deviation between a receiver and a transmitting end of the power line communication by using a sampling frequency deviation estimation algorithm, firstly adjusting a segmented binary code coarse tuning capacitor array in a frequency adjusting circuit according to the sampling frequency deviation, and then adjusting a segmented thermometer code fine tuning capacitor array in the frequency adjusting circuit so as to solve the technical problem of data packet receiving errors caused by the sampling frequency deviation between a transmitter and the receiver in the conventional power line communication.

With regard to the frequency adjustment circuit in the above-mentioned embodiment, the connection relationship of the components and the specific operation principle have been described in detail in the embodiment of the frequency adjustment circuit, and will not be described in detail here.

Based on the same inventive concept, the present disclosure also provides a communication device comprising the above frequency adjustment circuit.

Fig. 8 is a block diagram illustrating an electronic device 700 in accordance with an example embodiment. As shown in fig. 8, the electronic device 700 may include: a processor 701 and a memory 702. The electronic device 700 may also include one or more of a multimedia component 703, an input/output (I/O) interface 704, and a communication component 705.

The processor 701 is configured to control the overall operation of the electronic device 700, so as to control the frequency adjustment circuit to perform frequency adjustment. The memory 702 is used to store various types of data to support operation at the electronic device 700, such as instructions for any application or method operating on the electronic device 700 and application-related data, such as contact data, transmitted and received messages, pictures, audio, video, and the like. The Memory 702 may be implemented by any type of volatile or non-volatile Memory device or combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic Memory, flash Memory, magnetic disk, or optical disk. The multimedia components 703 may include screen and audio components. Wherein the screen may be, for example, a touch screen and the audio component is used for outputting and/or inputting audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signal may further be stored in the memory 702 or transmitted through the communication component 705. The audio assembly also includes at least one speaker for outputting audio signals. The I/O interface 704 provides an interface between the processor 701 and other interface modules, such as a keyboard, mouse, buttons, etc. These buttons may be virtual buttons or physical buttons. The communication component 705 is used for wired or wireless communication between the electronic device 700 and other devices. Wireless Communication, such as Wi-Fi, bluetooth, Near Field Communication (NFC), 2G, 3G, 4G, NB-IOT, eMTC, or other 5G, etc., or a combination of one or more of them, which is not limited herein. The corresponding communication component 705 may thus include: Wi-Fi module, Bluetooth module, NFC module, etc.

In an exemplary embodiment, the electronic Device 700 may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components, for controlling the frequency adjusting circuits to perform frequency modulation.

In another exemplary embodiment, a computer readable storage medium comprising program instructions that when executed by a processor control the frequency adjustment circuit to frequency modulate is also provided. For example, the computer readable storage medium may be the memory 702 comprising program instructions executable by the processor 701 of the electronic device 700 to control the frequency adjustment circuit to perform frequency adjustment.

The preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.

It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, various possible combinations will not be separately described in this disclosure.

In addition, any combination of various embodiments of the present disclosure may be made, and the same should be considered as the disclosure of the present disclosure, as long as it does not depart from the spirit of the present disclosure.

Claims

1. A frequency adjustment circuit is characterized in that the circuit comprises a crystal resonator, a starting oscillation circuit and a programmable capacitor array, wherein the crystal resonator is connected with the starting oscillation circuit in parallel, and the programmable capacitor array is connected with the crystal resonator;

the programmable capacitor array comprises a plurality of capacitor arrays which are connected in parallel in sequence, each capacitor array can work independently, and a target capacitor array used for coding in each time in the programmable capacitor array is determined according to values of part of bits in a preset code to be output.

2. The circuit of claim 1, wherein in the case where the circuit includes two programmable capacitor arrays, one end of a first programmable capacitor array is connected to a crystal oscillator input pin of the crystal resonator, and the other end of the first programmable capacitor array is grounded;

3. The circuit according to claim 1, wherein when the circuit comprises more than two programmable capacitor arrays, each programmable capacitor array is connected in series in sequence and then is connected between a crystal oscillator input pin and a crystal oscillator output pin of the crystal resonator.

4. A circuit according to any of claims 1-3, wherein the programmable capacitor array comprises a coarse tuning sub-circuit and a fine tuning sub-circuit connected in parallel with the coarse tuning sub-circuit;

5. The circuit of claim 4, wherein the segmented thermometer code fine tuning capacitor array comprises a plurality of sequentially parallel first capacitor sub-circuits, each of the first capacitor sub-circuits comprising a capacitor and a control switch sequentially connected in series.

6. The circuit of claim 4, wherein the segmented binary coarse tuning capacitor array comprises a plurality of capacitor arrays connected in parallel in sequence, and the unit capacitance of each capacitor array increases in sequence.

7. The circuit of claim 6, wherein the capacitor array of the segmented binary coarse tuning capacitor array comprises a plurality of second capacitor sub-circuits connected in parallel in sequence, each of the second capacitor sub-circuits comprising a capacitor and a control switch connected in series in sequence.

8. The circuit of claim 7, wherein the opening and closing of the control switch is determined according to the value of a part of bits in the code to be output.

9. A method of frequency adjustment, performed by the frequency adjustment circuit of any one of claims 1-8, the method comprising:

10. A communication device comprising the frequency adjustment circuit of any one of claims 1-8.