CN113745311B - High-voltage semiconductor device with buried layer structure - Google Patents

High-voltage semiconductor device with buried layer structure Download PDF

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CN113745311B
CN113745311B CN202110409628.7A CN202110409628A CN113745311B CN 113745311 B CN113745311 B CN 113745311B CN 202110409628 A CN202110409628 A CN 202110409628A CN 113745311 B CN113745311 B CN 113745311B
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buried layer
high voltage
buried
semiconductor device
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CN113745311A (en
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莫尼卡·巴提
韦维克
陈柏安
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Nuvoton Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A high voltage semiconductor device having a buried layer structure includes a semiconductor substrate, a deep well, first and second well regions, a gate, first and second top doped regions, and a buried layer structure. The semiconductor substrate, the first and second well regions, and the first and second top doped regions have a first conductive morphology. The deep well is located on the semiconductor substrate, and the first and second well regions extend downward from a top surface of the deep well. The grid electrode is positioned on the top surface of the deep well. The first and second top doped regions are located in the first and second well regions, respectively. The buried layer structure has a second conductive form and is positioned at the surface of the deep well and the semiconductor substrate. The buried layer structure comprises a first buried layer, is a continuous buried layer and is arranged corresponding to the first well region, and the first buried layer continuously extends from the high-voltage region to the potential conversion region; and the second buried layer corresponds to the second well region, and the second buried layer comprises a plurality of buried parts which are arranged at intervals.

Description

High-voltage semiconductor device with buried layer structure
Technical Field
The present invention relates to a high voltage semiconductor device, and more particularly, to a high voltage semiconductor device with buried layer structure.
Background
The high voltage semiconductor device technology is suitable for the field of high voltage and high power High Voltage Integrated Circuits (HVICs). Conventional high voltage semiconductor devices may be, for example, vertical diffused metal oxide semiconductor (vertically diffused metal oxide semiconductor, VDMOS) transistors and lateral diffused metal oxide semiconductor (laterally diffused metal oxide semiconductor, LDMOS) transistors. The advantage of high voltage device technology is that it is cost effective and compatible with other manufacturing processes, and has been widely used in the fields of display driver IC components, power supplies, power management, communications, automotive electronics, or industrial control, such as high voltage integrated circuits using 220V ac to drive Light Emitting Diode (LED) illumination.
The high-voltage semiconductor device includes not only a high-voltage unit and a low-voltage unit, but also a potential conversion unit (level shifting unit) located therebetween. The potential conversion unit can step down the signal from the high voltage unit and then provide the signal to the low voltage unit, and can also step up the signal from the low voltage unit and then provide the signal to the high voltage unit. The high voltage semiconductor device needs to have a breakdown voltage high enough to operate at a high voltage, and typically the operating voltage of the high voltage semiconductor device is about 600V, for example. Furthermore, in the conventional high voltage semiconductor device, a potential conversion unit (e.g., 600V LDMOS) does not transmit a signal from the low voltage unit to the high voltage unit or transmits a signal from the high voltage unit to the low voltage unit, wherein a leakage current is generated between the source of the potential conversion unit and the high voltage unit. However, the conventional high voltage semiconductor device generally has the problem that the substrate leakage current (substrate leakage current) increases with the increase of the breakdown voltage (breakdown voltage), and the problem that the manufacturing process window is too narrow.
Thus, while existing high voltage semiconductor devices can cope with their originally intended use, they still have problems in their construction that need to be overcome. How to improve the high-voltage semiconductor device to avoid the above problems, and other electrical properties of the improved high-voltage semiconductor device are not affected, is an important issue for related industries.
Disclosure of Invention
Some embodiments of the present invention disclose a high voltage semiconductor device including a semiconductor substrate, a deep well (deep well), a first well (first well) and a second well (second well), a gate, a first top doped region (first top doping region) and a second top doped region (second top doping region), and a buried layer structure. Wherein the semiconductor substrate has a first conductive morphology; the deep well is positioned on the semiconductor substrate and has a second conductive form different from the first conductive form; the first well region and the second well region extend downwards from the top surface of the deep well, wherein the first well region and the second well region have a first conductive mode; the grid electrode is positioned on the top surface of the deep well, and the first well region and the second well region are respectively overlapped with the bottom surface of the grid electrode partially; the first top doped region and the second top doped region are respectively located in the first well region and the second well region, and the first top doped region and the second top doped region have a first conductive form. In some embodiments, a buried layer structure is located at a surface of a semiconductor substrate and a deep well, and includes a first buried layer (first buried layer) and a second buried layer (second buried layer).
In some embodiments, the first buried layer has a second conductive state and is a continuous buried layer and is disposed corresponding to the first well region. In some embodiments, the first buried layer extends continuously from a high voltage region of the high voltage semiconductor device to a potential transition region.
In some embodiments, the second buried layer has a second conductive morphology and includes a plurality of buried portions (buried portions) disposed apart from each other, and the buried portions correspond to the second well region. In some embodiments, the second buried layer is located in the potential transition region.
According to some embodiments of the invention, the second well region has a first sidewall and a second sidewall opposite to the first sidewall, and the first sidewall is closer to the first well region, wherein a side edge of the first buried layer adjacent to the second buried layer is located under the first sidewall of the second well region.
According to some embodiments of the invention, a side edge of the first buried layer adjacent to the second buried layer exceeds under a first sidewall of the second well region, but does not exceed under a sidewall of the gate.
According to some embodiments of the invention, the second top doped region has a third sidewall and a fourth sidewall opposite the third sidewall, and the third sidewall is closer to the first well region, and a buried portion of the second buried layer farthest from the first buried layer does not exceed an underside of the third sidewall.
In some embodiments, the first conductive pattern is, for example, P-type, and the second conductive pattern is, for example, N-type.
Drawings
FIGS. 1A-1E are schematic cross-sectional views illustrating various intermediate stages in the formation of a high voltage semiconductor device according to some embodiments of the present invention;
FIG. 2 is a schematic cross-sectional view of a conventional high-voltage semiconductor device according to the control group 1 in a simulation experiment;
FIG. 3 is a schematic cross-sectional view of a high voltage semiconductor device according to control group 2 in a simulation experiment;
FIG. 4 is a schematic cross-sectional view of a high voltage semiconductor device according to control group 3 in a simulation experiment;
FIG. 5 is a graph showing the breakdown voltages of three control groups and one embodiment of a high voltage semiconductor device at different drift region implant doses in a simulation experiment;
fig. 6A shows the implantation dose of 7.5x10 in the P-type drift region of the high voltage semiconductor device of the control group 1 (i.e. the conventional buried layer structure with only the first buried layer) in the simulation experiment 12 Atoms/cm 2 A characteristic curve of a source current (expressed as logarithm) versus a source voltage;
fig. 6B is a simulation experiment showing an implant dose of 7.5x10 in a P-type drift region for a high voltage semiconductor device according to some embodiments of the present invention 12 Atoms/cm 2 A characteristic curve of a source current (expressed as logarithm) versus a source voltage;
fig. 7 is a graph showing a source current (expressed as logarithm) versus a source voltage for a high voltage semiconductor device according to some embodiments of the invention at different P-drift region implant doses in a simulation experiment.
Symbol description
100 semiconductor substrate
101a surface of semiconductor substrate
110 first buried layer
110-S1 side edge
120 a second buried layer
121. 122, 123, 124, 125: buried portion
125-S side wall
131. 132 deep well
131a top surface of deep well
141 first well region
142 second well region
143 third well region
142-S1 first side wall
142-S2 second sidewall
151 first top doped region
152 second top doped region
152-S3 third side wall
152-S4 fourth sidewall
153 third top doped region
154 fourth top doped region
161 first field oxide part
162 second field oxide part
163 third field oxide portion
164 fourth field oxide portion
165 fifth field oxide
166 sixth field oxide portion
170 grid electrode
170-S side wall of gate
180 dielectric layer
A HV High pressure region
A L Potential transition region
W1, W2, W3, W4, W5: width
d1, d2, d3, d4 spacing
S distance
H1 first height
H2 second height
D1 first direction
D2, second direction
L S1 、L G1 、L S3 Vertical extension line
190 conductive part
191V first guide hole
192V second guide hole
193V third guide hole
194V fourth guide hole
191M, 192M, 194M wires
Detailed Description
The high voltage semiconductor device and the method of manufacturing the same according to the present invention are described in detail below. It is to be understood that the following description provides various embodiments, or examples, for implementing different aspects of the invention. The specific elements and arrangements described below are only a brief description of the present invention. These are, of course, merely examples and are not intended to limit the scope of the invention. Furthermore, references to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Some variations of the embodiments are described below. In the various drawings and illustrative embodiments, like reference numerals are used to designate like elements. It will be appreciated that additional operations may be provided before, during, and after the method, and that some of the recited operations may be replaced or deleted for other embodiments of the method.
Moreover, relative terms such as "lower," "below" or "bottom" and "upper," "above" or "top" may be used in embodiments to describe the relative relationship of one element to another element as illustrated. It will be appreciated that if the device is turned upside down, elements described as being on the "lower" side would then be elements on the "upper" side.
The terms "about" and "approximately" herein generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The numbers given herein are about numbers, meaning that "about" may still be implied without specific recitation.
Embodiments of high voltage semiconductor devices are disclosed and may be included in integrated circuits (integrated circuit, ICs) such as microprocessors, memory elements, and/or other elements. The integrated circuits may also include various passive and active microelectronic elements such as thin film resistors (thin film resistors), other types of capacitors such as Metal-insulator-Metal capacitor (MIMCAP), inductors, diodes, metal-Oxide-semiconductor field effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (bipolar junction transistors, BJTs), laterally diffused MOS transistors, high power MOS transistors, or other types of transistors. Those skilled in the art will appreciate that high voltage semiconductor devices may also be used to include other types of semiconductor elements in integrated circuits.
The high-voltage semiconductor device of some embodiments of the present invention proposes a buried layer structure design to effectively improve breakdown voltage without increasing or even reducing substrate leakage current. Wherein the buried layer structure has a conductivity type opposite to that of the semiconductor substrate and the drift region. Furthermore, the high voltage semiconductor device according to some embodiments of the present invention can improve the manufacturing process window, so that the range of the manufacturing process conditions is enlarged. Therefore, the high-voltage semiconductor device according to some embodiments of the present invention can have both the advantages of high breakdown voltage and enlarged manufacturing process window, and also has no problem that the leakage current of the substrate increases when the breakdown voltage is increased in the conventional high-voltage semiconductor device. Accordingly, some embodiments of the present invention are well suited for use in fabricating high voltage semiconductor devices that operate at high voltages (operating voltages typically about 600V). Therefore, when the high voltage semiconductor device according to some embodiments of the present invention is applied to a potential conversion unit of a high voltage integrated circuit, the electrical performance of the high voltage semiconductor device can be effectively improved. In addition, the high-voltage semiconductor device and the manufacturing method thereof provided by the embodiment only need to properly adjust the mask pattern in the steps of the existing manufacturing process, and the high-voltage semiconductor device is compatible with the existing manufacturing process and does not need to add an additional mask.
Referring to fig. 1A-1E, cross-sectional views of various intermediate stages in the formation of a high voltage semiconductor device according to some embodiments of the present invention are shown, in accordance with some embodiments of the present invention.
According to some embodiments, as shown in fig. 1A, a semiconductor substrate 100 is provided, and a corresponding plurality of buried layers are formed within the semiconductor substrate 100. The semiconductor substrate 100 may be an elemental semiconductor substrate including silicon (silicon), germanium (germanium); or a compound semiconductor substrate including silicon carbide (silicon carbide), gallium arsenide (gallium arsenide), gallium phosphide (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide) and/or indium antimonide (indium antimonide); or an alloy semiconductor substrate including silicon germanium alloy (SiGe), gallium arsenide phosphide alloy (GaAsP), aluminum indium arsenide alloy (AlInAs), aluminum gallium arsenide alloy (AlGaAs), indium gallium arsenide alloy (GaInAs), indium gallium phosphide alloy (GaInP) and/or indium gallium arsenide phosphide alloy (GaInAsP) or combinations thereof.
The semiconductor substrate 100 may be a semiconductor-on-insulator (semiconductor on insulator, SOI) substrate. In some embodiments, the semiconductor substrate 100 may be a lightly doped P-type or N-type substrate. In this embodiment, the semiconductor substrate 100 is P-type and has a P-type dopant therein, such as boron (B).
According to some embodiments, as shown in fig. 1A, a first buried layer 110 and a second buried layer 120 are formed within a semiconductor substrate 100. In this embodiment, the semiconductor substrate 100 has a first conductive form, for example, P-type, and the first buried layer 110 and the second buried layer 120 have a conductive form (hereinafter referred to as a second conductive form) opposite to the semiconductor substrate 100, for example, N-type.
In some embodiments, an ion implantation process may be performed within the semiconductor substrate 100 using a mask having a pattern corresponding to the first buried layer 110 and the second buried layer 120 to implant an N-type dopant (e.g., phosphorus (P) or arsenic (As)) or a P-type dopant (e.g., boron (B)) to form the buried layer As shown in fig. 1A. In some embodiments, the dopant concentration of the buried layer is about 1x10 17 Atom/cubic centimeter (atoms/cm) 3 ) Up to about 5x10 18 Atom/cubic centimeter (atoms/cm) 3 ) Within a range of (2). Then, the implanted ions are driven into (drive-in) the semiconductor substrate 100 to form the first buried layer 110 and the second buried layer 120.
In some embodiments, the first buried layer 110 is a continuous buried layer and is formed from a high voltage region a of the high voltage semiconductor device HV Continuously extends to a potential conversion area A L . In some embodiments, the second buried layer 120 includes a plurality of buried portions (buried portions) disposed at a distance from each other in the potential conversion area A L . In some embodiments, the first buried layer 110 and the second buried layer 120 may be formed in the same manufacturing process.
Next, referring to fig. 1B, an epitaxial layer is formed on the semiconductor substrate 100, and a corresponding plurality of high-voltage well regions are formed within the epitaxial layer. FIG. 1B shows only the well region of interest, e.g., a high voltage region A of the high voltage semiconductor device HV Is adjacent to the high voltage region A HV Potential conversion region A of (2) L And the epitaxial layers outside these wells are not shown. In some embodiments, the epitaxial layer may be N-type or P-type.
As shown in fig. 1B, a corresponding plurality of high-voltage well regions are formed at the epitaxial layer on the semiconductor substrate 100. In some embodiments, deep wells (deep wells) 131 and 132 are formed in the epitaxial layer, wherein the deep well 131 on the semiconductor substrate 100 has a second conductive form identical to the conductive forms of the first buried layer 110 and the second buried layer 120, for example, an N-type deep well (DNW). Furthermore, in some embodiments, the deep well 131 is formed from the high voltage region a of the high voltage semiconductor device HV Continuously extending to the potential conversion area A L . In some embodiments, another deep well 132 adjacent to the deep well 131 has a first conductive pattern, such as a P-type, also referred to as a high voltage P-type deep well (HVPW).
In some embodiments, the doping concentration of the dopants of deep wells 131 and 132 is, for example, about 1x10 16 Atom/cubic centimeter (atoms/cm) 3 ) Up to about 1x10 18 Atom/cubic centimeter (atoms/cm) 3 ) Within a range of (2). In some embodiments, the doping concentration of the first buried layer 110 and the second buried layer 120 is greater than the doping concentration of the deep wells 131 and 132.
In some embodiments, ions previously implanted into the first buried layer 110 and the second buried layer 120 may diffuse into the epitaxial layer, since the epitaxial layer is formed at a high temperature. As shown in fig. 1B, the first buried layer 110 and the second buried layer 120 are located near the surfaces of the semiconductor substrate 100 and the corresponding well region, and have a portion within the semiconductor substrate 100 and another portion within the corresponding well region, respectively. Accordingly, the first buried layer 110 and the second buried layer 120 distributed in the first direction D1 (e.g., X direction) have heights (in the second direction D2 (e.g., Y direction)) that span the surface 101a of the semiconductor substrate 100.
In some embodiments, the second buried layer 120 includes a plurality of buried portions disposed apart from each other, such as the buried portions 121, 122, 123, 124, 125 shown in fig. 1B, which have widths W1, W2, W3, W4, W5, respectively, in the first direction D1 (e.g., X direction). Further, adjacent embedded portions have pitches (spacing) D1, D2, D3, and D4 in the first direction D1 (for example, the X direction), respectively. And a first buried portion 121 closest to the first buried layer 110 among the buried portions is spaced apart from the first buried layer 110 in a first direction D1 (for example, X direction) by a distance S.
In some embodiments, buried portions (e.g., 121, 122, 123, 124, 125) of the second buried layer 120 each have a width in a range between about 1 μm and about 3.5 μm. In some embodiments, the buried layers of the second buried layer 120 each have a width in a range between about 1.5 μm and about 3.0 μm. In some embodiments, the buried portions of the second buried layer 120 each have a width of between about 2 μm. The width of the embedded portion of the present invention is not limited to the numerical ranges set forth above.
In some embodiments, adjacent embedded portions (e.g., 121, 122, 123, 124, 125) each have a spacing therebetween in a first direction D1 (e.g., X-direction) in a range of between about 1 μm and about 3.5 μm. In some embodiments, adjacent buried regions each have a spacing in the range of about 1.5 μm to about 3.0 μm. In some embodiments, adjacent embedded portions each have a spacing of between about 2 μm. The spacing between adjacent embedded portions of the present invention is not limited to the numerical ranges set forth above.
In some embodiments, all buried portions (e.g., buried portions 121, 122, 123, 124, 125) of the second buried layer 120 are equally spaced apart at the deep well 131 and the surface 101a of the semiconductor substrate 100, i.e., d1=d2=d3=d4. Furthermore, in some embodiments, the distance S between the first buried portion 121 of the second buried layer 120 and the first buried layer 110 in the first direction D1 (e.g., X direction) is also equal to the spacing between adjacent buried portions, that is, d1=d2=d3=d4=s.
In some embodiments, all buried portions (e.g., buried portions 121, 122, 123, 124, 125) of second buried layer 120 have the same width in first direction D1 (e.g., X-direction), i.e., w1=w2=w3=w4=w5.
In addition, in some embodiments, the width of the embedded portions is also equal to the spacing between adjacent embedded portions, i.e., d1=d2=d3=d4=w1=w2=w3=w4=w5.
Furthermore, in some embodiments, the first buried layer has a first height H1 in the second direction D2 (e.g., Y direction), and the plurality of buried portions (e.g., 121, 122, 123, 124, 125) of the second buried layer 120 have the same second height H2 in the second direction D2 (e.g., Y direction), respectively.
In some embodiments, the first height H1 of the first buried layer 110 in the second direction D2 is, for example, in a range between about 0.5 μm and about 3.0 μm, or in a range between about 1.0 μm and about 2.0 μm, or in a range between about 1.0 μm and about 1.5 μm. The height (first height H1) of the first buried layer 110 of the present invention is not limited to the above-mentioned numerical range.
In some embodiments, the second height H2 of the plurality of buried portions (e.g., 121, 122, 123, 124, 125) of the second buried layer 120 in the second direction D2 is, for example, in a range between about 0.5 μm and about 3.0 μm, or in a range between about 1.0 μm and about 2.0 μm, or in a range between about 1.0 μm and about 1.5 μm. The height of the plurality of buried portions (second height H2) of the second buried layer 120 of the present invention is not limited to the above-mentioned numerical range.
In some embodiments, the first height H1 of the first buried layer 110 is equal to the second height H2 of the second buried layer 120. And the first buried layer 110 and the second buried layer 120 of equal height may be formed using the same manufacturing process.
In addition to avoiding the problem of bottom leakage current (bottom leakage issue), the buried layer structure of the embodiment may further effectively improve breakdown voltage without increasing or even reducing substrate leakage current by designing the first buried layer 110 and the second buried layer 120 (as described in detail below), and improve the manufacturing process window, so that the operation range is enlarged.
Then, corresponding well regions are formed in the high-pressure well regions (e.g., deep wells 131 and 132).
Referring to fig. 1C, in some embodiments, a first well region (first well) 141 and a second well region (second well) 142 are formed in the deep well 131. The first well region 141 and the second well region 142 are spaced apart from each other by a distance and extend downward from the top surface 131a of the deep well 131, respectively, and the first well region 141 and the second well region 142 have a first conductive pattern (a conductive pattern opposite to the first buried layer 110 and the second buried layer 120), for example, a P-type pattern.
In some embodiments, the first and second wells 141, 142 are implanted at a dose of, for example, about 3.0x10 12 Atoms/cm 2 To about 5.0x10 13 Atoms/cm 2 Within a range of (2).
Furthermore, in some embodiments, the doping concentration of the dopants in the first and second wells 141 and 142 is, for example, about 1×10 16 Atom/cubic centimeter (atoms/cm) 3 ) Up to about 1x10 18 Atom/cubic centimeter (atoms/cm) 3 ) Within a range of (2). It is noted that the doping concentration of the first buried layer 110 and the second buried layer 120 is greater than the doping concentration of the first well region 141 and the second well region 142.
According to the buried structure of some embodiments, the first buried layer 110 is a continuous buried layer and is disposed corresponding to the first well region 141, and the first buried layer 110 is formed from a high voltage region a of the high voltage semiconductor device HV Continuously extends to a potential conversion area A L . In some embodiments, a plurality of buried portions 121, 122, 123, 124, 125 of the second buried layer 120 are disposed apart from each other, and the buried portions correspond to the second well region 142.
Specifically, as shown in FIG. 1C, in this example, the vertical projection of the first well region 141 at the semiconductor substrate 100 is within the vertical projection of the first buried layer 110 at the semiconductor substrate 100, and the vertical projection of the buried portions 121, 122, 123, 124, 125 of the second buried layer 120 at the semiconductor substrate 100 is within the vertical projection of the second well region 142 at the semiconductor substrate 100.
Also, in some embodiments, e.g. As shown in FIG. 1C, the second well region 142 has a first sidewall 142-S1 and a second sidewall 142-S2 opposite the first sidewall 142-S1, and the first sidewall 142-S1 is closer to the first well region 141, wherein a side edge 110-S1 of the first buried layer 110 adjacent to the second buried layer 120 (e.g., the buried portion 121) is located under the first sidewall 142-S1 of the second well region 142. In some examples, a vertical extension L of the first sidewall 142-S1 of the second well 142 is shown in FIG. 1C S1 The side edges 110-S1 of the first buried layer 110 may, for example, contact or exceed the vertical extension L (along the second direction D2) S1 。
Furthermore, in some embodiments, in addition to the first well 141 and the second well 142 (located in the potential conversion region A L In) a third well 143 can be further formed in the high voltage region a HV Is a kind of medium. The third well 143 and the first well 141 are spaced apart from each other by a distance and extend downward from the top surface 131a of the deep well 131, respectively, and the third well 143 has a second conductive pattern, such as N-type. The extension depth of the third well region 143 and the first well region 141 may be the same or different. In this example, the extension depth of the third well region 143 is greater than the extension depth of the first well region 141. The third well region 143 may be formed after the first well region 141 and the second well region 142 are formed, or before they are formed, which is not limited in this regard.
Next, referring to fig. 1C again, a first top doped region (first top doping region) 151 and a second top doped region (second top doping region) 152 are formed in the first well region 141 and the second well region 142, wherein the first top doped region 151 and the second top doped region 152 respectively extend downward from the top surface 131a of the deep well 131 and have a first conductive shape, such as P-type.
In some embodiments, the doping concentration of the first top doped region 151 and the second top doped region 152 is equal to or greater than the doping concentration of the first well region 141 and the second well region 142. In some embodiments, the doping concentration of the first top doped region 151 and the second top doped region 152 is about 1x10 19 Atom/cubic centimeter (atoms/cm) 3 ) Up to about 5x10 20 Atom/cubic centimeter (atoms/cm) 3 ) Within a range of (2). For example, the doping concentration of the first top doping region 151 and the second top doping region 152 may be about 1×10 19 Atom/cubic centimeter (atoms/cm) 3 ) Up to about 1x10 20 Atom/cubic centimeter (atoms/cm) 3 ) Within a range of, or about 1x10 20 Atom/cubic centimeter (atoms/cm) 3 ) Up to about 5x10 20 Atom/cubic centimeter (atoms/cm) 3 ) Within (2) or other suitable range. Furthermore, in this example, the doping concentration of the first top doped region 151 is substantially equal to the doping concentration of the second top doped region 152.
Furthermore, in some embodiments, the vertical projection of the first top doped region 151 on the semiconductor substrate 100 is located within the vertical projection of the first buried layer 110 on the semiconductor substrate 100. In some embodiments, the vertical projection of second top doped region 152 at semiconductor substrate 100 does not overlap with the vertical projection of all buried portions (e.g., buried portions 121, 122, 123, 124, 125) of second buried layer 120 at semiconductor substrate 100, as shown in fig. 1C. Alternatively, in some other embodiments, the vertical projection of the second top doped region 152 at the semiconductor substrate 100 may partially overlap with the vertical projection of the buried portion 125 of the second buried layer 120 furthest from the first buried layer 110 at the semiconductor substrate 100.
In some embodiments, as shown in FIG. 1C, the second top doped region 152 has a third sidewall 152-S3 and a fourth sidewall 152-S4 opposite the third sidewall 152-S3, and the third sidewall 152-S3 is closer to the first well region 141, wherein all buried portions of the second buried layer 120 that are furthest from the buried portion of the first buried layer 110, such as the buried portion 125, correspond under the third sidewall 152-S3 of the second top doped region 152. In some examples, a vertical extension L of the third sidewall 152-S3 of the second top doped region 152 is shown in FIG. 1C S3 Sidewalls 125-S of buried portion 125 of second buried layer 120 are aligned (along second direction D2), or do not exceed, this vertical extension L S3 。
It is noted that the drawings in this example are drawn to illustrate that the second buried layer 120 includes 5 buried portions 121, 122, 123, 124, 125 disposed apart from each other. The invention is not limited to the number of embedded portions shown in this example. According to some embodiments of the present invention, second buried layer 120 may include 3 or more buried portions, such as 3, 4, and/or,5, 6, which are equally spaced apart at the deep well 131 and the surface 101a of the semiconductor substrate 100, the plurality of buried portions corresponding to under the second well 142 and not exceeding a vertically extending line L of the third sidewall 152-S3 of the second top doped region 152 as shown in fig. 1C S3 The effect of obviously improving the breakdown voltage and improving the manufacturing process window to enlarge the operation range can be achieved under the condition of not increasing or even reducing the leakage current of the substrate.
Additionally, in some embodiments, a third top doped region (third top doping region) 153 can be formed in the third well 143, wherein the third top doped region 153 extends downward from the top surface 131a of the deep well 131 and has a second conductive morphology, e.g., N-type. The conductive form of the third top doped region 153 is different from the conductive forms (first conductive form, e.g., P-type) of the first top doped region 151 and the second top doped region 152. In some embodiments, the doping concentration of the third top doped region 153 is about 1x10 19 Atom/cubic centimeter (atoms/cm) 3 ) Up to about 5x10 20 Atom/cubic centimeter (atoms/cm) 3 ) Within a range of (2). In some embodiments, the doping concentration of the third top doping region 153 may be substantially equal to the doping concentration of the first top doping region 151 and the doping concentration of the second top doping region 152. Furthermore, in some embodiments, the first top doped region 151 and the second top doped region 152 may be formed in the same manufacturing process, while the third top doped region 153 is formed in another manufacturing process.
Furthermore, in some embodiments, a fourth top doped region (fourth top doping region) 154 can be formed in another P-type deep well 132 (also referred to as a high-voltage P-type deep well) adjacent to the deep well 131, wherein the fourth top doped region 154 extends downward from the top surface 131a of the deep well 131 and has a first conductive morphology, such as P-type. In some embodiments, the doping concentration of the fourth top doping region 154 may be approximately equal to the doping concentration of the first top doping region 151 and the doping concentration of the second top doping region 152. Furthermore, the conductive form of the fourth top doped region 154 is the same as the conductive form of the first top doped region 151 and the second top doped region 152, so that the fourth top doped region 154 can be formed in the same manufacturing process as the first top doped region 151 and the second top doped region 152.
In some embodiments, the first well 141, the first top doped region 151, the second well 142, the second top doped region 152, and the fourth top doped region 154 are located in the potential transition region A L And third well 143 and third top doped region 153 may be located adjacent to potential transition region a L High-pressure region A of (2) HV Is a kind of medium. In some embodiments, the first well 141 and the second well 142 can be respectively used as the potential conversion region A L The first and second top doped regions 151 and 152 may serve as a source region and a drain region, respectively, of the potential conversion cell (level shifting unit). In one example, the fourth top doped region 154 may be used as a bulk region (bulk region) of the potential conversion cell. Furthermore, in the subsequent manufacturing process, the first top doped region 151 (the source region of the potential conversion unit) is electrically connected to the high voltage region A HV The top doped region of one of the high voltage cells, the third top doped region 153 in this example, is such that the potential transition region A L Potential conversion unit and high voltage region a in (a) HV The high voltage unit is electrically connected.
Then, according to some embodiments, a field oxide layer is formed on the corresponding well region of the epitaxial layer, the field oxide layer including a plurality of spaced apart field oxide portions.
Referring to fig. 1D, a first field oxide portion (first field oxide portion) 161 is formed over the first well region 141, one side of the first field oxide portion 161 is adjacent to the first top doped region 151, and a portion of the first field oxide portion 161 is embedded in the first top doped region 151. And, a second field oxide portion (second field oxide portion) 162 is formed over the second well region 142, one side of the second field oxide portion 162 is adjacent to the second top doped region 152, and a portion of the second field oxide portion 162 is embedded in the second top doped region 152. Furthermore, in some embodiments, buried portions of second buried layer 120, such as buried portions 121, 122, 123, 124, 125, correspond to second field oxide 162, as shown in FIG. 1D. In this example, the vertical projection of the buried portion of second buried layer 120 on semiconductor substrate 100 is within the vertical projection of second field oxide 162 on semiconductor substrate 100.
In addition, in some embodiments, the field oxide layer further includes a third field oxide (third field oxide portion) 163, a fourth field oxide (fourth field oxide portion) 164, a fifth field oxide (fifth field oxide portion) 165, and a sixth field oxide (sixth field oxide portion) 166. As shown in fig. 1D, specifically, the third field oxide 163 in this example is located between the first top doped region 151 and the third top doped region 153. The fourth field oxide 164 in this example is located between the second top doped region 152 and the fourth top doped region 154, and the fourth field oxide 164 extends over the deep wells 131 and 132. The fifth field oxide 165 in this example adjoins the third well 143, and the fifth field oxide 165 and the third field oxide 163 adjoin both sides of the third top doped region 153, respectively. The sixth field oxide 166 in this example adjoins the fourth top doped region 154, and the sixth field oxide 166 and the fourth field oxide 164 adjoin both sides of the fourth top doped region 154, respectively.
In some embodiments, the field oxide layer includes, for example, a first field oxide 161, a second field oxide 162, a third field oxide 163, a fourth field oxide 164, a fifth field oxide 165, and a sixth field oxide 166, is made of silicon oxide, and is a silicon local oxidation (local oxidation of silicon, LOCOS) isolation formed by a thermal oxidation method. In other embodiments, the field oxide may be a shallow trench isolation (shallow trench isolation, STI) structure formed by an etch and deposition process.
Next, in some embodiments, after forming the field oxide layer, electrode fabrication of the relevant elements in each region is performed, for example, forming a gate. Referring to fig. 1D again, a gate 170 is formed on the top surface 131a of the deep well 131, and the first well 141 and the second well 142 are respectively overlapped with the bottom surface of the gate 170. In this example, the gate 170 is located in the potential conversion region A L A gate of the potential conversion unit.
Furthermore, as shown in fig. 1D, in some embodiments, the gate 170 is located between the first field oxide 161 and the second field oxide 162, and two sides of the gate 170 extend above the first field oxide 161 and the second field oxide 162. In other words, two sides of the first field oxide 161 are adjacent to the first top doped region 151 and the gate 170, respectively, and two sides of the second field oxide 162 are adjacent to the second top doped region 152 and the gate 170, respectively.
In some embodiments, the vertical projection of the first buried layer 110 at the semiconductor substrate 100 overlaps with the vertical projection of the second well region 142 at the semiconductor substrate 100. It is noted that, as shown in FIG. 1D, in some embodiments, a lateral edge 110-S1 of the first buried layer 110 adjacent to the second buried layer 120 (e.g., buried portion 121) is located below a first sidewall 142-S1 of the second well region 142, but not more than below a sidewall 170-S of the gate 170. In some embodiments, a vertical extension L of the first sidewall 142-S1 of the second well 142 is shown in FIG. 1D S1 Vertical extension line L of sidewall 170-S of gate 170 (along second direction D2) G1 The side edge 110-S1 of the first buried layer 110 may contact or exceed the vertical extension L of the first sidewall 142-S1 of the second well region 142 (along the second direction D2) S1 But not beyond the vertical extension L of the sidewall 170-S of the gate 170 G1 。
Then, referring to fig. 1E, in some embodiments, a dielectric layer 180 is formed on the epitaxial layer and the desired conductive features are formed to complete the electrical connection of the relevant components in the high voltage semiconductor device. In some embodiments, the conductive features are, for example, interconnect structures disposed within and over the dielectric layer 180.
In some embodiments, the dielectric layer 180 may be a single dielectric material layer or may comprise a multi-layer structure formed of two or more dielectric materials. The dielectric material is, for example, silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (phosphosilicate glass, PSG), borophosphosilicate glass (borophosphosilicate glass, BPSG), low-k dielectric material, or other suitable dielectric material.
Referring again to fig. 1E, in some embodiments, the conductive portion 190 is formed to include, for example, a plurality of vias (e.g., first via 191V, second via 192V, third via 193V, and fourth via 194V) and conductive lines (e.g., conductive line 191M, conductive line 192M, and conductive line 194M) located above the vias. The material of the conductive portion 190 includes, for example, a metal material.
As shown in fig. 1E, specifically, the first via 191V is located on the first top doped region 151, the second via 192V is located on the second top doped region 152, the third via 193V is located on the third top doped region 153, the fourth via 194V is located on the fourth top doped region 154, the wire 191M is located over the first via 191V and the third via 193V, the wire 192M is located over the second via 192V, and the wire 194M is located over the fourth via 194V. Wherein the conductive line 191M connects the first via 191V and the third via 193V in parallel to make the potential conversion area A L A source region (i.e. the first top doped region 151) of the potential conversion unit of (a) is electrically connected to the high voltage region A HV A top doped region (i.e., the third top doped region 153) of the high voltage unit to complete the electrical connection between the potential conversion unit and the high voltage unit.
Compared with the conventional high-voltage semiconductor device, the high-voltage semiconductor device according to some embodiments of the present invention has the advantage that the substrate leakage current (substrate leakage current) increases with the increase of the breakdown voltage (breakdown voltage), the high-voltage semiconductor device according to some embodiments of the present invention can effectively increase the breakdown voltage without increasing or even decreasing the substrate leakage current, and the Process window (Process window) can be increased, so that the operation range is enlarged.
Simulation experiments are also presented herein to compare breakdown voltages of conventional high voltage semiconductor devices and high voltage semiconductor devices fabricated according to some embodiments of the present invention. In the simulation experiment, three control groups of high voltage semiconductor devices (as shown in fig. 2, 3, and 4) and one group of high voltage semiconductor devices (as shown in fig. 1E) manufactured according to some embodiments of the present invention were proposed. For convenience of description, the same reference numerals are used for the same components or layers as those in fig. 1E in fig. 2, 3 and 4, and the contents of the components or layers are referred to above, which will not be repeated here.
Fig. 2 is a schematic cross-sectional view of a conventional high-voltage semiconductor device according to the control group 1 in a simulation experiment. In comparison with the high voltage semiconductor device according to some embodiments of the present invention as shown in fig. 1E, the buried structure in the control group 1 is different from the first buried structure 110 only.
Fig. 3 is a schematic cross-sectional view of a high-voltage semiconductor device according to control group 2 in a simulation experiment. In comparison with the high voltage semiconductor device of some embodiments of the present invention as shown in fig. 1E, the buried layer structure in the control group 2 includes a first buried layer 110 and 1 buried portion 121 adjacent to the first buried layer 110.
Fig. 4 is a schematic cross-sectional view of a high-voltage semiconductor device according to control group 3 in a simulation experiment. In comparison with the high voltage semiconductor device according to some embodiments of the present invention shown in fig. 1E, the buried layer structure of the control group is different in that the buried portions 121-128 of the second buried layer 120 are distributed under the second well region 142, and the buried portion 128 farthest from the first buried layer 110 corresponds to under the second sidewall 142-S2 of the second well region 142.
In the simulation experiment, the length of the first buried layer 110 of the high voltage semiconductor device of the control group 1, 2, 3 and the embodiment is about 46 μm along the first direction D1.
In the simulation, the implantation doses of the P-type drift regions, i.e., the first well region 141 and the second well region 142, are varied, and the breakdown voltages of the three control high voltage semiconductor devices (shown in fig. 2, 3, and 4) and one high voltage semiconductor device (shown in fig. 1E) are measured at the different implantation doses of the drift regions. In the simulation experiment, the implantation doses of the P-type drift regions are 7.00x10 respectively 12 Atoms/cm 2 、7.50x10 12 Atoms/cm 2 、8.00x10 12 Atoms/cm 2 、8.50x10 12 Atoms/cm 2 、9.00x10 12 Atoms/cm 2 . Fig. 5 is a graph showing breakdown voltages of three control groups and one embodiment of a high voltage semiconductor device at different drift region implant doses in a simulation experiment. Table 1 shows the breakdown voltage values (V) measured for the high voltage semiconductor devices of the three control groups and one example in the simulation experiment.
TABLE 1
Figure BDA0003023638650000151
According to the results of the simulation experiments, referring to fig. 5 and table 1, at the same implantation dose of the P-type drift region, the implantation dose was 7×10 12 Atoms/cm 2 To 8.5x10 12 Atoms/cm 2 In comparison with the other three control groups 1-3, the high voltage semiconductor device (as shown in fig. 1E) of the embodiment of the invention has a higher breakdown voltage, and is suitable for high voltage operation.
Note that although the implantation dose in the P-type drift region is 9x10 12 Atoms/cm 2 In the case of the high voltage semiconductor device of the control group 3 (the buried portion of the second buried layer 120 is distributed below the second sidewall 142-S2 corresponding to the second well region 142), the breakdown voltage is about 586V, which is slightly higher than the breakdown voltage of the high voltage semiconductor device of the embodiment by about 554V, but is also lower than the operation voltage 600V required by the general high voltage semiconductor device. Furthermore, the implantation dose of the high voltage semiconductor device of the control group 3 in the P-type drift region was 7×10 12 Atoms/cm 2 To 8.5x10 12 Atoms/cm 2 Between the ranges, the breakdown voltage is only about 84V to about 193V, which is much lower than the 600V operating voltage of a typical high voltage semiconductor device. Therefore, the high voltage semiconductor device of the control group 3 is not suitable for application to a high voltage semiconductor device operating at a high voltage of about 600V.
Compared with the other three control groups 1-3, the high voltage semiconductor device of the embodiment of the invention has higher breakdown voltage exceeding 600V, especially the implantation dosage of 7x10 in the P-type drift region 12 Atoms/cm 2 To 8.5x10 12 Atoms/cm 2 In the range, the breakdown voltage of the high-voltage semiconductor device of the embodiment exceeds 730V, so that the high-voltage semiconductor device is very suitable for being applied to the high-voltage semiconductor device operated at the high voltage of about 600V, and the operating voltage range is larger, so that the manufacturing process window is increased. Implant dose of 7.5x10 with P-type drift region 12 Atoms/cm 2 For example, the breakdown voltage of the high voltage semiconductor device according to an embodiment of the invention can be raised to about 848V, so thatThe range of the operating voltage of the high voltage semiconductor device can be expanded to more than 800V, for example, about 840V.
Furthermore, in the simulation, the implantation dose of the same P-type drift region (e.g., 7.5x10 12 Atoms/cm 2 ) The substrate leakage current (substrate leakage current) and the calculated process window increase ratio (%) of the control groups 1-3 and the high voltage semiconductor device according to an embodiment of the present invention were measured. Table 2 shows the values of breakdown voltage (V), manufacturing process window increase (%) and substrate leakage current (μA/. Mu.m) of the high voltage semiconductor devices of the three control groups and one example in the simulation experiment.
TABLE 2
Figure BDA0003023638650000161
In the simulation experiment, the length of the first buried layer 110 (fig. 1E, 2 to 4) of the high voltage semiconductor device of the 3-group control group and the embodiment is about 46 μm along the first direction D1.
According to the results of the simulation experiment, referring to table 2, the implantation dose in the same P-type drift region is 7.5x10 12 Atoms/cm 2 Next, the breakdown voltages (V) of the control groups 1-3 and the high voltage semiconductor device according to an embodiment of the present invention were about 743V, about 766V, about 91V, and about 848V, respectively. The process window increase (%) for the control groups 1-3 and the high voltage semiconductor device according to an embodiment of the present invention is less than about 2%, about 3%, less than about 0.8%, and up to about 20%, respectively. Furthermore, the substrate leakage currents of the control groups 1-3 and the high voltage semiconductor device according to an embodiment of the present invention were about 680. Mu.A/μm, about 332. Mu.A/μm, and about 659. Mu.A/μm, respectively.
Although the substrate leakage current of the high voltage semiconductor device of the control group 3 was reduced to 332 μa/μm, the breakdown voltage (V) thereof was only about 91V, which is far lower than the operation voltage 600V of the general high voltage semiconductor device, and the manufacturing process window was too narrow (less than about 0.8%), so that the high voltage semiconductor device of the control group 3 was not suitable for the high voltage operation. Compared with the other three high voltage semiconductor devices of the control groups 1-3, the high voltage semiconductor device of the embodiment of the invention has the highest breakdown voltage (about 848V), effectively improves the breakdown voltage without increasing or even reducing the leakage current of the substrate, improves the manufacturing process window (about 20%), and enlarges the operation range, thus being very suitable for being applied to the high voltage semiconductor device operated at the high voltage of about 600V.
In addition, in the simulation experiment, the characteristic curves of the source current (source current) versus the source voltage (source voltage) of the control group 1 and the high-voltage semiconductor device according to an embodiment of the present invention were observed at the same implantation dose of the P-type drift region.
Fig. 6A shows the implantation dose of 7.5x10 in the P-type drift region of the high voltage semiconductor device of the control group 1 (i.e. the conventional buried layer structure with only the first buried layer) in the simulation experiment 12 Atoms/cm 2 The characteristic curve of the source current (expressed as logarithm) versus the source voltage is shown below, wherein the breakdown voltage is about 743V. Fig. 6B is a simulation experiment showing an implant dose of 7.5x10 in a P-type drift region for a high voltage semiconductor device according to some embodiments of the present invention 12 Atoms/cm 2 The characteristic curve of the source current (in logarithmic terms) versus the source voltage is shown below, with a breakdown voltage of approximately 848V.
According to the simulation results of fig. 6A and 6B, the two high voltage semiconductor devices have characteristic curves with the same trend, but the high voltage semiconductor device according to an embodiment of the present invention has a higher breakdown voltage. The breakdown voltage of the high-voltage semiconductor device of the embodiment is improved by about 12.3% (i.e., 100% x (848V-743V)/743V) compared to the conventional high-voltage semiconductor device having only the first buried layer, and the breakdown voltage can be effectively improved without increasing or even decreasing the substrate leakage current (e.g., substrate leakage current of about 659 μa/μm in table 2, slightly lower than substrate leakage current of about 680 μa/μm in the control group 1-2).
Furthermore, the depletion region (depletion region) generated by the control group 1 and the high voltage semiconductor device according to an embodiment of the present invention when the bias voltage is applied is also measured to be perpendicular to the depth (depth) of the semiconductor substrate 100. The results showed that the depletion regions of the high voltage semiconductor devices of the control group 1 and the examples were about 81.90 μm and 89.68 μm, respectively, in depth perpendicular to the semiconductor substrate 100 under the same bias applied. Thus, the high voltage semiconductor device of the embodiment creates a deeper and larger depletion region, i.e., the high voltage semiconductor device of the embodiment can be more fully depleted, increasing the breakdown voltage.
Fig. 7 is a graph showing a source current (expressed as logarithm) versus a source voltage for a high voltage semiconductor device according to some embodiments of the invention at different P-drift region implant doses in a simulation experiment. As shown in the simulation results of FIG. 7, the implantation dose in the P-type drift region is 7x10 12 Atoms/cm 2 To 9x10 12 Atoms/cm 2 In the case of the high-voltage semiconductor device of the embodiment, the characteristic curves of the high-voltage semiconductor device are the same. Furthermore, the implantation dosage of the P-type drift region is 7.5x10 12 Atoms/cm 2 Increased to 9x10 12 Atoms/cm 2 The breakdown voltage of the high voltage semiconductor device of the embodiment is reduced, however, at the implantation dose from 7.5x10 12 Atoms/cm 2 To 8.5x10 12 Atoms/cm 2 The breakdown voltage (848V-736V) is still far greater than 600V.
In summary, the design of the buried layer structure of the high-voltage semiconductor device according to some embodiments of the present invention is beneficial to effectively improving the breakdown voltage without increasing or even reducing the leakage current of the substrate. In some embodiments, the buried layer structure has a conductivity type opposite to that of the semiconductor substrate 100 and the drift region (i.e., the first well region 141 and the second well region 142). As shown in the above simulation results, the breakdown voltage of the high-voltage semiconductor device of the embodiment is significantly improved, for example, by about 12.3%. Furthermore, the high voltage semiconductor device of some embodiments of the present invention may further improve the manufacturing process window, making the operating range larger, for example, up to about 20%. In summary, the buried layer structure according to some embodiments of the present invention can improve the electrical performance of the high voltage semiconductor device. In addition, the high-voltage semiconductor device and the manufacturing method thereof provided by the embodiment only need to properly adjust the mask pattern in the steps of the existing manufacturing process, so that the high-voltage semiconductor device is compatible with the existing manufacturing process, and no additional mask is required to be added, thereby not increasing the manufacturing cost.
Although the present invention has been described with respect to the preferred embodiments, it should be understood by those skilled in the art that the present invention is not limited thereto, and that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined by the following claims.

Claims (15)

1. A high voltage semiconductor device having a buried layer structure, comprising:
a semiconductor substrate having a first conductive pattern;
a deep well on the semiconductor substrate, the deep well having a second conductivity type different from the first conductivity type;
a first well region and a second well region which are arranged in the deep well at a distance from each other, and extend downwards from the top surface of the deep well, wherein the first well region and the second well region have the first conductive form;
a gate electrode located on the top surface of the deep well, wherein the first well region and the second well region are respectively overlapped with the bottom surface of the gate electrode;
a first top doped region and a second top doped region respectively located in the first well region and the second well region, wherein the first top doped region and the second top doped region have the first conductive form; and
A buried layer structure at a surface of the deep well and the semiconductor substrate, the buried layer structure comprising:
a first buried layer having the second conductive pattern, the first buried layer being a continuous buried layer and being disposed corresponding to the first well region, wherein the first buried layer continuously extends from a high voltage region of the high voltage semiconductor device to a potential conversion region; and
and the second buried layer is provided with the second conductive form, comprises a plurality of buried parts which are arranged at intervals, corresponds to the second well region and is positioned in the potential conversion region.
2. The high voltage semiconductor device of claim 1, wherein the second well region has a first sidewall and a second sidewall opposite the first sidewall, and the first sidewall is closer to the first well region, a side edge of the first buried layer adjacent to the second buried layer being located below the first sidewall of the second well region.
3. The high voltage semiconductor device of claim 1, wherein the second well region has a first sidewall and a second sidewall opposite the first sidewall, and the first sidewall is closer to the first well region, a side edge of the first buried layer adjacent to the second buried layer exceeding under the first sidewall of the second well region but not exceeding under a sidewall of the gate.
4. The high voltage semiconductor device of claim 2, wherein the second top doped region has a third sidewall and a fourth sidewall opposite the third sidewall, and the third sidewall is closer to the first well region, a buried portion of the plurality of buried portions furthest from the first buried layer not exceeding under the third sidewall.
5. The high voltage semiconductor device of claim 1, wherein the plurality of buried portions of the second buried layer are equidistantly distributed at a surface of the deep well and the semiconductor substrate.
6. The high voltage semiconductor device according to claim 1, wherein the plurality of buried portions of the second buried layer have the same width in the first direction.
7. The high voltage semiconductor device of claim 1, wherein the plurality of buried portions includes a first buried portion closest to the first buried layer, the first buried portion being spaced from the first buried layer by a distance equal to a spacing between two adjacent ones of the plurality of buried portions.
8. The high voltage semiconductor device according to claim 1, wherein the first buried layer has a first height in a second direction, the plurality of buried portions of the second buried layer has a second height in the second direction, and the first height is equal to the second height.
9. The high voltage semiconductor device according to claim 1, wherein the plurality of buried portions of the second buried layer are spaced apart from each other by a pitch in the first direction, the plurality of buried portions each having a width in the first direction, the width being equal to the pitch.
10. The high voltage semiconductor device according to claim 1, wherein the second buried layer includes 3 or more of the plurality of buried portions, wherein the plurality of buried portions have the same height in the second direction.
11. The high voltage semiconductor device of claim 1, wherein a doping concentration of the first buried layer and the second buried layer is higher than a doping concentration of the deep well and higher than a doping concentration of the first well region and the second well region.
12. The high voltage semiconductor device according to claim 1, wherein the first well region and the second well region are located in the potential conversion region and are a first drift region and a second drift region, respectively, of a potential conversion unit of the potential conversion region, wherein the plurality of buried portions of the second buried layer are located within a vertical projection of the second drift region in the semiconductor substrate.
13. The high voltage semiconductor device according to claim 1, further comprising:
the first field oxidation part is positioned between the first top doping region and the grid electrode, and two sides of the first field oxidation part are respectively adjacent to the first top doping region and the grid electrode; and
a second field oxide part between the second top doped region and the gate, wherein the second field oxide part is separated from the first field oxide part, and two sides of the second field oxide part are respectively adjacent to the second top doped region and the gate,
wherein the plurality of buried portions of the second buried layer correspond to the second field oxide portion.
14. The high voltage semiconductor device of claim 1, wherein said potential conversion region is located between said high voltage region and a low voltage region, said gate is a gate of a potential conversion cell located in said potential conversion region, and wherein said first top doped region and said second top doped region are a source region and a drain region of said potential conversion cell located in said potential conversion region, respectively, wherein said source region is electrically connected to a top doped region of a high voltage cell in said high voltage region.
15. The high voltage semiconductor device according to claim 1, further comprising:
and a conductive part electrically connected with the first top doped region in the potential conversion region and a third top doped region in the high voltage region.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN85108671A (en) * 1984-12-03 1986-06-10 株式会社日立制作所 Semiconductor device and manufacturing process thereof
US8575693B1 (en) * 2012-05-24 2013-11-05 Richtek Technology Corporation Double diffused metal oxide semiconductor device
CN104835837A (en) * 2015-06-05 2015-08-12 杭州士兰微电子股份有限公司 High voltage semiconductor device and manufacture method thereof
CN108847423A (en) * 2018-05-30 2018-11-20 矽力杰半导体技术(杭州)有限公司 Semiconductor devices and its manufacturing method
CN109427913A (en) * 2017-08-29 2019-03-05 新唐科技股份有限公司 Semiconductor device and method for manufacturing the same
CN109545853A (en) * 2017-09-21 2019-03-29 新唐科技股份有限公司 semiconductor substrate structure and semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9437673B2 (en) * 2014-02-05 2016-09-06 Alpha And Omega Semiconductor Incorporated Floating guard ring for HV interconnect
US9460926B2 (en) * 2014-06-30 2016-10-04 Alpha And Omega Semiconductor Incorporated Forming JFET and LDMOS transistor in monolithic power integrated circuit using deep diffusion regions
US9831305B1 (en) * 2016-05-06 2017-11-28 Vanguard International Semiconductor Corporation Semiconductor device and method for manufacturing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN85108671A (en) * 1984-12-03 1986-06-10 株式会社日立制作所 Semiconductor device and manufacturing process thereof
US8575693B1 (en) * 2012-05-24 2013-11-05 Richtek Technology Corporation Double diffused metal oxide semiconductor device
CN104835837A (en) * 2015-06-05 2015-08-12 杭州士兰微电子股份有限公司 High voltage semiconductor device and manufacture method thereof
CN109427913A (en) * 2017-08-29 2019-03-05 新唐科技股份有限公司 Semiconductor device and method for manufacturing the same
CN109545853A (en) * 2017-09-21 2019-03-29 新唐科技股份有限公司 semiconductor substrate structure and semiconductor device
CN108847423A (en) * 2018-05-30 2018-11-20 矽力杰半导体技术(杭州)有限公司 Semiconductor devices and its manufacturing method

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