CN117198981A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN117198981A
CN117198981A CN202210602075.1A CN202210602075A CN117198981A CN 117198981 A CN117198981 A CN 117198981A CN 202210602075 A CN202210602075 A CN 202210602075A CN 117198981 A CN117198981 A CN 117198981A
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China
Prior art keywords
layer
well region
semiconductor device
buried layer
epitaxial layer
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CN202210602075.1A
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Chinese (zh)
Inventor
廖志成
罗宗仁
刘兴潮
李俊葳
廖学骏
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Vanguard International Semiconductor Corp
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Vanguard International Semiconductor Corp
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Priority to CN202210602075.1A priority Critical patent/CN117198981A/en
Publication of CN117198981A publication Critical patent/CN117198981A/en
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Abstract

A semiconductor device includes a substrate, a first buried layer, a second buried layer, a first well region, a second well region, a deep trench isolation structure, a source region, a drain region, and a gate electrode. The first buried layer and the second buried layer are both of a first conduction type and are arranged in the substrate, the second buried layer is arranged on the first buried layer, the first well region is of the first conduction type and is arranged above the second buried layer, the second well region is of a second conduction type and is adjacent to the first well region, the deep trench isolation structure is arranged in the substrate and surrounds the first well region and the second well region, the bottom surface of the deep trench isolation structure is lower than the bottom surface of the first buried layer, the source region is arranged in the second well region, the drain region is arranged in the first well region, and the gate electrode is arranged on the first well region and the second well region.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates generally to semiconductor technology, and more particularly, to a semiconductor device including an isolation structure for improving leakage current of a substrate and a method of fabricating the same.
Background
The semiconductor device generally includes P-well and N-well, and the semiconductor device having the staggered structure of P-well and N-well may cause latch-up (latch-up) due to parasitic bipolar transistor (bipolar junction transistor, BJT) to reduce the reliability of the semiconductor device. The existing method for preventing latch-up is to increase the distance between PN junctions or to form isolation structures at the PN junctions. As the operating voltage of the semiconductor device increases, the distance between the required PN junctions increases, or the size of the junction isolation structure increases, which results in an increase in the size of the semiconductor device.
However, in the development of electronic products, the size of the semiconductor device needs to be reduced, and the conventional method for preventing latch-up cannot increase the size of the semiconductor device when the operating voltage of the semiconductor device is increased, so that there is a need in the art for a semiconductor device that can improve the above-mentioned problems.
Disclosure of Invention
In view of the above, the present invention provides a semiconductor device and a method for manufacturing the same, which includes an isolation structure to improve the substrate leakage current, and the semiconductor device can reduce parasitic bipolar transistor characteristics of the semiconductor device without increasing the size of the semiconductor device when the operation voltage is increased, so as to reduce the substrate leakage current and prevent latch-up, and improve the breakdown voltage and reliability of the semiconductor device, thereby achieving isolation effect similar to that of the semiconductor device using a silicon-on-insulator (SOI) substrate.
According to one embodiment of the present invention, a semiconductor device is provided, which includes a substrate, a first buried layer, a second buried layer, a first well region, a second well region, a deep trench isolation structure, a source region, a drain region, and a gate electrode. The first buried layer is provided with a first conductive type and is arranged in the substrate, the second buried layer is provided with a first conductive type and is arranged on the first buried layer, the first well region is provided with a first conductive type and is arranged above the second buried layer, the second well region is provided with a second conductive type opposite to the first conductive type and is adjacent to the first well region, the deep trench isolation structure is arranged in the substrate and surrounds the first well region and the second well region, the bottom surface of the deep trench isolation structure is lower than the bottom surface of the first buried layer, the source region is arranged in the second well region, the drain region is arranged in the first well region, and the gate electrode is arranged on the first well region and the second well region.
According to an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device including the steps of: providing a substrate; forming a first buried layer in the substrate, the first buried layer having a first conductivity type; forming a second buried layer on the first buried layer, the second buried layer having the first conductivity type; forming a first well region over the second buried layer, the first well region having a first conductivity type; forming a second well region adjacent to the first well region, the second well region having a second conductivity type opposite to the first conductivity type; forming a deep trench isolation structure in the substrate and surrounding the first well region and the second well region, wherein the bottom surface of the deep trench isolation structure is lower than the bottom surface of the first buried layer; forming a source region in the second well region; forming a drain region in the first well region; and forming a gate electrode on the first well region and the second well region.
In order to make the features of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
For easier understanding, reference is made to the drawings and their detailed description when reading the present invention. Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the various features of the invention. Moreover, for the sake of clarity, various features in the drawings may not be drawn to actual scale, and thus the dimensions of some features in some of the drawings may be exaggerated or reduced on purpose.
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention.
Fig. 4, 5, 6, 7, 8 and 9 are schematic cross-sectional views illustrating an intermediate stage of a method of manufacturing a semiconductor device according to an embodiment of the invention.
Fig. 10 is a graph of substrate current versus source voltage for a semiconductor device according to some embodiments of the present invention.
Reference numerals illustrate:
10 … substrate
100 … semiconductor device
101 … semiconductor substrate
103 … first epitaxial layer
105 a … a second epitaxial layer
107 … first buried layer
109 … second buried layer
111 … first well region
112 … doped region
113 … second well region
114 … basal body region
115 … third well region
117 … fourth well region
120 … deep trench isolation structure
121 … core
121-1 … lower portion
121-2 … upper part
123 … Trench isolation portion
125 … lining
127 … peripheral part
129 … dielectric spacer
131 … first isolation region
132 and … second isolation region
133 … third isolation region
134 … fourth isolation region
141 … gate electrode
143 … drain region
145 … source region
147 … insulating layer
149 … Metal layer
151. 153, 155, 157, 159, … heavily doped contact regions
161. 163, 165, 169, 181 … patterned photoresist layer
167 … shallow trench
171 … first dielectric material layer
173 … hard shield
175 … initial groove
177 … deep trench
178 … groove
179 … second dielectric Material layer
183 … projection
190 … filler material layer
192 … gate dielectric
194 … gate electrode material layer
Steps S201, S203, S205, S207, S209, S211, S213, S215, S217, S219, S221, S223, S225, S227, S229, S231, S233 and 233 …
T … total thickness
H … depth
T1 … first thickness
T2 … second thickness
T3 … third thickness
T4 … fourth thickness
T5 … fifth thickness
Detailed Description
The invention provides several different embodiments that can be used to implement different features of the invention. For simplicity of explanation, the invention also describes examples of specific components and arrangements. These examples are provided for the purpose of illustration only and are not intended to be limiting in any way. For example, the following description of a first feature being formed on or over a second feature may refer to the first feature being in direct contact with the second feature, or may refer to other features being present between the first and second features, such that the first and second features are not in direct contact. Furthermore, various embodiments of the present invention may use repeated reference characters and/or textual notations. These repeated reference characters and notations are used to make the description more concise and clear, rather than to indicate a relationship between different embodiments and/or configurations.
In addition, for the spatially related narrative terms mentioned in the present invention, for example: when "under", "low", "lower", "upper", "top", "bottom" and the like, for ease of description, the description is used to describe one element or feature's relative relationship to another element(s) or feature(s) in the figures. In addition to the orientation shown in the drawings, these spatially dependent terms are also used to describe possible orientations of the semiconductor device in use and operation. With the semiconductor device oriented differently (rotated 90 degrees or other orientations), the spatially relative descriptors describing its orientation should be interpreted in a similar manner.
Although the invention has been described in the language of first, second, third, etc., to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section, which does not itself imply any preceding ordinal number or order of arrangement or method of manufacture of the element. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the embodiments of the present invention.
The terms "about" or "substantially" as referred to herein generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are about amounts, i.e., without a specific recitation of "about" or "substantially," the meaning of "about" or "substantially" may still be implied.
The terms "coupled," "coupled," and "electrically connected" as used herein include any direct or indirect electrical connection. For example, if a first element is coupled to a second element, that connection may be directly to the second element or indirectly to the second element through other means of attachment or connection.
Although the invention is described below by way of specific embodiments, the inventive principles of this patent are applicable to other embodiments as well. Furthermore, specific details are omitted so as not to obscure the spirit of the present invention, and such omitted details are within the knowledge of persons of ordinary skill in the art.
The invention relates to a semiconductor device comprising an isolation structure for improving substrate leakage current and a manufacturing method thereof, wherein the semiconductor device comprises a first buried layer, a second buried layer and a deep trench isolation structure which are arranged in a substrate, and the arrangement of the isolation structures can reduce the parasitic bipolar transistor characteristics in the semiconductor device, further reduce the substrate leakage current and prevent latch-up, achieve the isolation effect similar to that of the semiconductor device using a silicon-on-insulator (SOI) substrate, thereby saving the manufacturing cost of the semiconductor device and avoiding the problem of poor heat conduction using the SOI substrate. In addition, when the semiconductor device is applied to high operation voltage, the substrate leakage current can be effectively reduced without increasing the size of the semiconductor device, so that the breakdown voltage of the semiconductor device is improved, and the reliability of the semiconductor device is improved.
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention. As shown in fig. 1, in an embodiment, a semiconductor device 100 includes a substrate 10, the substrate 10 includes a semiconductor substrate 101, a first epitaxial layer 103 and a second epitaxial layer 105, wherein the first epitaxial layer 103 is disposed on the semiconductor substrate 101, and the second epitaxial layer 105 is disposed on the first epitaxial layer 103. The material of the semiconductor substrate 101 may include silicon, silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN), or other suitable semiconductor materials, and in this embodiment, the first epitaxial layer 103 and the second epitaxial layer 105 are semiconductor epitaxial layers of a first conductivity type, semiconductor epitaxial layers of a second conductivity type, or a combination thereof, wherein the first conductivity type is N-type and the second conductivity type is P-type. In one embodiment, the substrate 101, the first epitaxial layer 103 and the second epitaxial layer 105 are semiconductor epitaxial layers of the second conductivity type (P-type silicon epitaxial layers). Furthermore, according to an embodiment of the present invention, the semiconductor device 100 further includes a first buried layer 107 having a first conductivity type, such as an N-type first buried layer (N-type firstburied layer, NBL 1), the first buried layer 107 being disposed in the substrate 10 and within the semiconductor substrate 101 and the first epitaxial layer 103. The semiconductor device 100 further includes a second buried layer 109 having a first conductivity type, such as an N-type second buried layer (N-type secondburied layer, NBL 2), the second buried layer 109 being disposed in the substrate 10 and within the first epitaxial layer 103 and the second epitaxial layer 105. According to an embodiment of the present invention, the doping concentration of the second buried layer 109 may be lower than or equal to the doping concentration of the first buried layer 107, so that the electrical properties of each doped region and each well region in the second epitaxial layer 105 are not affected by the second buried layer 109. Furthermore, in some embodiments, the thickness of the first buried layer 107 is greater than the thickness of the second buried layer 109, for example, the thickness of the first buried layer 107 may be 1.2 times to 2 times the thickness of the second buried layer 109, and the first buried layer 107 with a larger thickness and a higher doping concentration below may provide a good isolation effect for the semiconductor device 100 to reduce the substrate leakage current.
With continued reference to fig. 1, the semiconductor device 100 further includes a first well region 111 having a first conductivity type, such as a high-voltage N-well (HVNW), the first well region 111 is disposed in the second epitaxial layer 105 of the substrate 10 and is located above the second buried layer 109, a second well region 113 having a second conductivity type, such as a high-voltage P-well (HVPW), is also disposed in the second epitaxial layer 105 of the substrate 10, and the second well region 113 includes two portions respectively adjacent to opposite sides of the first well region 111. In addition, the semiconductor device 100 further includes a third well region 115 having a first conductivity type, such as an N-type high-voltage N-well (DHVNW), the third well region 115 is disposed in the second epitaxial layer 105 of the substrate 10 and surrounds the first well region 111 and the second well region 113 in a top view, wherein a bottom surface of the third well region 115 contacts a top surface of the second buried layer 109, and a bottom surface of the third well region 115 is lower than a bottom surface of the first well region 111 and a bottom surface of the second well region 113. In some embodiments, the bottom surface of the first well region 111 and the bottom surface of the second well region 113 may be flush, and the bottom surface of the first well region 111 is spaced apart from the second buried layer 109, and the bottom surface of the second well region 113 is also spaced apart from the second buried layer 109, between the first well region 111 and the second buried layer 109, and between the second well region 113 and the second buried layer 109, by portions of the second epitaxial layer 105. Since the first well region 111 is separated from the second buried layer 109 in the vertical direction, current can be prevented from flowing from the first well region 111 into the second buried layer 109.
According to an embodiment of the present invention, the semiconductor device 100 includes a deep trench isolation structure 120 disposed in the substrate 10 and penetrating the second epitaxial layer 105, the second buried layer 109, the first epitaxial layer 103 and the first buried layer 107 to a depth of the semiconductor substrate 101. The deep trench isolation structure 120 extends from the top surface of the second epitaxial layer 105 down into the semiconductor substrate 101, and the bottom surface of the deep trench isolation structure 120 is lower than the bottom surface of the first buried layer 107. Furthermore, as shown in fig. 1, in an embodiment, the deep trench isolation structure 120 surrounds the first well region 111, the second well region 113, and the third well region 115 in a top view, wherein the third well region 115 is located between the first well region 111 and the deep trench isolation structure 120, and is also located between the second well region 113 and the deep trench isolation structure 120. In some embodiments, deep trench isolation structure 120 comprises a core portion 121, a liner 125, and a periphery portion 127, wherein core portion 121 comprises a lower portion 121-1 and an upper portion 121-2, upper portion 121-2 may comprise a dielectric material, such as silicon oxide or other suitable dielectric material, and lower portion 121-1 comprises a semiconductor material, such as polysilicon. The liner 125 surrounds the sidewalls and bottom surface of the core 121. The liner 125 is formed of a material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The peripheral portion 127 surrounds a portion of the liner 125 and the upper portion 121-2 of the core portion 121, for example, the peripheral portion 127 surrounds the liner 125 and the upper portion 121-2 of the core portion 121 near the top surface of the second epitaxial layer 105, the material of the peripheral portion 127 is, for example, silicon oxide, and the bottom surface of the peripheral portion 127 may be slightly higher than the bottom surface of the upper portion 121-2 of the core portion 121. In some embodiments, the top surface of peripheral portion 127 and the top surface of upper portion 121-2 of core portion 121 may be on the same plane, and this same plane may be slightly higher than the top surface of second epitaxial layer 105. In some embodiments, the depth H of the deep trench isolation structure 120 is 1.5 times to 2.5 times the total thickness T of the first epitaxial layer 103 and the second epitaxial layer 105, and the total thickness T of the first epitaxial layer 103 and the second epitaxial layer 105 may be greater than or equal to about 10 micrometers (μm), but is not limited thereto. According to the embodiment of the invention, the deep trench isolation structure 120 can provide a good electrical isolation effect for the semiconductor device 100 to reduce the substrate leakage current.
With continued reference to fig. 1, the semiconductor device 100 further includes a fourth well 117 having a second conductivity type, such as a P-voltage P-well (HVPW), the fourth well 117 being disposed in the second epitaxial layer 105 of the substrate 10, and the fourth well 117 including two portions respectively adjacent to opposite outer sides of the deep trench isolation structure 120. In some embodiments, the doping concentration of the fourth well 117 may be the same as the doping concentration of the second well 113, and the bottom surface of the fourth well 117 may be flush with the bottom surface of the second well 113. In other embodiments, the doping concentration of the fourth well 117 may be different from the doping concentration of the second well 113, and the bottom surface of the fourth well 117 may be slightly higher or slightly lower than the bottom surface of the second well 113. In addition, the semiconductor device 100 further includes a source region 145, a drain region 143 and a gate electrode 141, wherein the source region 145 is disposed in the right portion of the second well region 113, the drain region 143 is disposed in the first well region 111, the gate electrode 141 is disposed on the first well region 111 and the second well region 113 and is located directly above the junction of the first well region 111 and the second well region 113, and the source region 145 and the drain region 143 are respectively located at two sides of the gate electrode 141. In some embodiments, the drain region 143 and the source region 145 are heavily doped regions of the first conductivity type, such as N-type heavily doped regions, and heavily doped contact regions 151 of the second conductivity type, such as P-type heavily doped contact regions (P + The heavily doped contact region 151 adjoins the source region 145. A body region 114 of a second conductivity type, e.g. a P-type body, is also provided in the right portion of the second well region 113Body region (P-body) and body region 114 is located directly below source region 145 and heavily doped contact region 151.
In addition, the semiconductor device 100 further includes a plurality of isolation regions, which may be disposed at the junctions of the well regions of different conductivity types, but the location of the isolation regions of the semiconductor device of the present invention is not limited thereto. In one embodiment, the isolation region is disposed in the second well region 113 where the source region 145 is located, and the first well region 111 where the drain region 143 is located, and the isolation region is also disposed outside the fourth well region 117. As shown in fig. 1, the first isolation region 131 is disposed in the right portion of the second well region 113 and at the junction of the first well region 111 and the left portion of the second well region 113, the second isolation region 132 is disposed at the junction of the second well region 113 and the third well region 115, the third isolation region 133 is disposed outside the fourth well region 117, the fourth isolation region 134 is disposed in the first well region 111 and between the drain region 143 and the gate electrode 141, and a portion of the fourth isolation region 134 is located directly below the gate electrode 141. In some embodiments, the first, second, and third isolation regions 131, 132, and 133 may be shallow trench isolation regions (shallow trench isolation, STI) or field oxide layers (field oxide layer), and the fourth isolation region 134 is a shallow trench isolation region.
In addition, the semiconductor device 100 further includes a plurality of heavily doped contact regions disposed in each well region, as shown in FIG. 1, having heavily doped contact regions 153 and 155 of the second conductivity type, such as P-type heavily doped contact regions (P) + contact region), wherein a heavily doped contact region 153 is disposed in the right portion of the second well region 113, a heavily doped contact region 155 is disposed in the left portion of the second well region 113, and both heavily doped contact regions 153 and 155 are located between the first isolation region 131 and the second isolation region 132. Heavily doped contact region 157 having the first conductivity type, e.g., an N-type heavily doped contact region (N + contact region) disposed in the third well region 115 and between the second isolation region 132 and the deep trench isolation structure 120. Heavily doped contact regions 159 of the second conductivity type, e.g. P-type heavily doped contact regions (P + contact region) disposed in the fourth well region 117 and between the deep trench isolation structure 120 and the third isolation region 133.In some embodiments, heavily doped contact region 151 and source region 145 are electrically connected to heavily doped contact region 153 and electrically coupled to a source/base voltage (V S/B ) The heavily doped contact region 157 is electrically coupled to an insulation voltage (Viso), and the heavily doped contact region 159 is electrically coupled to a substrate voltage (Vsub). The first buried layer 107, the second buried layer 109, and the third well region 115 are coupled to an insulation voltage (Viso) through the heavily doped contact region 157 to avoid unnecessary substrate leakage current during operation of the semiconductor device 100.
Furthermore, as shown in fig. 1, in some embodiments, a doped region 112 of the first conductivity type, such as an N-type field effect deposition region (N-type field effect deposition region, NFD), is also provided in the first well region 111, and a drain region 143 is located in the doped region 112. In addition, the semiconductor device 100 may further include an insulating layer 147 and a metal layer 149 sequentially stacked upward, disposed between the drain region 143 and the gate electrode 141, and a portion of the insulating layer 147 and a portion of the metal layer 149 laterally extend onto the gate electrode 141, the portion of the insulating layer 147 and the portion of the metal layer 149 together with a portion of the gate electrode 141 constituting a metal-insulating-polysilicon capacitance structure when the gate electrode 141 is made of polysilicon. The stacked insulating layer 147 and metal layer 149 may be used as field plates to regulate the electric field distribution in the first well region 111.
Fig. 2 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention. The semiconductor device 100 of fig. 2 differs from the semiconductor device 100 of fig. 1 in that the bottom surface of the second well region 113 of the semiconductor device 100 of fig. 2 is lower than the bottom surface of the first well region 111, and the bottom surface of the second well region 113 is in contact with the top surface of the second buried layer 109, the second well region 113 being part between the first well region 111 and the second buried layer 109, and not being separated by the second epitaxial layer 105 between the second well region 113 and the second buried layer 109. In this embodiment, the first epitaxial layer 103 and the second epitaxial layer 105 are each a semiconductor epitaxial layer having the first or second conductivity type, such as an N-type silicon epitaxial layer (N-epi layer) or a P-type silicon epitaxial layer (P-epi layer). For example, when the first epitaxial layer 103 is a semiconductor epitaxial layer of a first conductivity type (N-type silicon epitaxial layer), the second epitaxial layer 105 is a semiconductor epitaxial layer of a second conductivity type (P-type silicon epitaxial layer), and when the first epitaxial layer 103 is a semiconductor epitaxial layer of a second conductivity type (P-type silicon epitaxial layer), the second epitaxial layer 105 is a semiconductor epitaxial layer of a second conductivity type (P-type silicon epitaxial layer) or a semiconductor epitaxial layer of a first conductivity type (N-type silicon epitaxial layer). Details of other components of the semiconductor device 100 of fig. 2 may be referred to the above description of the semiconductor device 100 of fig. 1, and will not be repeated here.
Fig. 3 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention. The semiconductor device 100 of fig. 3 differs from the semiconductor device 100 of fig. 1 in that the deep trench isolation structure 120 of the semiconductor device 100 of fig. 3 includes a trench isolation portion 123, a liner 125, and a dielectric isolation portion 129, wherein the liner 125 wraps around the sidewall and the bottom surface of the trench isolation portion 123, the dielectric isolation portion 129 is disposed directly above the trench isolation portion 123 and the liner 125, and the bottom surface of the dielectric isolation portion 129 contacts the top surface of the trench isolation portion 123 and the top surface of the liner 125. The material of the trench isolation 123 comprises a semiconductor material, such as polysilicon. The material of the liner 125 is, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination of the foregoing. The material of the dielectric isolation portion 129 includes a dielectric material, such as silicon oxide or other suitable dielectric material, and the dielectric isolation portion 129 may be a Shallow Trench Isolation (STI) or a field oxide layer, and the dielectric isolation portion 129 may be formed by a process of forming other isolation regions, such as forming the first isolation region 131, the second isolation region 132, and the third isolation region 133. In one embodiment, as shown in fig. 3, dielectric isolation portion 129 extends downward from the top surface of second epitaxial layer 105 to a depth of second epitaxial layer 105, and trench isolation portion 123 extends downward from the depth of second epitaxial layer 105, through first epitaxial layer 103, second buried layer 109, and first buried layer 107 to a depth of semiconductor substrate 101. In some embodiments, the depth H of the deep trench isolation structure 120 is 1.5 times to 2.5 times the total thickness T of the first epitaxial layer 103 and the second epitaxial layer 105, which may be greater than or equal to 10 micrometers (μm), but is not limited thereto. According to the embodiment of the invention, the deep trench isolation structure 120 can provide a good isolation effect for the semiconductor device 100 to reduce the substrate leakage current. Details of other components of the semiconductor device 100 of fig. 3 may be referred to the above description of the semiconductor device 100 of fig. 1, and will not be repeated here.
Fig. 4, 5, 6, 7, 8 and 9 are schematic cross-sectional views illustrating an intermediate stage of a method of manufacturing a semiconductor device according to an embodiment of the invention. Referring to fig. 4, first, a semiconductor substrate 101 is provided, and then a patterned photoresist layer 161 is formed on the semiconductor substrate 101, an ion implantation process is performed on the semiconductor substrate 101 through an opening of the patterned photoresist layer 161, and ions of a first conductivity type (N-type ions), such As phosphorus (P), arsenic (As), or antimony (Sb), are implanted into the semiconductor substrate 101 to form a first buried layer 107 having the first conductivity type within the semiconductor substrate 101. In some embodiments, the doping concentration of the first buried layer 107 is about 1E13 to 1E15 ions/cm 3 Or about 5E13 to 5E14 ions/cm 3 . At this stage, the first buried layer 107 has a first thickness T1. Next, in step S201, the patterned photoresist layer 161 is removed, and then the first epitaxial layer 103 is formed on the semiconductor substrate 101 and the first buried layer 107 using an epitaxial growth process, and in the epitaxial growth process, ion doping of the first or second conductivity type (P-type ion), such as boron (B), may be performed on the first epitaxial layer 103, so that the first epitaxial layer 103 has the first or second conductivity type. In some embodiments, the thickness of the first epitaxial layer 103 may be equal to or greater than about 4.5 micrometers (μm), but is not limited thereto. Meanwhile, due to the temperature of the epitaxial growth process, ions of the first buried layer 107 thermally diffuse into the first epitaxial layer 103, so that the first buried layer 107 is formed in the semiconductor substrate 101 and the first epitaxial layer 103. After step S201, the first buried layer 107 has a second thickness T2, and the second thickness T2 is greater than the first thickness T1.
Continuing with fig. 4, a patterned photoresist layer 163 is formed on the first epitaxial layer 103, an ion implantation process is performed on the first epitaxial layer 103 through the opening of the patterned photoresist layer 163, and ions of the first conductivity type (N-type ions), such As phosphorus (P), arsenic (As) or antimony (Sb), are implanted into the first epitaxial layer 103 to form a first epitaxial layerA second buried layer 109 having the first conductivity type is formed within layer 103. In some embodiments, the second buried layer 109 has a doping concentration of about 1E11 to 1E13 ions/cm 3 Or about 5E11 to 5E12 ions/cm 3 So that the doping concentration of the second buried layer 109 is lower than the doping concentration of the first buried layer 107. In other embodiments, the doping concentrations of the first buried layer 107 and the second buried layer 109 may each be about 1E13 ions/cm 3 The doping concentration of the second buried layer 109 is made equal to the doping concentration of the first buried layer 107. After step S203, the second buried layer 109 has a third thickness T3.
Next, referring to fig. 5, step S205 is performed to form a second epitaxial layer 105 on the first epitaxial layer 103 and the second buried layer 109 using an epitaxial growth process, and in the epitaxial growth process, ion doping of a second conductivity type (P-type ion), such as boron (B), may be performed on the second epitaxial layer 105, so that the second epitaxial layer 105 has the second conductivity type. In other embodiments, the second epitaxial layer 105 may be doped with ions of the first conductivity type (N-type ions) such that the second epitaxial layer 105 has the first conductivity type. In some embodiments, the thickness of the second epitaxial layer 105 may be equal to or greater than about 4.5 micrometers (μm), but is not limited thereto. Meanwhile, due to the temperature of the epitaxial growth process, ions of the second buried layer 109 thermally diffuse into the second epitaxial layer 105, so that the second buried layer 109 is formed in the first epitaxial layer 103 and the second epitaxial layer 105, and ions of the first buried layer 107 also thermally diffuse up and down into the first epitaxial layer 103 and the semiconductor substrate 101. After step S205, the second buried layer 109 has a fourth thickness T4, the first buried layer 107 has a fifth thickness T5, and the fourth thickness T4 is greater than the third thickness T3, and the fifth thickness T5 is greater than the second thickness T2. In some embodiments, the fifth thickness T5 of the first buried layer 107 is about 6 micrometers (μm), the fourth thickness T4 of the second buried layer 109 is about 4 micrometers (μm), but is not limited thereto, the fifth thickness T5 of the first buried layer 107 is greater than the fourth thickness T4 of the second buried layer 109. In some embodiments, the total thickness of the fifth thickness T5 of the first buried layer 107 and the fourth thickness T4 of the second buried layer 109 is about 10 micrometers (μm) to 30 micrometers (μm), but is not limited thereto.
Continuing with fig. 5, in step S207, a patterned photoresist layer 165 is formed on the second epitaxial layer 105, and an etching process is performed on the second epitaxial layer 105 through the opening of the patterned photoresist layer 165, so as to form a shallow trench 167 in the second epitaxial layer 105, wherein a bottom surface of the shallow trench 167 is higher than a top surface of the second buried layer 109. Next, step S209 is performed to deposit a first dielectric material layer 171 on the second epitaxial layer 105 through a deposition process after removing the patterned photoresist layer 165, and fill the shallow trench 167, wherein the first dielectric material layer 171 is, for example, a silicon oxide layer. In some embodiments, the deposition process may use a high-density plasma (HDP) Chemical Vapor Deposition (CVD) process that has good gap-filling capability to fill the shallow trench 167.
Thereafter, referring to fig. 6, step S211 is performed to form a hard mask layer 173 on the first dielectric material layer 171 through a deposition process. In some embodiments, the deposition process is a Low Pressure Chemical Vapor Deposition (LPCVD) process using Tetraethoxysilane (TEOS), and the hard mask layer 173 is, for example, a silicon oxide layer. Next, in step S213, a patterned photoresist layer 169 is formed on the hard mask layer 173, and an etching process is performed on the hard mask layer 173 and the first dielectric material layer 171 through the opening of the patterned photoresist layer 169 to form an initial trench 175 of the deep trench in the hard mask layer 173 and the first dielectric material layer 171, wherein the position of the initial trench 175 corresponds to the shallow trench 167, and the bottom surface of the initial trench 175 may be flush with the bottom surface of the shallow trench 167, and the width of the initial trench 175 is smaller than the width of the shallow trench 167, such that the remaining first dielectric material layer 171 in the shallow trench 167 surrounds the initial trench 175. Next, in step S215, an etching process is performed on the second epitaxial layer 105, the second buried layer 109, the first buried layer 107 and the semiconductor substrate 101 through the initial trench 175 to form a deep trench 177, where the deep trench 177 passes through the hard mask layer 173, the first dielectric material layer 171 in the shallow trench 167, the second epitaxial layer 105, the second buried layer 109 and the first buried layer 107, and reaches a depth position of the semiconductor substrate 101, such that a bottom surface of the deep trench 177 is lower than a bottom surface of the first buried layer 107. Thereafter, the patterned photoresist layer 169 is removed to expose the hard mask layer 173.
Next, referring to fig. 7, step S217 is performed to deposit a liner 125 on the top surface of the hard mask layer 173 and the inner sidewalls and bottom surface of the deep trench 177 in a conformal manner, wherein the deposition process may be a Low Pressure Chemical Vapor Deposition (LPCVD) process using Tetraethoxysilane (TEOS) in some embodiments, and the liner 125 is, for example, a silicon oxide layer. A layer of fill material 190 is then deposited over the liner 125 and fills in the deep trenches 177. In some embodiments, the fill material layer 190 is a polysilicon layer, and the fill material layer 190 may be deposited using a Low Pressure Chemical Vapor Deposition (LPCVD) process. Then, in step S219, a Chemical Mechanical Planarization (CMP) process is performed on the filling material layer 190 above the hard mask layer 173 to expose the liner 125, and then an etching back (etching back) process is performed on the filling material layer 190 in the deep trench 177 to form a lower portion 121-1 of the core portion 121 of the deep trench isolation structure 120, and a trench 178 is formed on the lower portion 121-1, where the trench 178 is the remaining portion of the deep trench 177. In some embodiments, the top surface of lower portion 121-1 is higher than the top surface of second buried layer 109 and lower than the bottom surface of shallow trench 167. Thereafter, step S221 is performed to deposit a second dielectric material layer 179 on the liner 125 and fill the trench 178, i.e. the second dielectric material layer 179 fills the remaining portion of the deep trench 177, and the second dielectric material layer 179 is, for example, a silicon oxide layer. In some embodiments, the deposition process may use a High Density Plasma (HDP) Chemical Vapor Deposition (CVD) process that has good gap filling capability to fill the trench 178.
Then, referring to fig. 8, a Chemical Mechanical Planarization (CMP) process is performed to remove the second dielectric material layer 179 and the liner 125 above the hard mask layer 173, exposing the hard mask layer 173, and making the top surface of the second dielectric material layer 179 in the trench 178 flush with the top surface of the hard mask layer 173. Thereafter, in step S225, a patterned photoresist layer 181 is formed on the hard mask layer 173, and an etching process is performed to pattern the hard mask layer 173 and the first dielectric material layer 171 using the patterned photoresist layer 181 as an etching mask, so as to form a protruding portion 183, wherein the protruding portion 183 is located directly above the subsequently formed deep trench isolation structure. Then, in step S227, after removing the patterned photoresist layer 181, a Chemical Mechanical Planarization (CMP) process is performed to remove the protruding portion 183, so as to form the deep trench isolation structure 120. In this embodiment, the deep trench isolation structure 120 comprises a lower portion 121-1 and an upper portion 121-1 of the core, a liner 125, and a periphery 127, wherein the lower portion 121-1 of the core is formed by a portion of the fill material layer 190 filled in the deep trench 177 in steps S217 and S219 of fig. 7, the upper portion 121-2 of the core is formed by a second dielectric material layer 179 filled in the trench 178 (the remainder of the deep trench) in step S221 of fig. 7, the liner 125 is formed by the liner 125 deposited in the deep trench 177 in step S217 of fig. 7, and the liner 125 wraps around the sidewalls and bottom surface of the core, the periphery 127 is formed by the first dielectric material layer 171 filled in the shallow trench 167 in steps S211 and S213 of fig. 6, and the periphery 127 surrounds 125 and the upper portion 121-1 of the liner.
Next, referring to fig. 9, step S229 is performed to form the well regions, the doped regions, the heavily doped contact regions and the isolation regions of the semiconductor device 100, such as the first well region 111, the second well region 113, the third well region 115, the fourth well region 117, the source region 145, the drain region 143, the doped region 112, the heavily doped contact regions 151, 153, 155, 157 and 159, the body region 114, the first isolation region 131, the second isolation region 132, the third isolation region 133 and the fourth isolation region 134 of the semiconductor device 100 in the second epitaxial layer 105, and for brevity, fig. 9 does not depict all the device regions, and details of the device regions may be referred to in the related description of fig. 1. In some embodiments, the well regions, the doped regions, or the heavily doped contact regions having the same conductivity type and the same depth may be formed in the same ion implantation process step, and the isolation regions may be formed in the same etching, deposition, and chemical mechanical planarization process steps, or in the same oxidation process step. Thereafter, step S231 is performed to sequentially and globally deposit a gate dielectric layer 192 and a gate electrode material layer 194 over the second epitaxial layer 105, the deep trench isolation structure 120, the wells, the doped regions, the heavily doped contact regions and the isolation regions, wherein the gate dielectric layer 192 is, for example, a silicon oxide layer, and the gate electrode material layer 194 is, for example, a polysilicon layer. Then, step S233 is performed to pattern the gate electrode material layer 194 by photolithography and etching processes to form the gate electrode 141 on the gate dielectric layer 192. Thereafter, an insulating layer 147 and a metal layer 149 as shown in fig. 1 may be sequentially formed on the first well region 111 and the gate electrode 141, thereby completing the semiconductor device 100.
Fig. 10 is a graph of substrate current versus source voltage for a semiconductor device according to some embodiments of the present invention, where the vertical axis represents substrate current (Isub) in milliamp (mA) and the horizontal axis represents source voltage (Vs) in volts (V). Curve a in fig. 10 is a graph of the substrate current (or referred to as the substrate leakage current) of the semiconductor device after the deep trench isolation structure 120 and the first buried layer 107 in the semiconductor device 100 of fig. 1 are removed versus the source voltage, curve B is a graph of the substrate current of the semiconductor device after the first buried layer 107 in the semiconductor device 100 of fig. 1 is removed versus the source voltage, and curve C is a graph of the substrate current of the semiconductor device 100 of fig. 1 versus the source voltage. As can be seen from comparing the curves a, B and C of fig. 10, the substrate current of the semiconductor device of the curve B can be reduced by about 60% when the source voltage is 1V, compared with the semiconductor device of the curve a including only the second buried layer 109. In addition, the semiconductor device 100 of the curve C including the first buried layer 107, the second buried layer 109 and the deep trench isolation structure 120 may have a substrate current reduced by about 30% at a source voltage of 1V compared to the semiconductor device of the curve B including only the second buried layer 109 and the deep trench isolation structure 120, and the semiconductor device 100 of the curve C may have a substrate current reduced by about 90% at a source voltage of 1V compared to the semiconductor device of the curve a including only the second buried layer 109. In addition, when the source voltage is greater than 0.75V, the substrate current of curve C is lower than those of curves a and B.
It can be seen that the semiconductor device 100 according to the embodiment of the invention can reduce parasitic bipolar transistor characteristics in the semiconductor device by providing the first buried layer 107, the second buried layer 109 and the deep trench isolation structure 120, thereby reducing substrate leakage current and preventing latch-up, achieving isolation effect similar to that of a semiconductor device using a silicon-on-insulator (SOI) substrate, so as to save manufacturing cost of the semiconductor device, and avoid poor heat conduction problem using the SOI substrate. In addition, when the semiconductor device is applied to high operation voltage, the substrate leakage current can be effectively reduced without increasing the size of the semiconductor device, thereby improving the breakdown voltage of the semiconductor device and improving the reliability of the semiconductor device.
The above description is only of the preferred embodiments of the present invention, and all the equivalent changes and modifications according to the claims should be considered as falling within the scope of the present invention.

Claims (20)

1. A semiconductor device, comprising:
a substrate;
a first buried layer having a first conductivity type and disposed in the substrate;
a second buried layer having the first conductivity type and disposed on the first buried layer;
A first well region having the first conductivity type and disposed above the second buried layer;
a second well region having a second conductivity type opposite to the first conductivity type and adjacent to the first well region;
a deep trench isolation structure disposed in the substrate and surrounding the first well region and the second well region, wherein a bottom surface of the deep trench isolation structure is lower than a bottom surface of the first buried layer;
a source region disposed in the second well region;
a drain region disposed in the first well region; and
and a gate electrode disposed on the first well region and the second well region.
2. The semiconductor device according to claim 1, wherein a doping concentration of the second buried layer is equal to or lower than a doping concentration of the first buried layer.
3. The semiconductor device of claim 1, wherein a thickness of the first buried layer is greater than a thickness of the second buried layer.
4. The semiconductor device of claim 1, wherein the deep trench isolation structure extends through the second buried layer and the first buried layer.
5. The semiconductor device of claim 1, further comprising a third well of the first conductivity type surrounding the first well and the second well and between the first well and the deep trench isolation structure, and between the second well and the deep trench isolation structure, wherein a bottom surface of the third well contacts a top surface of the second buried layer and a bottom surface of the third well is lower than a bottom surface of the first well.
6. The semiconductor device of claim 5, wherein the second well region comprises two portions adjacent to two sides of the first well region, respectively, and a bottom surface of the second well region is flush with or lower than a bottom surface of the first well region.
7. The semiconductor device according to claim 1, wherein the substrate comprises:
a semiconductor substrate;
a first epitaxial layer disposed on the semiconductor substrate; and
a second epitaxial layer disposed on the first epitaxial layer,
the first buried layer is arranged in the semiconductor substrate and the first epitaxial layer, and the second buried layer is arranged in the first epitaxial layer and the second epitaxial layer.
8. The semiconductor device according to claim 7, wherein the second epitaxial layer and the first epitaxial layer each have the second conductivity type, or the second epitaxial layer has the second conductivity type, and the first epitaxial layer has the first conductivity type, or the second epitaxial layer has the first conductivity type, and the first epitaxial layer has the second conductivity type.
9. The semiconductor device of claim 7, wherein a depth of the deep trench isolation structure is 1.5 times to 2.5 times a total thickness of the second epitaxial layer and the first epitaxial layer.
10. The semiconductor device of claim 1, wherein the deep trench isolation structure comprises:
a core portion comprising an upper portion and a lower portion, wherein the upper portion comprises a dielectric material and the lower portion comprises a polysilicon;
a liner surrounding the core; and
a peripheral portion surrounding the liner and the upper portion.
11. The semiconductor device of claim 1, wherein the deep trench isolation structure comprises:
a trench isolation portion;
a liner surrounding the trench isolation; and
a dielectric isolation part arranged right above the trench isolation part,
wherein a bottom surface of the dielectric isolation portion contacts a top surface of the trench isolation portion, and the trench isolation portion comprises a polysilicon.
12. A method for manufacturing a semiconductor device, comprising:
providing a substrate;
forming a first buried layer in the substrate, wherein the first buried layer has a first conductivity type;
Forming a second buried layer on the first buried layer, the second buried layer having the first conductivity type;
forming a first well region over the second buried layer, the first well region having the first conductivity type;
forming a second well region adjacent to the first well region, the second well region having a second conductivity type opposite to the first conductivity type;
forming a deep trench isolation structure in the substrate and surrounding the first well region and the second well region, wherein the bottom surface of the deep trench isolation structure is lower than the bottom surface of the first buried layer;
forming a source region in the second well region;
forming a drain region in the first well region; and
a gate electrode is formed over the first well region and the second well region.
13. The method for manufacturing a semiconductor device according to claim 12, wherein a doping concentration of the second buried layer is equal to or lower than a doping concentration of the first buried layer.
14. The method for manufacturing a semiconductor device according to claim 12, wherein a thickness of the first buried layer is larger than a thickness of the second buried layer.
15. The method for manufacturing a semiconductor device according to claim 12, wherein providing the substrate comprises:
Providing a semiconductor substrate;
growing a first epitaxial layer on the semiconductor substrate; and
growing a second epitaxial layer on the first epitaxial layer,
wherein the first buried layer is formed within the semiconductor substrate and the first epitaxial layer, and the second buried layer is formed within the first epitaxial layer and the second epitaxial layer.
16. The method for manufacturing a semiconductor device according to claim 15, wherein the second epitaxial layer and the first epitaxial layer each have the second conductivity type, or the second epitaxial layer has the second conductivity type, and the first epitaxial layer has the first conductivity type, or the second epitaxial layer has the first conductivity type, and the first epitaxial layer has the second conductivity type.
17. The method of manufacturing a semiconductor device of claim 15, further comprising forming a third well region surrounding the first well region and the second well region, the third well region having the first conductivity type and being located between the first well region and the deep trench isolation structure and between the second well region and the deep trench isolation structure, wherein a bottom surface of the third well region contacts a top surface of the second buried layer and a bottom surface of the third well region is lower than a bottom surface of the first well region.
18. The method of manufacturing a semiconductor device of claim 15, wherein forming the deep trench isolation structure comprises:
forming a shallow trench in the second epitaxial layer;
depositing a first dielectric material layer on the second epitaxial layer and filling the shallow trench;
forming a deep trench penetrating through the first dielectric material layer, the second epitaxial layer, the second buried layer and the first buried layer in the shallow trench into the semiconductor substrate;
forming a liner on the inner sidewall and the bottom surface of the deep trench and over the first dielectric material layer;
forming a filling material layer on the lining layer and filling the deep trench;
etching back the filling material layer in the deep trench to form a lower portion of a core portion; and
forming a second dielectric material layer on the liner layer and filling the remaining portion of the deep trench to form an upper portion of the core,
wherein the first layer of dielectric material remaining within the shallow trench forms a periphery around the liner and the upper portion.
19. The method of manufacturing a semiconductor device of claim 18, wherein forming the deep trench isolation structure further comprises:
Depositing a hard shielding layer on the first dielectric material layer;
forming a patterned mask over the hard mask layer;
etching the hard mask layer and the first dielectric material layer through an opening of the patterned mask using an etching process to form an initial trench of the deep trench;
performing a first chemical mechanical planarization process to remove the filling material layer on the liner layer before etching back the filling material layer in the deep trench;
performing a second chemical mechanical planarization process to remove the liner layer and the second dielectric layer on the hard mask layer;
patterning the first dielectric layer and the hard mask layer to form a protruding portion on the deep trench isolation structure; and
a third chemical mechanical planarization process is performed to remove the protruding portion.
20. The method for manufacturing a semiconductor device according to claim 18, wherein the filler material layer comprises polysilicon.
CN202210602075.1A 2022-05-30 2022-05-30 Semiconductor device and method for manufacturing the same Pending CN117198981A (en)

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