CN113745109A - FinFET manufacturing method - Google Patents

FinFET manufacturing method Download PDF

Info

Publication number
CN113745109A
CN113745109A CN202010464454.XA CN202010464454A CN113745109A CN 113745109 A CN113745109 A CN 113745109A CN 202010464454 A CN202010464454 A CN 202010464454A CN 113745109 A CN113745109 A CN 113745109A
Authority
CN
China
Prior art keywords
fins
oxide layer
finfet
fin
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010464454.XA
Other languages
Chinese (zh)
Inventor
张峰溢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong Hanqi Industrial Technology Research And Development Co ltd
Original Assignee
Guangdong Hanqi Industrial Technology Research And Development Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangdong Hanqi Industrial Technology Research And Development Co ltd filed Critical Guangdong Hanqi Industrial Technology Research And Development Co ltd
Priority to CN202010464454.XA priority Critical patent/CN113745109A/en
Publication of CN113745109A publication Critical patent/CN113745109A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention discloses a FinFET manufacturing method, which comprises the following steps: forming a structure comprising a substrate, a first oxide layer, a hard mask layer, a second oxide layer and a plurality of spacers by adopting a multiple patterning mask process; etching the patterned structure, forming a plurality of fins at the parts corresponding to the spacers, and forming a first oxide layer, a hard mask layer and a second oxide layer above each fin; forming a shallow trench isolation region between two adjacent fins, wherein the height of the shallow trench isolation region is the same as that of the fins; carrying out a recess treatment on each shallow trench isolation region to form a groove between two adjacent fins so as to expose the upper parts of the fins; depositing an ALD thin film on the surface of each fin and each groove; and cutting the plurality of fins and grooves on which the ALD thin films are deposited. Thus, it can be seen that the fin of the FinFET structure made by the method of the present invention has no tilt, symmetric groove edges, the same groove depth and the same fin feature size.

Description

FinFET manufacturing method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a FinFET manufacturing method.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. As the transistor is currently widely used as the most basic semiconductor device, as the element density and the integration degree of the semiconductor device are improved, the gate size of the planar transistor is shorter and shorter, and the conventional planar transistor has weak control capability on channel current, generates a short channel effect, generates leakage current, and finally affects the electrical performance of the semiconductor device.
A Fin Field effect transistor (FinFET) is a new type of mosfet, which includes narrow and isolated silicon strips (i.e., vertical channel structures, also called fins) with gate structures on both sides of the Fin. The FinFET structure makes the device smaller and has higher performance.
The existing FinFET manufacturing method comprises the following flows: forming a structure comprising a substrate, a first oxide layer, a mask layer, a second oxide layer and a spacer by adopting a multiple patterning mask process; etching the patterned structure to form a fin; preliminarily cutting the structure with the fins; forming a shallow trench isolation region on the cut structure; and forming a groove in the shallow channel isolation region.
FIG. 1 is a cross-sectional view of a prior art FinFET structure formed by a fabrication method; as shown in fig. 1, the FinFET manufactured by the above method has the disadvantages of fin tilt, asymmetric groove edges, different fin recess depths, and non-uniform fin feature sizes.
Disclosure of Invention
The invention aims to provide a FinFET manufacturing method.
The technical scheme adopted by the invention is as follows: a FinFET fabrication method is constructed, comprising the steps of:
forming a structure comprising a substrate, a first oxide layer, a hard mask layer, a second oxide layer and a plurality of spacers by adopting a multiple patterning mask process;
etching the patterned structure, forming a plurality of fins at the parts corresponding to the positions of the spacers, and forming the first oxide layer, the hard mask layer and the second oxide layer above each fin;
forming a shallow trench isolation region between two adjacent fins, wherein the height of the shallow trench isolation region is the same as that of the fins;
carrying out recess treatment on each shallow trench isolation region to form a groove between two adjacent fins so as to expose the upper parts of the fins;
depositing an ALD thin film on the surface of each fin and each groove;
and cutting the plurality of fins and grooves on which the ALD thin film is deposited.
In the FinFET manufacturing method provided by the invention, the ALD thin film is one of SiN, SiOCN, TiN and TaN.
In the FinFET manufacturing method provided by the invention, the substrate is Si, and the hard mask layer is SiN.
In the FinFET manufacturing method provided in the present invention, the step of forming a shallow trench isolation region between two adjacent fins includes:
uniformly covering a liner oxide layer between every two adjacent fins and above the fins;
and carrying out chemical mechanical polishing treatment to enable the upper surface of the liner oxide layer and the top of the fin to be flat, so that the first oxide layer, the hard mask layer and the second oxide layer are removed.
In the FinFET manufacturing method provided by the invention, a liner oxide layer is uniformly covered between two adjacent fins and above the plurality of fins through one of ISSG, ALD-Ox and FCVD.
In the FinFET manufacturing method provided by the invention, the step of cutting the plurality of fins and grooves deposited with the ALD thin film comprises the following steps:
removing the dummy fins and the corresponding grooves at the edge part;
depositing an oxide layer between and above the remaining fins and grooves;
performing oxygen etch-back treatment to expose the ALD thin film;
removing the ALD thin film.
In the FinFET fabrication method provided by the present invention, the ALD thin film is removed by one of plasma isotropic etching, chemical isotropic etching or wet etching.
There is also provided in accordance with another aspect of the present invention a FinFET fabricated in accordance with the method described above.
In the FinFET provided by the invention, different gate bottom structures are formed by controlling the depth of oxygen etch-back treatment.
The FinFET manufacturing method has the following beneficial effects: the FinFET manufacturing method provided by the invention can avoid the generation of inclined fins by carrying out shallow trench isolation treatment on all the fins; by carrying out recess treatment on the shallow trench isolation regions between the fins, the problems of different fin recess depths and uneven fin characteristic sizes in the finally formed FinFET structure can be avoided; protecting the groove depth in a subsequent cutting process by depositing an ALD thin film; the FinFET structure has no inclined fin, symmetrical notch edge, and the same notch depth and fin characteristic size.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts:
FIG. 1 is a cross-sectional view of a prior art FinFET structure formed by a fabrication method;
FIG. 2 is a flow chart of a method of fabricating a FinFET in accordance with an embodiment of the present invention;
fig. 3-12 are schematic device structures during a method of fabricating a FinFET in accordance with an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
In order to provide a thorough understanding of the present invention, detailed steps will be set forth in the following description in order to explain the FinFET fabrication method of the present invention. It will be apparent that the invention may be practiced without limitation to specific details that are within the skill of one of ordinary skill in the semiconductor arts. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
In order to solve the technical problems of the defects of the FinFET manufactured by the existing method, such as the inclination of the fin, the asymmetry of the edge of the groove, the different depth of the sunken part of the fin and the non-uniform characteristic dimension of the fin, the invention provides a FinFET manufacturing method, as shown in FIG. 2, the manufacturing method provided by the invention comprises the following steps:
step S1, forming a structure including a substrate, a first oxide layer, a hard mask layer, a second oxide layer and a plurality of spacers by using a multiple patterning mask process;
step S2, etching the patterned structure, forming a plurality of fins on portions corresponding to the spacers, and forming the first oxide layer, the hard mask layer, and the second oxide layer over each of the fins;
step S3, forming a shallow trench isolation region between two adjacent fins, wherein the height of the shallow trench isolation region is the same as that of the fins;
step S4, performing a recess process on each shallow trench isolation region to form a groove between two adjacent fins, so as to expose the upper portions of the fins;
step S5, depositing an ALD thin film on the surface of each fin and each groove;
and step S6, performing cutting processing (Fin cut) on the plurality of fins and grooves on which the ALD thin film is deposited.
Specifically, as shown in fig. 3 and 4, in step S1, a core component is first formed by using a multiple patterning mask process, where the core component includes the substrate 10, the first oxide layer 20, the hard mask layer 30, the second oxide layer 40, and the plurality of features 50; then, the plurality of features 50 are replaced with a plurality of spacers 60 over the second oxide layer 40, and the formation locations of subsequent fins are determined by the spacers 60. The substrate 10 may be formed of undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), or the like. By way of example, in the present embodiment, the substrate 10 and features 50 are formed from a single crystal silicon material, and the hard mask layer 30 and spacers 60 are formed from a SiN material. It will be appreciated by those skilled in the art that the formation of the oxide layer, the hard mask layer and the spacers on the substrate may be performed according to conventional processes and will not be described in detail. Further, the multiple patterning mask process comprises: a Self-aligned Double patterning (SADP) process, or a Self-aligned quad patterning (SAQP) process.
Specifically, as shown in fig. 5, in step S2, the patterned structure is sequentially etched to form a plurality of fins 70 at portions corresponding to the spacers 60, and the first oxide layer 20, the hard mask layer 30 and the second oxide layer 40 are formed over each of the fins 70. The etching can also be carried out by conventional technical means by those skilled in the art, and will not be described herein.
Specifically, as shown in fig. 6, in step S3, a plurality of shallow trench isolation regions 80 having the same height as the fin height are formed between two adjacent fins 70. Firstly, a liner oxide layer is uniformly covered between two adjacent fins 70 and above the fins, and can be implemented by one of an In-Situ Vapor Generation (ISSG) process, an Atomic Layer Deposition (ALD) process, and a Fluid Chemical Vapor Deposition (FCVD) process; and then, carrying out chemical mechanical polishing treatment to flatten the upper surface of the liner oxide layer and the top of the fin so as to remove the first oxide layer, the hard mask layer and the second oxide layer. In the invention, the generation of inclined fins can be avoided by carrying out shallow trench isolation treatment on all the fins.
Specifically, as shown in fig. 7, in step S4, each of the shallow trench isolation regions 80 is recessed to form a groove 90 between two adjacent fins, so as to expose the upper portion of the fin. In the invention, by carrying out the recess treatment on the shallow trench isolation region between the fins, the problems of different fin recess depths and uneven fin characteristic sizes in the finally formed FinFET structure can be avoided.
Specifically, as shown in fig. 8, in step S5, an ALD thin film 100, which is one of SiN, SiOCN, TiN, TaN, is deposited on the surface of each fin 70 and each groove 90 to protect the groove depth in the subsequent cutting process.
Specifically, as shown in fig. 9 to 12, in step S6, a cutting process is performed on the plurality of fins and grooves on which the ALD thin film is deposited to remove dummy fins at the edges. As shown in fig. 9, the dummy fins and the corresponding grooves of the edge portion are removed first; as shown in fig. 10, an oxide layer 110 is deposited between and over the remaining fins and grooves; as shown in fig. 11, performing an oxygen etch-back process to expose the ALD film, which may be removed by one of plasma isotropic etching, chemical isotropic etching or wet etching, forming different gate bottom structures by controlling the depth of the oxygen etch-back process; the ALD thin film is removed as shown in fig. 12.
Fig. 12 is a cross-sectional view of a resulting FinFET structure in accordance with the present invention. Thus, it can be seen that the fin of the FinFET structure made by the method of the present invention has no tilt, symmetric groove edges, the same groove depth and the same fin feature size.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (9)

1. A method of FinFET fabrication, comprising:
forming a structure comprising a substrate, a first oxide layer, a hard mask layer, a second oxide layer and a plurality of spacers by adopting a multiple patterning mask process;
etching the patterned structure, forming a plurality of fins at the parts corresponding to the positions of the spacers, and forming the first oxide layer, the hard mask layer and the second oxide layer above each fin;
forming a shallow trench isolation region between two adjacent fins, wherein the height of the shallow trench isolation region is the same as that of the fins;
carrying out recess treatment on each shallow trench isolation region to form a groove between two adjacent fins so as to expose the upper parts of the fins;
depositing an ALD thin film on the surface of each fin and each groove;
and cutting the plurality of fins and grooves on which the ALD thin film is deposited.
2. The FinFET manufacturing method of claim 1, wherein the ALD thin film is one of SiN, SiOCN, TiN, TaN.
3. The method of claim 1, wherein the substrate is Si and the hard mask layer is SiN.
4. The method of manufacturing a FinFET in claim 1, wherein said step of forming shallow trench isolation regions between two adjacent fins comprises:
uniformly covering a liner oxide layer between every two adjacent fins and above the fins;
and carrying out chemical mechanical polishing treatment to enable the upper surface of the liner oxide layer and the top of the fin to be flat, so that the first oxide layer, the hard mask layer and the second oxide layer are removed.
5. The method of claim 4, wherein a liner oxide layer is uniformly coated between adjacent two of the fins and over the plurality of fins by one of ISSG, ALD-Ox, FCVD.
6. The method of FinFET fabrication of claim 1, wherein the step of cutting the plurality of fins and grooves with the ALD thin film deposited thereon comprises:
removing the dummy fins and the corresponding grooves at the edge part;
depositing an oxide layer between and above the remaining fins and grooves;
performing oxygen etch-back treatment to expose the ALD thin film;
removing the ALD thin film.
7. The FinFET fabrication method of claim 6, wherein the ALD thin film is removed by one of plasma isotropic etching, chemical isotropic etching, or wet etching.
8. A FinFET formed in accordance with the FinFET fabrication method of claims 1-7.
9. The FinFET of claim 8, wherein different gate bottom structures are formed by controlling oxygen etch back process depth.
CN202010464454.XA 2020-05-27 2020-05-27 FinFET manufacturing method Pending CN113745109A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010464454.XA CN113745109A (en) 2020-05-27 2020-05-27 FinFET manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010464454.XA CN113745109A (en) 2020-05-27 2020-05-27 FinFET manufacturing method

Publications (1)

Publication Number Publication Date
CN113745109A true CN113745109A (en) 2021-12-03

Family

ID=78723585

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010464454.XA Pending CN113745109A (en) 2020-05-27 2020-05-27 FinFET manufacturing method

Country Status (1)

Country Link
CN (1) CN113745109A (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107134433A (en) * 2016-02-26 2017-09-05 台湾积体电路制造股份有限公司 The method for making semiconductor device
CN107887439A (en) * 2016-09-29 2018-04-06 台湾积体电路制造股份有限公司 The forming method of fin-shaped field-effect transistor structure
CN108122840A (en) * 2016-11-28 2018-06-05 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and preparation method, electronic device
US20180174854A1 (en) * 2016-12-16 2018-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-Like Field Effect Transistor Patterning Methods for Increasing Process Margins
CN108807534A (en) * 2017-05-03 2018-11-13 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN110047755A (en) * 2018-01-17 2019-07-23 中芯国际集成电路制造(上海)有限公司 A kind of manufacturing method of semiconductor devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107134433A (en) * 2016-02-26 2017-09-05 台湾积体电路制造股份有限公司 The method for making semiconductor device
CN107887439A (en) * 2016-09-29 2018-04-06 台湾积体电路制造股份有限公司 The forming method of fin-shaped field-effect transistor structure
CN108122840A (en) * 2016-11-28 2018-06-05 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and preparation method, electronic device
US20180174854A1 (en) * 2016-12-16 2018-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-Like Field Effect Transistor Patterning Methods for Increasing Process Margins
CN108807534A (en) * 2017-05-03 2018-11-13 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN110047755A (en) * 2018-01-17 2019-07-23 中芯国际集成电路制造(上海)有限公司 A kind of manufacturing method of semiconductor devices

Similar Documents

Publication Publication Date Title
TWI691076B (en) Semiconductor structure and method of forming the same
TW201806157A (en) Semiconductor structure and method of forming the same
US11049973B2 (en) Semiconductor device and fabrication method thereof
KR100498475B1 (en) Mosfet structure and method of fabricating the same
TW201639014A (en) Semiconductor device and method of fabricating the same
US9111871B2 (en) Semiconductor structure and method for forming the same
JPH11111981A (en) Semiconductor device and its manufacture
US11456216B2 (en) Fabrication method of semiconductor structure
KR20050078729A (en) Semiconductor device and method of manufacturing for the same
JP2007103455A (en) Semiconductor device having fin structure and its manufacturing method
US20200251565A1 (en) Gate structure of split-gate metal oxide semiconductor field effect transistor and manufacturing method thereof
US11456367B2 (en) Trench gate structure and method of forming a trench gate structure
US11742414B2 (en) Semiconductor device with fins
KR102014437B1 (en) Semiconductor appratus having multi-type wall oxides and manufacturing method of the same
US10522619B2 (en) Three-dimensional transistor
CN109698119B (en) Manufacturing method of semiconductor device and semiconductor device
US11682725B2 (en) Semiconductor device with isolation layer
CN115312374A (en) Preparation method of groove type device wafer and groove type device wafer
CN110867377B (en) Planarization method of virtual gate
CN113745109A (en) FinFET manufacturing method
CN112687622A (en) Single diffusion region cutting structure of fin field effect transistor and forming method thereof
JP2005019984A (en) Ultra-short channel field effect transistor and method of fabricating the same
CN108155100B (en) Method for forming semiconductor device
US20240128357A1 (en) 3d-transistor structure with precise geometries
KR100611083B1 (en) Mos transistor and method for manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination