CN113743042B - Coordinate rotation digital computing method and system based on high-level comprehensive tool - Google Patents
Coordinate rotation digital computing method and system based on high-level comprehensive tool Download PDFInfo
- Publication number
- CN113743042B CN113743042B CN202110846817.0A CN202110846817A CN113743042B CN 113743042 B CN113743042 B CN 113743042B CN 202110846817 A CN202110846817 A CN 202110846817A CN 113743042 B CN113743042 B CN 113743042B
- Authority
- CN
- China
- Prior art keywords
- rotation digital
- coordinate rotation
- level
- llvm
- digital computing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004364 calculation method Methods 0.000 title claims abstract description 58
- 230000006870 function Effects 0.000 claims abstract description 35
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 238000003786 synthesis reaction Methods 0.000 claims description 14
- 230000009466 transformation Effects 0.000 claims description 13
- 238000005457 optimization Methods 0.000 claims description 12
- 230000005540 biological transmission Effects 0.000 claims description 11
- 230000004048 modification Effects 0.000 claims description 8
- 238000012986 modification Methods 0.000 claims description 8
- 238000004088 simulation Methods 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 230000003993 interaction Effects 0.000 claims description 5
- 238000010276 construction Methods 0.000 claims description 3
- 230000009191 jumping Effects 0.000 claims description 3
- 238000004422 calculation algorithm Methods 0.000 abstract description 13
- 230000007547 defect Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000000844 transformation Methods 0.000 description 2
- 241001197925 Theila Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000013598 vector Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Data Mining & Analysis (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Mathematical Physics (AREA)
- Algebra (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Computational Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Databases & Information Systems (AREA)
- Software Systems (AREA)
- Devices For Executing Special Programs (AREA)
- Image Processing (AREA)
Abstract
The invention provides a coordinate rotation digital computing method and a system based on a high-level comprehensive tool, which are used for overcoming the defect that a cordic algorithm cannot be implemented on an FPGA lacking an FPU module, and comprise the following steps: constructing a coordinate rotation digital computing model based on long integer operation by adopting a high-level language; converting the coordinate rotation digital computing model by adopting a high-level comprehensive tool; and simulating the converted coordinate rotation digital calculation model through the FPGA to finish the coordinate rotation digital calculation. Before the coordinate rotation digital calculation model is configured to the FPGA, the operation of a triangular function, a hyperbola, an index and a logarithm is constructed into the coordinate rotation digital calculation model based on long integer operation, and the coordinate rotation digital calculation model is configured to the FPGA through a high-level comprehensive tool, so that floating point operation can be performed on the FPGA without the FPU module.
Description
Technical Field
The invention relates to the technical field of digital processing, in particular to a coordinate rotation digital computing method and system based on a high-level comprehensive tool.
Background
The cordic algorithm (Coordinate Rotation Digital Computer, coordinate rotation digital computing method) is mainly applied to the computation of trigonometric functions, hyperbolas, exponentials and logarithms. The cordic algorithm replaces multiplication operations by basic addition and shift calculations, so that rotation and orientation calculations of vectors do not require exponentiation, evolution, multiplication, etc.
In the cordic algorithm, floating Point operation is realized on hardware, which has been realized by using a FPU (floating Point Unit) on an FPGA (Field Programmable Gate Array ), whereas in the FPGA without a FPU module, floating Point operation cannot be performed.
Disclosure of Invention
The invention provides a coordinate rotation digital computing method and system based on a high-level comprehensive tool, which are used for overcoming the defect that a cordic algorithm cannot be implemented on an FPGA lacking an FPU module in the prior art.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a coordinate rotation digital computing method based on a high-level comprehensive tool comprises the following steps:
s1: constructing a coordinate rotation digital computing model based on long integer operation by adopting high-level language, wherein the coordinate rotation digital computing model comprises operation operations on trigonometric functions, hyperbolas, exponents and logarithms;
s2: converting the coordinate rotation digital computing model by adopting a high-level comprehensive tool;
s3: and simulating the converted coordinate rotation digital calculation model through the FPGA to finish the coordinate rotation digital calculation.
Preferably, the step of constructing the coordinate rotation digital computing model based on the integer operation includes:
1) Converting the floating point number into a 64-bit integer number;
2) Converting floating point operations into long integer operations;
3) Setting a trigonometric function type and output precision thereof;
4) And modifying and outputting the target trigonometric function type through the modification enumeration type, and adjusting the output precision through the modification iteration times.
Preferably, the step of converting the coordinate rotation digital computing model by using a high-level synthesis tool includes: converting a coordinate rotation digital computing model constructed by a high-level language into an LLVM-IR intermediate expression file, configuring the LLVM-IR intermediate expression file through a Lua script file, and converting the LLVM-IR intermediate expression file into a coordinate rotation digital computing model expressed by a low-level language.
Preferably, the step of configuring the LLVM-IR intermediate expression file through the Lua script file includes:
performing high-level general optimization on the LLVM-IR intermediate expression file;
and performing high-level comprehensive transformation on the optimized LLVM-IR intermediate expression file, and converting the LLVM-IR intermediate expression file into a coordinate rotation digital computing model expressed by a register transmission level code language based on a behavior level time sequence constraint.
Preferably, the step of simulating the transformed coordinate rotation digital computing model through the FPGA includes:
generating a corresponding bit stream file according to the converted coordinate rotation digital calculation model, and downloading and configuring the bit stream file into the FPGA;
performing online debugging on the FPGA, comparing the debugging result with the cordic core, and outputting the debugging result as a coordinate rotation digital calculation result when the debugging result is matched with the cordic core data; otherwise, the step S1 is executed in a jumping mode.
Furthermore, the invention also provides a coordinate rotation digital computing system based on the high-level comprehensive tool, which comprises:
the model construction module is used for constructing a coordinate rotation digital calculation model based on long integer operation by adopting a high-level language;
the high-level comprehensive module is used for converting the coordinate rotation digital computing model by adopting a high-level comprehensive tool;
and the simulation module is used for performing simulation calculation on the converted coordinate rotation digital calculation model and outputting a coordinate rotation digital calculation result.
Preferably, the model building module includes:
the floating point operation conversion unit is used for converting the floating point number into a 64-bit integer number and converting the floating point operation into the integer operation;
the trigonometric function setting unit is used for setting a trigonometric function type; the trigonometric function type comprises an SIN function, a COS function, a TAN function, a COT function, a CSC function and a SEC function;
and the precision adjusting unit is used for modifying the iteration times to adjust the precision of the output result.
As a preferred scheme, the system further comprises a man-machine interaction module, wherein the man-machine interaction module comprises a SIN selection key, a COS selection key, a TAN selection key, a COT selection key, a CSC selection key and a SEC selection key, which are respectively used for selecting the set trigonometric function type and a target precision input unit, and is used for modifying the precision of an output result.
Preferably, the high-level synthesis module includes:
the LLVM-IR file conversion unit is used for converting a coordinate rotation digital calculation model constructed by high-level language into an LLVM-IR intermediate expression file;
and the configuration unit is used for configuring the LLVM-IR intermediate expression file through the Lua script file and converting the LLVM-IR intermediate expression file into a coordinate rotation digital calculation model expressed through a low-level language.
As a preferred scheme, the configuration unit comprises a high-level general optimization layer, a high-level comprehensive transformation layer, a register transmission level code and a behavior level time sequence constraint generation layer which are sequentially connected, wherein the high-level general optimization layer, the high-level comprehensive transformation layer and the register transmission level code and behavior level time sequence constraint generation layer are respectively used for carrying out high-level general optimization on the LLVM-IR intermediate expression file, carrying out high-level comprehensive transformation on the optimized LLVM-IR intermediate expression file, and converting the optimized LLVM-IR intermediate expression file into a coordinate rotation digital calculation model expressed by a register transmission level code language based on the behavior level time sequence constraint.
Compared with the prior art, the technical scheme of the invention has the beneficial effects that: before the coordinate rotation digital calculation model is configured to the FPGA, the operation of a triangular function, a hyperbola, an index and a logarithm is constructed into the coordinate rotation digital calculation model based on long integer operation, and the coordinate rotation digital calculation model is configured to the FPGA through a high-level comprehensive tool, so that floating point operation can be performed on the FPGA without the FPU module.
Drawings
Fig. 1 is a flowchart of a coordinate rotation digital computing method based on the high-level synthesis tool of embodiment 1.
Fig. 2 is a schematic diagram of a shell script corresponding to a modified cordic algorithm output trigonometric function type sin.
Fig. 3 is a schematic diagram of a shell script corresponding to the number of iterations of the modified cordic algorithm.
Fig. 4 is an architecture diagram of a high-level synthesis tool-based coordinate rotation digital computing system of example 2.
Detailed Description
The drawings are for illustrative purposes only and are not to be construed as limiting the present patent;
it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The technical scheme of the invention is further described below with reference to the accompanying drawings and examples.
Example 1
The present embodiment provides a coordinate rotation digital computing method based on a high-level synthesis tool, as shown in fig. 1, which is a flowchart of the coordinate rotation digital computing method based on the high-level synthesis tool in this embodiment.
The coordinate rotation digital computing method based on the high-level comprehensive tool provided by the embodiment comprises the following steps:
s1: and constructing a coordinate rotation digital computing model based on long integer operation by adopting a high-level language, wherein the coordinate rotation digital computing model comprises operation operations on trigonometric functions, hyperbolas, exponents and logarithms.
The method for constructing the coordinate rotation digital computing model based on the long integer operation comprises the following steps of:
1) Converting the floating point number into a 64-bit integer number;
2) Converting floating point operations into long integer operations;
3) Setting a trigonometric function type and output precision thereof;
4) And modifying and outputting the target trigonometric function type through the modification enumeration type, and adjusting the output precision through the modification iteration times.
S2: and converting the coordinate rotation digital computing model by adopting a high-level comprehensive tool. The method comprises the following specific steps:
converting a coordinate rotation digital computing model constructed by a high-level language into an LLVM-IR intermediate expression file, configuring the LLVM-IR intermediate expression file through a Lua script file, and converting the LLVM-IR intermediate expression file into a coordinate rotation digital computing model expressed by a low-level language.
Wherein, the step of configuring the LLVM-IR intermediate expression file through the Lua script file comprises the following steps:
performing high-level general optimization on the LLVM-IR intermediate expression file;
and performing high-level comprehensive transformation on the optimized LLVM-IR intermediate expression file, and converting the LLVM-IR intermediate expression file into a coordinate rotation digital computing model expressed by a register transmission level code language based on a behavior level time sequence constraint.
S3: and simulating the converted coordinate rotation digital calculation model through the FPGA to finish the coordinate rotation digital calculation. The method comprises the following specific steps:
generating a corresponding bit stream file according to the converted coordinate rotation digital calculation model, and downloading and configuring the bit stream file into the FPGA;
performing online debugging on the FPGA, comparing the debugging result with the cordic core, and outputting the debugging result as a coordinate rotation digital calculation result when the debugging result is matched with the cordic core data; otherwise, the step S1 is executed in a jumping mode.
In the implementation process, a corresponding algorithm is written in a C language through visual studio 2015 for the constructed coordinate rotation digital calculation model, and the correctness of the algorithm function is verified. Specifically, the method adopts the C language to convert the floating point number related in the coordinate rotation digital computing model into a 64-bit long integer number, converts the floating point operation related in the coordinate rotation digital computing model into a long integer operation, realizes the floating point operation through the long integer operation, and judges the type of trigonometric function to be output, and comprises the following six types: sin, cos, tan, cot, csc, sec and the accuracy of its output, and modifying the type of output trigonometric function by modifying the enumeration type, and changing the number of iterations by modifying the number of loops for a loop, thereby affecting the accuracy. In this embodiment, the output parameter type and the iteration number are changed by the shell script, so that the accuracy of the output result is affected. The CORDIC algorithm is an iterative algorithm that approximates a target value, and the more the number of iterations, the higher the accuracy. As shown in fig. 2 and 3, in this embodiment, the shell script corresponding to sin is modified by modifying the cordic algorithm output trigonometric function type, and the shell script corresponding to the cordic algorithm iteration number is modified, and in this embodiment, the iteration number is changed by replacing a for loop.
The coordinate rotation digital computing model passing verification accuracy is converted into Verilog codes by adopting a high-level comprehensive tool. Specifically, a LLVM-IR intermediate expression file is generated by a C language through the front end of SHANG under a Linux system, then the converted LLVM-IR intermediate expression file is configured by the rear end of SHANG under a Windows system through a Lua script file, and finally the LLVM-IR intermediate expression file is converted into a Verilog code.
And finally, simulating the converted coordinate rotation digital calculation model through an FPGA, adopting ILA online debugging of Xilinx Vivado in the embodiment, downloading and configuring a bit stream file generated by RTL codes generated first to the FPGA, carrying out online debugging through the ILA, comparing a debugging result with a cordic core of the Xilinx, and outputting the debugging result as the coordinate rotation digital calculation result when the debugging result is matched with the cordic core data.
In the embodiment, before the coordinate rotation digital computing model is configured to the FPGA, the floating point operation is converted into the long integer operation, and then the coordinate rotation digital computing model is further converted by adopting a high-level comprehensive tool, and the converted coordinate rotation digital computing model is configured to the FPGA, so that the floating point operation is performed on the FPGA without the FPU module.
Example 2
The embodiment provides a coordinate rotation digital computing system based on a high-level comprehensive tool, which is applied to the coordinate rotation digital computing method based on the high-level comprehensive tool provided in embodiment 1. As shown in fig. 4, an architecture diagram of the coordinate rotation digital computing system based on the high-level synthesis tool of the present embodiment is shown.
The coordinate rotation digital computing system based on the high-level comprehensive tool provided in this embodiment includes:
the model construction module 1 is used for constructing a coordinate rotation digital computing model based on long integer operation by adopting a high-level language;
the high-level synthesis module 2 is used for converting the coordinate rotation digital computing model by adopting a high-level synthesis tool;
and the simulation module 3 is used for performing simulation calculation on the converted coordinate rotation digital calculation model and outputting a coordinate rotation digital calculation result.
The model building module 1 in this embodiment includes:
a floating point operation conversion unit 11 for converting a floating point number into a 64-bit integer number and converting a floating point operation into an integer operation;
a trigonometric function setting unit 12 for setting a trigonometric function type; the trigonometric function type comprises an SIN function, a COS function, a TAN function, a COT function, a CSC function and a SEC function;
and the precision adjusting unit 13 is used for adjusting the precision of the output result by modifying the iteration times.
Further, the coordinate rotation digital computing system in this embodiment further includes a man-machine interaction module 4, where the man-machine interaction module 4 includes a SIN selection key, a COS selection key, a TAN selection key, a COT selection key, a CSC selection key, and a SEC selection key, which are respectively used to select a set trigonometric function type, and a target precision input unit, which are used to modify the precision of the output result.
The high-level synthesis module 2 in this embodiment includes:
an LLVM-IR file converting unit 21 for converting a coordinate rotation digital computing model constructed in a high-level language into an LLVM-IR intermediate expression file;
a configuration unit 22, configured to configure the LLVM-IR intermediate expression file by the Lua script file, and convert the LLVM-IR intermediate expression file into a coordinate rotation digital computing model expressed by a low-level language.
Further, the configuration unit 22 in this embodiment includes a high-level general optimization layer (Generic Transformations with Lowlevel information), a high-level comprehensive transformation layer (HLS-specific Transformations), and a register transmission level code and behavior level timing constraint generation layer (RTL Synthesis with Behaviorlevel information) that are sequentially connected, and are respectively configured to perform high-level general optimization on the LLVM-IR intermediate expression file, perform high-level comprehensive transformation on the optimized LLVM-IR intermediate expression file, and convert the high-level general optimization into a coordinate rotation digital calculation model expressed by a register transmission level code language based on the behavior level timing constraint.
The same or similar reference numerals correspond to the same or similar components;
the terms describing the positional relationship in the drawings are merely illustrative, and are not to be construed as limiting the present patent;
it is to be understood that the above examples of the present invention are provided by way of illustration only and not by way of limitation of the embodiments of the present invention. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the invention are desired to be protected by the following claims.
Claims (6)
1. The coordinate rotation digital computing method based on the high-level comprehensive tool is characterized by comprising the following steps of:
s1: constructing a coordinate rotation digital computing model based on long integer operation by adopting a high-level language, wherein the coordinate rotation digital computing model comprises operation operations on trigonometric functions, hyperbolas, exponents and logarithms;
s2: converting the coordinate rotation digital computing model by adopting a high-level comprehensive tool;
s3: simulating the converted coordinate rotation digital calculation model through an FPGA to finish coordinate rotation digital calculation;
the step of converting the coordinate rotation digital computing model by using a high-level synthesis tool comprises the following steps: converting a coordinate rotation digital computing model constructed by a high-level language into an LLVM-IR intermediate expression file, configuring the LLVM-IR intermediate expression file through a Lua script file, and converting the LLVM-IR intermediate expression file into a coordinate rotation digital computing model expressed by a low-level language;
the step of configuring the LLVM-IR intermediate expression file through the Lua script file comprises the following steps:
performing high-level general optimization on the LLVM-IR intermediate expression file;
and performing high-level comprehensive transformation on the optimized LLVM-IR intermediate expression file, and converting the LLVM-IR intermediate expression file into a coordinate rotation digital computing model expressed by a register transmission level code language based on a behavior level time sequence constraint.
2. The coordinate rotation digital computing method according to claim 1, wherein the step of constructing a coordinate rotation digital computing model based on a long integer operation includes:
1) Converting the floating point number into a 64-bit integer number;
2) Converting floating point operations into long integer operations;
3) Setting a trigonometric function type and output precision thereof;
4) And modifying and outputting the target trigonometric function type through the modification enumeration type, and adjusting the output precision through the modification iteration times.
3. The coordinate rotation digital computing method according to claim 1, wherein the step of simulating the converted coordinate rotation digital computing model by an FPGA comprises:
generating a corresponding bit stream file according to the converted coordinate rotation digital calculation model, and downloading and configuring the bit stream file into the FPGA;
performing online debugging on the FPGA, comparing the debugging result with the cordic core, and outputting the debugging result as a coordinate rotation digital calculation result when the debugging result is matched with the cordic core data; otherwise, the step S1 is executed in a jumping mode.
4. A coordinate rotation digital computing system based on a high-level synthesis tool, comprising: the model construction module is used for constructing a coordinate rotation digital calculation model based on long integer operation by adopting a high-level language;
the high-level comprehensive module is used for converting the coordinate rotation digital computing model by adopting a high-level comprehensive tool;
the simulation module is used for performing simulation calculation on the converted coordinate rotation digital calculation model and outputting a coordinate rotation digital calculation result;
the high-level synthesis module comprises:
the LLVM-IR file conversion unit is used for converting a coordinate rotation digital calculation model constructed by high-level language into an LLVM-IR intermediate expression file;
the configuration unit is used for configuring the LLVM-IR intermediate expression file through the Lua script file and converting the LLVM-IR intermediate expression file into a coordinate rotation digital calculation model expressed through a low-level language;
the configuration unit comprises a high-level general optimization layer, a high-level comprehensive transformation layer, a register transmission level code and a behavior level time sequence constraint generation layer which are sequentially connected, wherein the high-level general optimization layer, the high-level comprehensive transformation layer and the register transmission level code and behavior level time sequence constraint generation layer are respectively used for carrying out high-level general optimization on the LLVM-IR intermediate expression file, carrying out high-level comprehensive transformation on the optimized LLVM-IR intermediate expression file, and converting the optimized LLVM-IR intermediate expression file into a coordinate rotation digital calculation model expressed by a register transmission level code language based on the behavior level time sequence constraint.
5. The coordinate-rotation digital computing system of claim 4, wherein the model building module comprises:
the floating point operation conversion unit is used for converting the floating point number into a 64-bit integer number and converting the floating point operation into the integer operation;
the trigonometric function setting unit is used for setting a trigonometric function type; the trigonometric function type comprises a SIN function, a COS function, a TAN function, a COT function, a CSC function and a SEC function;
and the precision adjusting unit is used for modifying the iteration times to adjust the precision of the output result.
6. The coordinate-rotation digital computing system of claim 5, further comprising a human-computer interaction module including a SIN selection key, a COS selection key, a TAN selection key, a COT selection key, a CSC selection key, and a SEC selection key for selecting a set trigonometric function type, and a target precision input unit for modifying a precision of an output result, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110846817.0A CN113743042B (en) | 2021-07-26 | 2021-07-26 | Coordinate rotation digital computing method and system based on high-level comprehensive tool |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110846817.0A CN113743042B (en) | 2021-07-26 | 2021-07-26 | Coordinate rotation digital computing method and system based on high-level comprehensive tool |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113743042A CN113743042A (en) | 2021-12-03 |
| CN113743042B true CN113743042B (en) | 2023-11-10 |
Family
ID=78729098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110846817.0A Active CN113743042B (en) | 2021-07-26 | 2021-07-26 | Coordinate rotation digital computing method and system based on high-level comprehensive tool |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113743042B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115600533A (en) * | 2022-09-07 | 2023-01-13 | 中山大学（Cn） | High-level comprehensive phase-locked amplification processing method, system, device and medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102542336A (en) * | 2011-12-23 | 2012-07-04 | 西安奇维科技股份有限公司 | Triangle function implementation method based on field programmable gata array (FPGA) |
| CN109062540A (en) * | 2018-06-06 | 2018-12-21 | 北京理工大学 | A kind of restructural floating-point operation device based on cordic algorithm |
| CN111666065A (en) * | 2020-06-03 | 2020-09-15 | 合肥工业大学 | Trigonometric function pipeline iteration solving method and device based on CORDIC |
-
2021
- 2021-07-26 CN CN202110846817.0A patent/CN113743042B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102542336A (en) * | 2011-12-23 | 2012-07-04 | 西安奇维科技股份有限公司 | Triangle function implementation method based on field programmable gata array (FPGA) |
| CN109062540A (en) * | 2018-06-06 | 2018-12-21 | 北京理工大学 | A kind of restructural floating-point operation device based on cordic algorithm |
| CN111666065A (en) * | 2020-06-03 | 2020-09-15 | 合肥工业大学 | Trigonometric function pipeline iteration solving method and device based on CORDIC |
Non-Patent Citations (2)
| Title |
|---|
| FPGA高层综合中的内存子系统研究综述;张展鹏等;计算机科学;第39卷(第6A期);第350-356页 * |
| Rigid 3-D Registration: A Simple Method Free of SVD and Eigendecomposition;Jin Wu;IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT;第69卷(第10期);第8288-8303页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113743042A (en) | 2021-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110209830B (en) | Entity linking method, apparatus, device, and computer readable storage medium | |
| Erbas et al. | A framework for system-level modeling and simulation of embedded systems architectures | |
| US7594200B2 (en) | Method for finding multi-cycle clock gating | |
| US20040111248A1 (en) | Polymorphic computational system and method | |
| US20030023950A1 (en) | Methods and apparatus for deep embedded software development | |
| US20120072876A1 (en) | Method and apparatus for reducing x-pessimism in gate-level simulation and verification | |
| CN106775905A (en) | Higher synthesis based on FPGA realizes the method that Quasi-Newton algorithm accelerates | |
| CN113743042B (en) | Coordinate rotation digital computing method and system based on high-level comprehensive tool | |
| CN115204076B (en) | Logic optimization method and device of integrated circuit, electronic equipment and readable medium | |
| Borrione et al. | A compositional model for the functional verification of high-level synthesis results | |
| CN112632890B (en) | Verification of hardware design for data transformation component | |
| US7783467B2 (en) | Method for digital system modeling by using higher software simulator | |
| Du et al. | Actors with stretchable access patterns | |
| Dandamudi | Guide to Assembly Language Programming in Linux | |
| CN116701085B (en) | Form verification method and device for consistency of instruction set design of RISC-V processor Chisel | |
| Saglamdemir et al. | A formal equivalence checking methodology for Simulink and register transfer level designs | |
| CN114970872B (en) | Quantum circuit compiling method and device, medium and electronic device | |
| Ordaz et al. | On the hls design of bit-level operations and custom data types | |
| Leong et al. | The automatic generation of bus-interface models | |
| Paulweber et al. | Unified (A) Synchronous Circuit Development | |
| Lu et al. | Towards High-Level Synthesis of Quantum Circuits | |
| Jeng et al. | FACE: Fine-tuned architecture codesign environment for ASIP development | |
| CN117519643A (en) | Method for verifying arithmetic logic unit and computing device | |
| US8245178B2 (en) | Method for multi-cycle clock gating | |
| US8566772B2 (en) | Method, computer program and computing system for optimizing an architectural model of a microprocessor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |