CN113728431A

CN113728431A - Light emitting diode module

Info

Publication number: CN113728431A
Application number: CN202080029636.2A
Authority: CN
Inventors: 李昶准; 孙圣昊; 李钟声; 丁英基
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2019-05-03
Filing date: 2020-04-29
Publication date: 2021-11-30
Also published as: KR20200127815A

Abstract

A Light Emitting Diode (LED) module includes an integrated substrate comprising: a plurality of LEDs; a glass substrate; and a signal wiring layer provided on the glass substrate. The signal wiring layer includes a plurality of signal electrodes configured to supply data signals to the plurality of LEDs. The LED module further includes a conductive pattern disposed on at least one surface of the integration substrate and connected to a ground.

Description

Light emitting diode module

Technical Field

The present disclosure relates to a light emitting diode module configured to display an image using a light emitting diode.

Background

The display device may include a non-self-luminous display panel such as a Liquid Crystal Display (LCD) and a self-luminous display panel that generates light corresponding to a data signal.

In particular, for self-luminous display panels, Light Emitting Diodes (LEDs) corresponding to inorganic light emitting diodes have been actively studied. An LED is a device that converts an electric signal into a form of light such as infrared ray or visible light by using the characteristics of a compound semiconductor. The LED may be used for home appliances, remote controllers, digital signage, and various automation devices. In addition, LEDs have been widely used in small handheld electronic devices and large display devices. In addition, with the recent development of a micro LED display manufactured by miniaturizing LEDs, LEDs have been implemented in the form of a modular display.

Disclosure of Invention

Technical problem

Provided is a Light Emitting Diode (LED) module capable of preventing damage to an LED, which may be caused by electrostatic discharge, by implementing a conductive pattern in the LED module.

Technical scheme

Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

According to an aspect of the present disclosure, there is provided a Light Emitting Diode (LED) module including: an integrated substrate comprising a plurality of LEDs; a glass substrate; and a signal wiring layer provided on the glass substrate, the signal wiring layer including: a plurality of signal electrodes configured to provide data signals to the plurality of LEDs; and a conductive pattern disposed on at least one surface of the integration substrate and connected to a ground.

The integrated substrate may further include a first substrate, the plurality of LEDs may be disposed on the first substrate, and at least a portion of the conductive pattern may be disposed on at least one side surface of the first substrate.

The integrated substrate may further include a second substrate, the signal wiring layer may further include a plurality of scan lines and a plurality of data lines disposed on the second substrate, and the conductive pattern may be disposed on at least one surface of the second substrate.

The LED module may further include: a plate on a surface of the glass substrate, the plate being connected to the conductive pattern, and the conductive pattern may be connected to ground through the plate.

The signal wiring layer may further include: at least one via hole penetrating through the glass substrate; a plurality of reference electrodes, wherein the conductive pattern is connected to the plurality of reference electrodes through the at least one via and to ground through at least one of the plurality of reference electrodes.

The conductive pattern may be electrically isolated from the plurality of LEDs and the plurality of signal electrodes.

The conductive pattern may be connected to ground through an external component.

The signal wiring layer may further include: an upper signal wiring layer disposed between the plurality of LEDs and the first surface of the glass substrate; a lower signal wiring layer connected to the upper signal wiring layer and disposed on a second surface of the glass substrate, the second surface facing the first surface of the glass substrate.

The LED module may further include a side wiring configured to connect the upper signal wiring layer to the lower signal wiring layer.

According to an aspect of the present disclosure, there is provided a Light Emitting Diode (LED) module including: a glass substrate including a pair of surfaces and a plurality of side surfaces between the pair of surfaces; an upper signal wiring layer disposed on the glass substrate and including a plurality of signal electrodes configured to supply data signals to a plurality of LEDs and a plurality of reference electrodes configured to ground the plurality of LEDs; a lower signal wiring layer connected to the upper signal wiring layer, the lower signal wiring layer being disposed below the glass substrate; a side wiring disposed on at least one first surface of the LED module and configured to connect the upper signal wiring layer to the lower signal wiring layer; and a conductive pattern disposed on at least one second surface of the LED module different from the at least one first surface, the conductive pattern being connected to at least one of the plurality of reference electrodes.

At least a portion of the conductive pattern may be disposed on at least one side surface of the upper signal wiring layer.

At least a portion of the conductive pattern may be disposed on at least one side surface of the lower signal wiring layer.

The LED module may further include: at least one plate disposed on a surface of the glass substrate and connected to the conductive pattern, wherein the conductive pattern is connected to ground through the at least one plate.

The glass substrate may further include at least one via penetrating the pair of surfaces, wherein the conductive pattern is connected to at least one of the plurality of reference electrodes through the at least one via.

According to an aspect of the present disclosure, there is provided a Light Emitting Diode (LED) module including: a glass substrate including a pair of surfaces and four side surfaces between the pair of surfaces; a plurality of LEDs disposed on the glass substrate; a signal wiring layer electrically connected to the plurality of LEDs; a driving signal wiring layer disposed on a lower surface of the glass substrate; a side wiring provided on a first side surface of the glass substrate and a second side surface of the glass substrate, the second side surface facing the first side surface, the side wiring configured to electrically connect the signal wiring layer to the driving signal wiring layer; and a conductive pattern provided on a third side surface of the glass substrate and a fourth side surface of the glass substrate, the third side surface and the fourth side surface being different from the first side surface and the second side surface, the third side surface facing the fourth side surface, and the conductive pattern being connected to a ground.

A reference electrode may be included in at least one of the signal wiring layer and the driving signal wiring layer, and the conductive pattern may be electrically connected to the reference electrode.

The glass substrate may have a rectangular shape, and the pair of surfaces may include flat surfaces.

The conductive pattern may be electrically isolated from the plurality of LEDs, the signal wiring layer, and the driving signal wiring layer.

The conductive pattern may have a capacitance greater than that of the side wiring and an impedance lower than that of the side wiring.

Drawings

Fig. 1 is a perspective view of a display device according to an embodiment;

fig. 2 is an exploded perspective view of a display panel used in the display device according to the embodiment;

fig. 3 is a view illustrating a display panel provided with a Light Emitting Diode (LED) module according to an embodiment;

fig. 4 is a schematic diagram showing a configuration of an LED module according to the embodiment;

fig. 5 is a circuit diagram showing a circuit provided in a pixel region of the display panel of fig. 4;

fig. 6 is a sectional view showing an arrangement structure of a pixel region of a display panel according to an embodiment;

fig. 7A is a sectional view showing a configuration in which an upper signal wiring layer is connected to a lower signal wiring layer according to the embodiment;

fig. 7B is a sectional view showing a configuration in which an upper signal wiring layer is connected to a lower signal wiring layer according to the embodiment;

fig. 8A is a plan view illustrating an implementation of a conductive pattern implemented on an LED module, according to an embodiment;

fig. 8B is a cross-sectional view showing an implementation of a conductive pattern on an LED module according to an embodiment;

fig. 9A is a plan view of an LED module according to an embodiment;

fig. 9B is a cross-sectional view of an LED module according to an embodiment;

fig. 10A is a plan view of an LED module according to an embodiment;

fig. 10B is a perspective view of an LED module according to an embodiment;

fig. 11A is a plan view of an LED module according to an embodiment;

fig. 11B is a perspective view of an LED module according to an embodiment;

fig. 12 is a cross-sectional view showing a power supply for an LED module according to an embodiment; and

fig. 13 is a block diagram of a display device according to an embodiment.

Detailed Description

The embodiments described in the present disclosure and the configurations shown in the drawings are merely examples of the embodiments of the present disclosure, and may be modified in various different ways to replace the embodiments and drawings of the present disclosure at the time of filing the present application.

The terminology used herein is for the purpose of describing embodiments and is not intended to be limiting and/or restrictive of the disclosure.

The singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

In the present disclosure, the terms "comprises," "comprising," "includes," "including," "has," "having," and the like, are used to specify the presence of stated features, quantities, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, elements, steps, operations, elements, components, or combinations thereof.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, the elements are not limited by these terms.

Furthermore, terms such as "unit," "component," "block," "member," and "module" indicate a unit for processing at least one function or operation, and may represent at least one hardware (e.g., a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC)), at least one software stored in a memory, and/or at least one process processed by a processor.

The present disclosure will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals refer to like elements throughout the description. Well-known functions or constructions are not described in detail since they would obscure one or more example embodiments in unnecessary detail. The relative sizes and descriptions of these elements may be exaggerated for clarity, illustration, and convenience.

It will be understood that when an element or layer is referred to as being "on," "over," "on," "connected to," or "coupled to" another element or layer, it can be directly on, over, or on the other element or layer, may be connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "above," "on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present.

Also, when a given layer of material is described as being on a substrate or other layer, that layer of material may be in direct contact with the substrate or other layer, and another third layer may be present therebetween. In the following examples, the material forming each layer is an example, and other materials may be used.

Hereinafter, the display device includes any device capable of providing an image to a user by displaying the image. For example, the display apparatus may include a display device such as, but not limited to, a television, a monitor, a laptop computer, and a mobile communication terminal.

Fig. 1 is a perspective view of a display device according to an embodiment, and fig. 2 is an exploded perspective view of a display panel used in the display device according to the embodiment.

Referring to fig. 1, a display device 1 includes a display panel 2 on which a screen is displayed and a case 3 configured to support the display panel 2 and provide a rear surface and/or a side surface of the display device (refer to fig. 3). The display panel 2 may be implemented with at least one Light Emitting Diode (LED) module 10.

Referring to fig. 2, the display panel 2 may include LED modules 10 arranged in columns and rows in a MN matrix form, a fixing member 12 configured to allow the LED modules 10 to be fixed in a matrix form, and a glass panel 13 arranged on the front side of the LED modules 10 by the fixing member 12.

Fig. 2 shows that the LED module 10, the fixing member 12, and the glass panel 13 are separable from each other. However, in the embodiment, the LED module 10 and the glass panel 13 may be integrally formed with the fixing member 12 therebetween, thereby forming the display panel 2.

That is, according to the embodiment, the display device 1 may include: a glass plate (or glass substrate), a plurality of Light Emitting Diodes (LEDs), and a signal wiring layer disposed on the glass substrate, the signal wiring layer further comprising a plurality of signal electrodes configured to provide a data signal to each of the plurality of LEDs and a plurality of reference electrodes configured to ground the plurality of LEDs.

According to the embodiment, the conductive pattern may be formed on at least one surface of the integrated substrate implemented by the glass substrate, the plurality of LEDs, and the signal wiring layer.

The conductive pattern may be connected to at least one of the plurality of reference electrodes or ground.

Further, the display device 1 may further include a glass panel disposed on the front surface of the integration substrate and a fixing member configured to fix the integration substrate.

Fig. 3 is a view illustrating a display panel provided with a Light Emitting Diode (LED) module according to an embodiment.

Referring to fig. 3, the LED module 10 includes a glass substrate P3 and a plurality of LEDs 300 mounted on the glass substrate P3.

The glass substrate P3 may include a transparent material such as glass, and a plurality of pixel regions P may be formed. According to an embodiment, the circuits and elements mounted on the glass substrate may be mounted in a Chip On Glass (COG) type. Specifically, the COG type may be a method of directly embedding a driving integrated circuit on a glass substrate of a liquid crystal panel to achieve ultra-thin and lightweight fine pitch of a display panel.

The signal wiring layer P2 is a Thin Film Transistor (TFT) substrate, and a thin film transistor and various wirings for driving the LED 300 may be formed corresponding to the pixel region P. When the thin film transistor is turned on, a driving signal input from the outside through the wiring is applied to the LED 300, and thus the LED 300 emits light to implement an image.

Referring to fig. 3, the LED module 10 may include a glass substrate P3, a TFT array substrate P2, and a substrate P1 including LEDs 300, wherein the TFT array substrate P2 includes a plurality of signal electrodes configured to provide a data signal to each LED 300 and a plurality of reference electrodes configured to ground the plurality of LEDs 300.

According to an embodiment, the LED 300 may have a size of 10-100 μm, and the LED 300 may be formed in the following manner: a thin film growth method is performed on a sapphire substrate or a silicon substrate using inorganic materials such As Al, Ga, N, P, As, and In, and then the sapphire substrate or the silicon substrate is cut and separated. Therefore, the LED 300 may have a fine size.

The plurality of gate lines and data lines may be arranged in vertical and horizontal directions to define a plurality of pixel regions P in a matrix form. In this case, the gate line and the data line may be connected to the LED 300, ends of the gate line and the data line may be provided with a gate pad and a data pad connected to the outside, respectively, and the gate pad and the data pad may be formed in the side wiring in the above-described LED module 10.

The LED 300 may operate based on an external signal applied to the LED 300 through the gate line and the data line.

Fig. 4 is a schematic diagram showing a configuration of an LED module according to the embodiment.

Referring to fig. 4, a plurality of data lines D1-Dm, a plurality of scan lines S1-Sn, and a plurality of pixel circuits may be disposed on one surface of the LED module as an electrode pattern. The pixel region SP may represent a region defined by intersections between adjacent ones of the data lines D1-Dm and the scan lines S1-Sn, and may be provided with pixel circuits. The plurality of pixel regions SP may be grouped into pixels, and one color represented by a corresponding pixel may be selected by mixing respective lights generated in one pixel region SP.

The data lines D1-Dm may transmit data signals representing image signals to corresponding pixel circuits of the pixel regions SP, and the scan lines S1-Sn may transmit scan signals to corresponding pixel circuits of the pixel regions SP.

The scan driver 140 may sequentially apply scan signals to each of the plurality of scan lines S1-Sn arranged in the row direction, and the data driver 130 may sequentially apply data Voltages (VDATA) corresponding to image signals to the data lines D1-Dm arranged in the column direction.

The scan driver 140 and/or the data driver 130 may be electrically connected to the display panel 110, or may be mounted in a chip form to a Tape Carrier Package (TCP) that is bonded to the display panel 110 and then electrically connected to the display panel 110. Alternatively, the scan driver 140 and/or the data driver 130 may be mounted in a chip form to a Flexible Printed Circuit (FPC) or a film, which is bonded to the display panel 110 and then electrically connected to the display panel 110. In addition, the scan driver 140 and/or the data driver 130 may be directly mounted to the substrate of the LED module 10.

Fig. 5 is an equivalent circuit diagram showing a pixel circuit of the pixel region of fig. 4. Specifically, fig. 5 shows a pixel circuit driven by the first scan line S1 and the first data line D1.

Referring to fig. 5, the pixel circuit may include an LED, two transistors M1 and M2, and a capacitor Cst. The plurality of transistors M1 and M2 may be provided as PMOS transistors. However, such a circuit configuration is based on an Active Matrix (AM) driving method, which is merely an example of a pixel circuit. Therefore, the pixel circuit is not limited to the circuit configuration of fig. 4.

For the switching transistor M2, a gate electrode may be connected to the scan line Sn, a source electrode may be connected to the data line Dm, a drain electrode may be connected to a first terminal of the capacitor Cst and a gate electrode of the driving transistor M1, and a second terminal of the capacitor Cst may be connected to the power supply voltage VDD. For the driving transistor M1, the source electrode may be connected to the power supply voltage VDD, the drain electrode may be connected to the anode 310 (refer to fig. 6) of the LED, and the cathode 390 (refer to fig. 6) of the LED may be connected to the reference voltage VSS through the reference electrodes 250-1 and 250-2 (refer to fig. 6). Accordingly, the LED may emit light based on the current applied from the driver transistor M1. The reference voltage VSS connected to the cathode 390 of the LED may be lower than the power supply voltage VDD, and thus the ground voltage may be used as the reference voltage VSS.

According to an embodiment, a power supply provided in the LED may supply a power supply voltage VDD to the LED module and connected to a reference voltage VSS.

The operation of the pixel circuit according to the embodiment is described. First, when a scan signal is applied to the scan line Sn and the switching transistor M2 is turned on, a data voltage may be transmitted to the first terminal of the capacitor Cst and the gate electrode of the driving transistor M1. Accordingly, the gate-source voltage VGS of the driver transistor M1 may be maintained by the capacitor Cst for a predetermined period of time. In addition, the driving transistor M1 may allow the LED to emit light by applying a current ILED corresponding to the gate-source voltage VGS of the driving transistor M1 to the anode 310 of the LED.

When the high data voltage VDATA is transmitted to the gate electrode of the driving transistor M1, the gate-source voltage VGS of the driving transistor M1 may be lowered. Accordingly, a small amount of current ILED may be applied to the anode 310 of the LED, and thus the LED may emit light having a small intensity. Therefore, the LED may display low gray. On the other hand, when the low data voltage VDATA is transmitted to the gate of the driving transistor M1, the gate-source voltage VGS of the driving transistor M1 may increase. Accordingly, a large amount of current ILED may be applied to the anode 310 of the LED, and thus the LED may emit light having a large intensity. Therefore, the LED can display high gray. Therefore, the level of the data voltage VDATA applied to each pixel circuit can be selected based on an image to be displayed.

An embodiment of a cross section of the pixel region SP is shown in fig. 6.

Fig. 6 is a view illustrating an arrangement structure of a pixel region of a display panel according to an embodiment. Fig. 6 shows a case where one of the two transistors 200 is connected to the LED 300.

The glass substrate P3 may include various materials. For example, the glass substrate P3 may be formed of a transparent glass material containing SiO2 as a main component, but the glass substrate P3 is not limited thereto. Accordingly, the glass substrate P3 may be formed of a transparent plastic material, and thus the glass substrate P3 may have flexibility. The plastic material may be an insulating organic material selected from the group consisting of: polyethersulfone (PES), Polyacrylate (PAR), Polyetherimide (PEI), polyethylene terephthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide, Polycarbonate (PC), cellulose Triacetate (TAC), and Cellulose Acetate Propionate (CAP).

The buffer layer 111 may be formed on the glass substrate P3. The buffer layer 111 may provide a flat surface on top of the glass substrate P3 and may prevent foreign substances or moisture from being introduced into the glass substrate P3. For example, the buffer layer 111 may be formed of an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, titanium oxide, or titanium nitride, or an organic material such as polyimide, polyester, or acrylic. Alternatively, the buffer layer 111 may be formed of a plurality of stacked layers of inorganic materials as described above.

The transistor 200 may be disposed on the buffer layer 111.

The transistor 200 may include an active layer 210, a gate electrode 220, a source electrode 230a, and a drain electrode 230 b. The active layer 210 may include a semiconductor material, and the active layer 210 may include a source region, a drain region, and a channel region between the source region and the drain region. The gate electrode 220 may be formed on the active layer 210 to correspond to the channel region. The source and

drain electrodes

230a and 230b may be electrically connected to the source and drain regions of the active layer 210, respectively. The first insulating layer 113 formed of an inorganic insulating material may be disposed as a gate insulating film between the active layer 210 and the gate electrode 220. The second insulating layer 115 may be disposed as an interlayer insulating film between the gate electrode 220 and the source electrode 230a and between the gate electrode 220 and the drain electrode 230 b. The third insulating layer 117 may be disposed as a planarization film on the source electrode 230a and the drain electrode 230 b. The second insulating layer 115 and the third insulating layer 117 may be formed of an organic insulating material or an inorganic insulating material. Alternatively, the second insulating layer 115 and the third insulating layer 117 may be formed by alternating an organic insulating material and an inorganic insulating material.

Fig. 6 shows that the transistor 200 is implemented in a top gate type in which a gate electrode is disposed on top of an active layer, but the present disclosure is not limited thereto. In an embodiment, the gate electrode may be disposed under the active layer.

The buffer layer 111, the first insulating layer 113, the second insulating layer 115, the third insulating layer 117, and the transistor 200 may form a signal wiring layer including the scan line and the data line described above. According to an embodiment, a signal wiring layer may be formed in a Thin Film Transistor (TFT) substrate.

In the embodiment of fig. 6. A layer including the LED 300 is referred to as a first substrate P1, and a layer including a scan line and a data line and including the buffer layer 111, the first insulating layer 113, the second insulating layer 115, the third insulating layer 117, and the transistor 200 is referred to as a second substrate. The second substrate may include an upper signal wiring layer P2-1 and a lower signal wiring layer P2-2.

The first substrate P1, the second substrate including the layers P2-1, P2-2, and the glass substrate P3 may form an integrated substrate.

Further, although the LED 300 is described as an inverted type, a vertical type is also applicable.

The bank 400 defining the pixel region may be disposed on the third insulating layer 117. The bank 400 may include a recess 430 in which the LED 300 is to be received. The height of the bank 400 may be selected based on the height and viewing angle of the LEDs 300. The size (or width) of the recess 430 may be selected based on the resolution and pixel density of the display device 1. According to an embodiment, the height of the LED 300 may be greater than the height of the bank 400.

Fig. 6 shows that the recess 430 has a quadrangular shape, but is not limited thereto. Accordingly, the recess 430 may have various shapes, such as a polygonal shape, a rectangular shape, a circular shape, a conical shape, an elliptical shape, and a triangular shape.

The signal electrode 510 may be disposed along side and bottom surfaces of the recess 430 and an upper surface of the memory bank 400 around the recess 430. The signal electrode 510 may be electrically connected to the source electrode 230a or the drain electrode 230b of the transistor 200 through a via hole formed on the third insulating layer 117.

According to an embodiment, a conductive pattern to be described later may be connected to ground together with the reference electrode through a via hole.

The bank 400 may function as a light blocking part having low light transmittance to block light emitted toward a side surface of the LED 300. Accordingly, the bank 400 may prevent colors of light emitted from the LEDs 300 adjacent to each other from being mixed. In addition, the bank 400 may improve a bright room contrast of the display device 1 by absorbing and blocking light incident from the outside. The storage volume 400 may comprise a material that absorbs at least some of the optical beam, a light reflecting material and/or a light scattering material.

The bank 400 may include a translucent or opaque insulating material for visible light (e.g., light having a wavelength ranging from 380nm to 750 nm). The memory body 400 may be formed of a thermoplastic resin such as Polycarbonate (PC), polyethylene terephthalate (PET), polyether sulfone, polyvinyl butyral, polyphenylene ether, polyamide, polyetherimide, norbornene-based resin, methacrylic resin, or cyclic polyolefin-based resin, a thermosetting resin such as epoxy resin, phenol resin, urethane resin, acrylic resin, vinyl ester resin, imide-based resin, polyurethane-based resin, urea resin, or melamine resin, or an organic insulating material such as polystyrene, polyacrylonitrile, or polycarbonate, but is not limited thereto.

Alternatively, the memory body 400 may be formed of an inorganic insulating material, for example, an inorganic oxide such as SiOx, SiNx, SiNxOy, AlOx, TiOx, TaOx, or ZnOx, or an inorganic nitride, but is not limited thereto.

According to an embodiment, the bank 400 may be formed of an opaque material such as a black matrix material. The insulating black matrix material may include a resin or paste including an organic resin, a glass paste, and a black pigment, metal particles (e.g., nickel, aluminum, molybdenum, and alloys thereof), metal oxide particles (e.g., chromium oxide), or metal nitride particles (e.g., chromium nitride). According to another embodiment, the memory bank 400 may be a Distributed Bragg Reflector (DBR) having a high reflectivity or a specular reflector formed of metal.

The LED 300 may be disposed on the recess 430 of the bank 400. The LED 300 may be a micro LED. The micro LED may have a size of 1 to 100 μm, but the LED 300 is not limited thereto. Thus, the LED 300 may employ LEDs having a size greater or smaller than 1 to 100 μm. The LEDs 300 may be individually or collectively picked up from the wafer by a transfer mechanism and transferred to the glass substrate P3 to be accommodated in the recess 430 of the glass substrate P3. According to an embodiment, after the memory bank 400 and the signal electrode 510 are formed, the LED 300 may be received in the recess 430 of the glass substrate P3. The LED 300 may emit light of a predetermined wavelength in a wavelength range from ultraviolet light to visible light. For example, the LED 300 may be a red, green, blue, white LED, or an Ultraviolet (UV) LED.

The LED 300 may include a p-n diode, an anode 310, and a cathode 390. Anode 310 and/or cathode 390 can be formed from a variety of conductive materials including metals, conductive oxides, and conductive polymers. The anode 310 may be electrically connected to the signal electrode 510, and the cathode 390 may be electrically connected to the common electrode 530. The p-n diode may include a p-doped portion 330 in the anode 310 side, one or more quantum well portions 350, and an n-doped portion 370 in the cathode 390 side. Alternatively, the doping in the cathode 390 side may correspond to the p-doping 330 and the doping in the anode 310 side may correspond to the n-doping 370.

A passivation layer 520 may be disposed to surround the LED 300 in the recess 430. The passivation layer 520 may be disposed between the memory bank 400 and the LED 300. The passivation layer 520 may include an organic insulating material. For example, the passivation layer 520 may be formed of acrylic, Polymethylmethacrylate (PMMA), benzocyclobutene (BCB), polyimide, acrylate, epoxy, and polyester, but is not limited thereto.

Each of the LEDs 300 included in the display device 1 may emit a unique color. In this case, each of the plurality of LEDs included in one pixel region P may be connected to a different signal electrode and may be disposed to share one common electrode 530.

The signal wiring layers may include an upper signal wiring layer P2-1 disposed above the glass substrate P3 and a lower signal wiring layer P2-2 disposed below the glass substrate P3.

Reference electrodes 250-1 and 250-2 may be disposed on at least one of upper signal wiring layer P2-1 and lower signal wiring layer P2-2.

Regardless of the positions of reference electrodes 250-1 and 250-2 disposed on the upper and/or lower signal wiring layers, upper signal wiring layer P2-1 and lower signal wiring layer P2-2 may be connected to each other.

In fig. 6, the reference electrode is conceptually shown as an electrode arranged in the signal wiring layer. However, the embodiment is not limited thereto as long as the diode is an electrode of a wiring connected to a reference voltage.

The reference electrodes provided in the upper wiring layer P2-1 and the lower wiring layer P2-2 can be shared regardless of the connection method of the upper signal wiring layer P2-1 and the lower signal wiring layer P2-2. The reference electrode may be connected to ground.

As will be described later, the upper signal wiring layer P2-1 and the lower wiring layer P2-2 may be connected to each other in various ways.

Fig. 7A and 7B are sectional views showing a configuration in which an upper signal wiring layer is connected to a lower signal wiring layer according to an embodiment.

Fig. 7A shows that the upper signal wiring layer P2-1 is connected to the lower signal wiring layer P2-2 through the glass substrate P3.

The connection structure between the upper signal wiring layer P2-1 and the lower signal wiring layer P2-2 illustrated in fig. 7A may be referred to as a Through Glass Via (TGV) method.

According to an embodiment, the upper signal wiring layer P2-1 may be connected to the lower signal wiring layer P2-2 through vias formed in the glass substrate P3.

Specifically, pad 270-1 provided in upper signal wiring layer P2-1 may be connected to flexible printed circuit pad 260 provided in lower signal wiring layer P2-2 by a via.

The flexible circuit board pads 260 may be connected to external components of the LED module 10.

In this case, the conductive pattern may be connected to the ground through the wiring of the via hole formed in the glass substrate P3. Further, the conductive pattern may be connected to the reference electrode 250-2 provided in the lower signal wiring layer P2-2.

Fig. 7B shows that upper signal wiring layer P2-1 is connected to lower signal wiring layer P2-2 through separate side wiring 280.

Specifically, side wiring pad 270-2 of upper signal wiring layer P2-1 may be connected to side wiring pad 270-3 of lower signal wiring layer P2-2 by side wiring 280.

Specifically, the side wiring 280 may connect the upper and lower pads of the glass substrate P3 to each other.

When the upper signal wiring layer P2-1 is connected to the lower signal wiring layer P2-2 through the side wiring 280, a conductive pattern may be formed on the surface of the integrated substrate where the side wiring 280 is not formed. A detailed description thereof will be described later.

As illustrated in fig. 7A, the flexible circuit board pad 260 may be disposed in the lower signal wiring layer P2-2 and connected to an external component of the LED module 10.

Further, the conductive pattern may be connected to the reference electrode 250-2 provided in the lower signal wiring layer P2-2.

Referring again to fig. 7B, according to an embodiment, the LED module 10 may be provided in a structure in which at least one layer is stacked.

An upper layer included in the LED module 10 may be disposed on an upper surface of the glass substrate P3 to fix the plurality of LEDs 300.

In addition, the upper layer of the LED module 10 may include a plurality of signal electrodes configured to provide data signals to the plurality of LEDs 300 and a plurality of reference electrodes configured to ground the plurality of LEDs 300.

The upper layer of the LED module 10 may include an upper signal wiring layer P2-1. The upper layer of the LED module 10 may include a first substrate P1 and an upper signal wiring layer P2-1.

The lower layer of the LED module 10 may include a lower signal wiring layer P2-2 connected to the upper signal wiring layer P2-1, and may be disposed under the glass substrate P3.

According to the embodiment shown in fig. 7B, side wiring 280 may be configured to connect upper signal wiring layer P2-1 to lower signal wiring layer P2-2.

In addition, the conductive pattern may be disposed on a side surface of the LED module 10 and connected to at least one of the plurality of reference electrodes.

The entire LED module 10 may be provided as a substrate structure, and the substrate structure may be provided to have an upper surface, a lower surface, and side surfaces.

The side wiring 280 may be disposed on a portion of the side surface, and the conductive pattern may be disposed on a surface of the LED module 10 on which the side wiring 280 is not disposed.

At least a portion of the conductive pattern may be disposed on at least one side surface of an upper layer of the LED module 10, and may be formed on at least one side surface of a lower layer of the LED module.

Further, it should be understood that the above-described upper and lower layers of the LED module 10 may be functional expressions.

Specifically, the above-described upper and lower layers may be integrally formed on the substrate. The upper and lower layers may be formed as a structure stacked on a substrate and formed by using a process of film bonding and deposition and patterning of various conductors, semiconductors, and nonconductors based on the substrate. It will be understood by those skilled in the art that the extent (e.g., width or thickness) of the upper and/or lower layers may vary.

Fig. 8A and 8B are a plan view and a sectional view of the LED module 10 according to the embodiment, respectively, to explain an implementation of the conductive pattern on the LED module 10.

Referring to fig. 8A and 8B, according to an embodiment, the LED module 10 may include an ultra-small LED (e.g., a size of several micrometers (μm)).

According to an embodiment of the present disclosure, the LED module 10 may include a conductive pattern 600 connected to a reference electrode independently (or electrically isolated) from the plurality of LEDs and the plurality of signal electrodes.

Further, in the implementation of the LED module 10, the conductive pattern 600 may be formed on a side surface of the LED module 10 to prevent damage to the LED 300.

When electrostatic discharge (ESD) occurs, current may flow to the conductive pattern 600 and then to ground. Accordingly, the conductive pattern 600 may provide protection of the LED 300 and the signal wiring. Further, the conductive pattern 600 may have a larger capacitance and a lower impedance compared to the capacitance and impedance of the side wiring.

In addition, the conductive pattern 600 may be disposed to be electrically independent (or electrically isolated) from the first substrate P1 including the LED 300 and the second substrates P2-1 and P2-2 including the plurality of signal electrodes.

The conductive pattern 600 may be disposed to surround the LED 300 and the plurality of signal electrodes.

The conductive pattern 600 may be connected to the reference electrodes 250-1 and 250-2 independently of the plurality of signal electrodes. In addition, the conductive pattern 600 may be connected to the board P4 provided in the LED module 10. Panel P4 may be connected to ground. For example, the board P4 may be provided on the lower portion of the LED module 10, and fig. 8A may be a plan view when viewed from the bottom of the LED module 10.

As described above, when ESD is applied to the LED module 10 in a state where the conductive pattern 600 is connected to the ground, the ESD may flow to the ground through the conductive pattern 600 without affecting other circuits included in the LED module 10.

The conductive pattern 600 may be connected to ground in various forms, an example of which is shown in fig. 8B.

The conductive pattern 600 may be connected to the reference electrodes 250-1 and 250-2 independently of the plurality of signal electrodes, and the reference electrode may provide a ground. The signal wiring levels may include an upper signal wiring level P2-1 and a lower signal wiring level P2-2.

The reference electrode 250-2 may be disposed on the lower signal wiring layer P2-2 and then connected to the conductive pattern 600.

The reference electrode provided on the lower signal wiring layer P2-2 may be connected to ground.

The conductive pattern 600 may be directly connected to the board P4 disposed under the LED module 10 through a separate wiring. According to an embodiment, the board P4 may be connected to ground.

Accordingly, the conductive pattern 600 may be connected to the ground through the board P4.

The conductive pattern 600 may be connected to a wiring in a via provided in the lower signal wiring layer P2-2, and further, to the reference electrode 250-2 by a wiring. Reference electrode 250-2 may be connected to a via provided in lower signal wiring layer P2-2.

Accordingly, the conductive pattern 600 may be connected to the reference electrode 250-2 and to the ground through the via provided on the lower signal wiring layer P2-2.

According to another embodiment, the conductive pads may be connected to ground through an external component of the LED module 10. The detailed description thereof will be described below.

The LED module 10 may include a first substrate P1 including the LEDs 300 and second substrates P2-1 and P2-2 on which a plurality of scan lines and a plurality of data lines are disposed.

At least a portion of the conductive pattern 600 may be disposed on at least one side surface of the first substrate.

When electrostatic discharge (ESD) occurs in the LED module 10, the ESD may be transmitted to the conductive pattern 600 provided in the LED module 10, not to the LED 300 and the signal electrode. The conductive pattern 600 may transfer the ESD to a connected ground. Based on this operation, the ESD applied to the LED module 10 may not be transmitted to the LED and the signal electrode, but transmitted to the ground through the conductive pattern 600.

As described above, the conductive patterns 600 may be independently provided without being connected to the circuit configuration of the LED module 10 that connects the plurality of scan lines, the plurality of data lines, and the LEDs.

It is described above that the conductive pattern 600 may be connected to the ground, thereby directly transferring the ESD to the ground. However, the form in which the conductive pattern 600 is connected to the ground is not limited thereto, and may be varied as long as the conductive pattern 600 is implemented to be connected to the ground.

Further, the operations described in fig. 8A and 8B are only examples of protecting the LED module 10 of the present disclosure, and the operation of transferring ESD through the conductive pattern 600 may be performed in various ways.

Fig. 9A, 9B, 10A, 10B, 11A, and 11B are views showing various implementations of conductive patterns on the LED module 10.

Fig. 9A is a plan view of the LED module 10 according to the embodiment, and fig. 9B is a sectional view of the LED module 10 according to the embodiment.

Referring to fig. 9A and 9B, conductive patterns 600-9A and 600-9B may be disposed to surround the LED 300 and connected to ground.

When the conductive patterns 600-9A and 600-9B are connected to the ground, the conductive patterns 600-9A and 600-9B may eliminate ESD occurring in the LED module 10. The conductive patterns 600-9A and 600-9B may be connected to the reference electrodes 250-1 and 250-2.

Reference electrodes 250-1 and 250-2 may be connected to a reference voltage VSS. As described above, the conductive patterns 600-9A and 600-9B may be connected to the signal wiring layer, specifically, the reference electrode 250-2 of the lower signal wiring layer P2-2. According to an embodiment, the conductive patterns 600-9A and 600-9B may be directly connected to the reference electrode 250-2 disposed in the lower signal wiring layer P2-2. According to an embodiment, the reference electrode may be connected to the conductive patterns 600-9A and 600-9B through a via provided in the lower signal wiring layer P2-2. Further, as described above, the conductive patterns 600-9A and 600-9B may be connected to the ground through the board 4 provided in the LED module 10.

Fig. 10A is a plan view of an LED module according to an embodiment, and fig. 10B is a perspective view of the LED module according to the embodiment.

Fig. 10A and 10B show that at least a part of the conductive pattern is disposed on the side surface of the LED module 10. Fig. 10A shows that the conductive patterns 600-10A are disposed on the side surface of the first substrate P1 and the periphery of the LED module 10.

Further, fig. 10A and 10B show that the conductive pattern 600-10A or 600-10B is provided at a position where the side wiring 280 is not placed. The side wiring 280 may connect the upper signal wiring layer P2-1 disposed above the glass substrate to the lower signal wiring layer P2-2 disposed below the glass substrate. The details of the side wiring 280 have been described above, and a repetitive description thereof will be omitted.

The side wiring 280 and the conductive pattern 600-10A or 600-10B may be formed in a thin film structure on a side surface of a substrate structure included in the LED module 10.

According to the embodiment, the side wiring 280 and the conductive pattern 600-10A or 600-10B may be formed in the form of a thin film, and may be formed to be in close contact with a side surface of a glass substrate included in the LED module 10.

The conductive patterns 600-10A and 600-10B may be connected to a reference electrode and then to ground. Specifically, the conductive patterns 600-10A and 600-10B may be connected to the ground through the reference electrodes 250-1 and 250-2, but alternatively, may be connected to the ground through the board P4 and external components (e.g., other frames and/or other substrates provided in the display device).

The conductive patterns 600-10A may be disposed in consideration of a positional relationship of the conductive patterns 600-10A with respect to the LEDs disposed on the first substrate P1 and the signal electrodes and the side wirings disposed on the second substrate P2.

According to an embodiment, the signal electrode and the side wiring 280 may be disposed on at least one surface of the LED module 10, and the conductive patterns 600-10A may be disposed in a region on the LED module 10 where the wiring of the signal electrode is not disposed.

In addition, the conductive patterns 600-10A may be connected to a reference electrode provided in the LED module 10. The conductive patterns 600-10A may be intermittently disposed on the side surface of the first substrate P1. The intermittently arranged conductive patterns 600-10A and 600-10B may be connected to the ground through one or more paths.

The conductive pattern 600-10B shown in fig. 10B is formed on the side surface of the first substrate P1 on which the LEDs 300 are mounted in an intermittent manner, and thus the conductive pattern 600-10B may be connected to the ground through one or more paths.

Specifically, a plurality of reference electrodes may be provided in the signal wiring layer. Each reference electrode may be connected to ground. Accordingly, the intermittently arranged conductive patterns 600-10B may be connected to the ground by being connected to a plurality of reference electrodes.

The conductive pattern may be formed in consideration of the wiring position of the wiring of the signal electrode provided on the second substrate P2.

The configuration described in fig. 10A and 10B is merely an example of the present disclosure. The configuration of the LED module and the conductive pattern may vary as long as the conductive pattern can eliminate ESD by being connected to ground.

Fig. 11A is a plan view of the LED module 10 according to the embodiment, and fig. 11B is a perspective view of the LED module 10 according to the embodiment.

Referring to fig. 11A and 11B, a side wiring 280 configured to connect an upper signal wiring layer to a lower signal wiring layer as shown in fig. 10A and 10B may be provided. In addition, the conductive patterns 600-11A and 600-11B may be disposed to avoid the surface of the LED on which the side wiring 280 is formed.

However, the conductive patterns 600-11A and 600-11B shown in fig. 11A and 11B may be continuously provided, unlike fig. 10A and 10B. In fig. 11A and 11B, since the conductive patterns 600-11A and 600-11B are formed on the surface of the integration substrate except the surface on which the side wiring 280 is formed, the conductive patterns 600-11A and 600-11B may be continuously disposed.

In this case, the conductive patterns 600-11A and 600-11B may be connected to the ground without any limitation on the forms of the conductive patterns 600-11A and 600-11B.

Specifically, according to an embodiment, the LED module 10 may include a rectangular type glass substrate.

The glass substrate may include a first surface and a second surface, and may include a plurality of side surfaces surrounding the first surface and the second surface.

The first and second surfaces may be disposed to face each other, and the side surface may be disposed to surround the first and second surfaces.

Each of the first surface and the second surface may correspond to a planar surface of the glass substrate.

According to an embodiment, the first surface may correspond to an upper surface of the glass substrate and the second surface may correspond to a lower surface of the glass substrate.

According to another embodiment, the first surface may correspond to the lower surface and the second surface may correspond to the upper surface.

Further, according to the embodiment, the LED module 10 may include a plurality of LEDs arranged on an upper surface of a glass substrate, a signal wiring layer electrically connected to the LEDs, and a driving signal wiring layer disposed on a lower surface of the glass substrate.

According to an embodiment, the side wiring 280 may be formed on a first side surface of the glass substrate and a second side surface of the glass substrate opposite to the first side surface.

The side wiring 280 may electrically connect the signal wiring layer to the driving signal wiring layer. The conductive patterns 600-11A and 600-11B may be formed on third and fourth side surfaces of the glass substrate, which are different from the first and second side surfaces of the glass substrate provided with the side wiring 280, and the conductive patterns 600-11A and 600-11B are connected to the ground to prevent electrostatic discharge from being applied to the LEDs. The third surface may be opposite the fourth surface.

Specifically, the side wiring 280 may be arranged in two side surfaces (e.g., a first side surface and a second side surface) of the LED module 10 provided as a rectangular substrate, and the two side surfaces may face each other. The conductive patterns 600-11A and 600-11B may be arranged on other side surfaces (e.g., the third side surface or the fourth side surface) of the LED module 10 where the side wiring 280 is not provided.

The reference electrode may be included in at least one of the signal wiring layer and the driving signal wiring layer. In addition, the conductive pattern layer may be provided to be electrically connected to the reference electrode.

The implementation of the conductive pattern described in fig. 9A to 11B is only an example, and the conductive pattern according to the present disclosure may have various other forms and implementations as long as the conductive pattern can eliminate ESD by being connected to a ground.

Fig. 12 is a sectional view illustrating a conductive pattern connected to an external component according to an embodiment, and fig. 13 is a block diagram of a display device according to an embodiment.

Referring to fig. 12 and 13, the conductive pattern 600 may be formed on at least one surface of the second substrates P2-1 and P2-2. In addition, at least one surface of the second substrates P2-1 and P2-2 may include a conductive plate P4. The conductive pattern 600 may be connected to ground by being connected to the conductive plate P4.

In addition, the ESD applied to the LED module 10 may be connected to the external component 700 via the conductive pattern 600. According to an embodiment, the external component 700 may be provided as a power source provided in the display device.

As shown in fig. 13, the display device 1 may include a plurality of LED modules 10, a conductive pattern 600, and an external member 700. The external components 700 may include a power supply 710 and a signal processor 720. The power supply 710 may be provided as a power supply device, such as a Switching Mode Power Supply (SMPS), for supplying power to drive the plurality of LED modules 10, and the signal processor 720 may be provided with a plurality of input signal ports for receiving external signals and a processor.

Therefore, according to an embodiment, the conductive pattern 600 may not be electrically connected to a component included in the LED module 10, but electrically connected to the ground of the external component 700.

The form of the external assembly 700 is not limited thereto as long as the external assembly 700 is connected to the ground.

The external component 700 may be connected to ground through the conductive pattern 600 and the reference electrode 250-2.

According to another embodiment, the external assembly 700 may be connected to the ground through the signal wiring layer and the flexible printed circuit board.

Further, since the ESD is transmitted to the conductive plate P4 provided on the rear surface of the glass substrate, the LED and the signal electrode provided in the LED module 10 can be prevented from being damaged.

The conductive plate P4 may be connected to a ground provided in another substrate in the display device 1. By using such a structure, the conductive plate P4 may prevent ESD from being transferred back to the first and second substrates P1 and P2-1 and P2-2. Fig. 12 shows that the conductive plate P4 is formed on the rear surface of the LED module 10, but is not limited thereto. Therefore, the conductive plate P4 may be formed on any surface of the LED module 10.

That is, the conductive pattern 600 may be connected to ground through the external component 700 configured to ground the reference electrode 250-2.

According to the embodiments of the present disclosure described above, the display device and the LED module may prevent damage to the LED, which may be caused by electrostatic discharge, by implementing the conductive pattern in the LED module.

The present disclosure may be embodied in the form of a computer-readable recording medium storing instructions executable by a processor (or a computer). The instructions may be stored in the form of program code and, when executed by a processor, may generate program modules to perform the operations of the embodiments. The computer-readable recording medium may be embodied as a computer-readable recording medium.

The non-transitory computer-readable recording medium includes all kinds of recording media in which instructions that a computer can decode are stored. For example, there may be Read Only Memory (ROM), Random Access Memory (RAM), magnetic tape, magnetic disk, flash memory, and optical data storage devices.

Although a few embodiments of the present disclosure have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the disclosure, the scope of which is defined in the claims and their equivalents.

Claims

1. A light emitting diode, LED, module comprising:

an integrated substrate, comprising:

a plurality of LEDs;

a glass substrate; and

a signal wiring layer disposed on the glass substrate, the signal wiring layer including: a plurality of signal electrodes configured to provide data signals to the plurality of LEDs, and a plurality of reference electrodes configured to ground the plurality of LEDs; and

a conductive pattern disposed on at least one surface of the integration substrate and connected to at least one of the plurality of reference electrodes or to ground.

2. The LED module of claim 1, wherein the integrated substrate further comprises a first substrate, and

wherein the plurality of LEDs are disposed on the first substrate, and

wherein at least a portion of the conductive pattern is disposed on at least one side surface of the first substrate.

3. The LED module of claim 1, wherein the integrated substrate further comprises a second substrate,

wherein the signal wiring layer further includes a plurality of scan lines and a plurality of data lines disposed on the second substrate, and

wherein the conductive pattern is disposed on at least one surface of the second substrate.

4. The LED module of claim 1, further comprising:

a plate on a surface of the glass substrate, the plate being connected to the conductive pattern, and

wherein the conductive pattern is connected to ground through the board.

5. The LED module of claim 1, wherein said signal wiring layer further comprises:

at least one via hole penetrating through the glass substrate; and is

Wherein the conductive pattern is connected to the plurality of reference electrodes through the at least one via and to ground through at least one of the plurality of reference electrodes.

6. The LED module of claim 1, wherein said conductive pattern is electrically isolated from said plurality of LEDs and said plurality of signal electrodes.

7. The LED module of claim 1, wherein said conductive pattern is connected to ground through an external component.

8. A Light Emitting Diode (LED) module stacked with at least one layer, comprising:

a glass substrate including a pair of surfaces and a plurality of side surfaces surrounding the pair of surfaces;

an upper layer disposed on the glass substrate to fix a plurality of Light Emitting Diodes (LEDs), and including an upper signal wiring layer including: a plurality of signal electrodes configured to provide data signals to a plurality of LEDs, and a plurality of reference electrodes configured to ground the plurality of LEDs;

a lower layer including a lower signal wiring layer connected to the upper signal wiring layer, the lower signal wiring layer being disposed below the glass substrate;

a side wiring disposed on at least one first surface of the LED module and configured to connect the upper signal wiring layer to the lower signal wiring layer; and

a conductive pattern disposed on at least one second surface of the LED module different from the at least one first surface, the conductive pattern being connected to at least one of the plurality of reference electrodes.

9. The LED module of claim 8, wherein at least a portion of said conductive pattern is disposed on at least one side surface of said upper signal wiring level.

10. The LED module of claim 8, wherein at least a portion of said conductive pattern is disposed on at least one side surface of said lower signal wiring level.

11. The LED module of claim 8, further comprising:

at least one plate disposed on a surface of the glass substrate and connected to the conductive pattern,

wherein the conductive pattern is connected to ground through the at least one plate.

12. The LED module of claim 8, wherein the glass substrate comprises a first surface surrounded by four side surfaces and a second surface opposite the first surface,

wherein at least one via hole penetrating the first surface and the second surface is formed on the glass substrate,

wherein the conductive pattern is connected to at least one of the plurality of reference electrodes through the at least one via.

13. The LED module of claim 8, wherein said conductive pattern is electrically isolated from said plurality of LEDs and said plurality of signal electrodes.

14. A light emitting diode, LED, module comprising:

a glass substrate including a pair of surfaces and four side surfaces between the pair of surfaces;

a plurality of Light Emitting Diodes (LEDs) arranged on an upper surface of the glass substrate;

a signal wiring layer electrically connected to the plurality of LEDs;

a driving signal wiring layer disposed on a lower surface of the glass substrate;

a side wiring provided on a first side surface of the glass substrate and a second side surface of the glass substrate, the second side surface facing the first side surface, the side wiring configured to electrically connect the signal wiring layer to the driving signal wiring layer; and

a conductive pattern disposed on a third side surface of the glass substrate and a fourth side surface of the glass substrate, the third side surface and the fourth side surface being different from the first side surface and the second side surface, the third side surface facing the fourth side surface, and the conductive pattern being connected to a ground.

15. The LED module of claim 16, wherein a reference electrode is included in at least one of said signal wiring layer and said drive signal wiring layer, and

wherein the conductive pattern is electrically connected to the reference electrode.