CN113725236A - Display substrate and display device - Google Patents
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- CN113725236A CN113725236A CN202111049451.0A CN202111049451A CN113725236A CN 113725236 A CN113725236 A CN 113725236A CN 202111049451 A CN202111049451 A CN 202111049451A CN 113725236 A CN113725236 A CN 113725236A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- Condensed Matter Physics & Semiconductors (AREA)
- Theoretical Computer Science (AREA)
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Abstract
The present disclosure provides a display substrate and a display device, the display substrate includes: a gate line, a data line and a gate driving circuit; the gate line includes: a plurality of transverse gate lines crossing the data lines to define a plurality of sub-pixels, and a plurality of longitudinal gate lines parallel to the data lines; the number of the longitudinal grid lines is less than or equal to that of the transverse grid lines, and one longitudinal grid line is connected to the corresponding transverse grid line; the display substrate comprises a display area and a peripheral area located on the periphery of the display area, the peripheral area comprises a binding side and a binding opposite side opposite to the binding side, the grid driving circuit comprises a first grid driving unit located on the binding side or the binding opposite side, and the longitudinal grid line is connected with the first grid driving unit. The display substrate and the display device provided by the disclosure can further narrow the frame of a display product.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display substrate and a display device.
Background
An Active-matrix organic light emitting diode (AMOLED) display has the advantages of Active light emission without a backlight source, high contrast, flexibility and the like, and is very likely to become a next generation display technology. The Array substrate line driving (GOA) technology is a technology for integrating a Gate driving Circuit (IC) of a display device On an Array substrate, and the GOA technology can reduce the usage amount of the IC, thereby reducing the production cost and power consumption of the product, and can also realize the narrow frame of the display device. However, how to narrow the frame further on the basis of the prior art becomes a problem to be solved urgently.
Disclosure of Invention
The embodiment of the disclosure provides a display substrate and a display device, which can further narrow a frame of a display product.
The technical scheme provided by the embodiment of the disclosure is as follows:
an embodiment of the present disclosure provides a display substrate, including: a gate line, a data line and a gate driving circuit; the gate line includes: a plurality of transverse gate lines crossing the data lines to define a plurality of sub-pixels, and a plurality of longitudinal gate lines parallel to the data lines; the number of the longitudinal grid lines is less than or equal to that of the transverse grid lines, and one longitudinal grid line is connected to the corresponding transverse grid line;
the display substrate comprises a display area and a peripheral area located on the periphery of the display area, the peripheral area comprises a binding side and a binding opposite side opposite to the binding side, the grid driving circuit comprises a first grid driving unit located on the binding side or the binding opposite side, and the longitudinal grid line is connected with the first grid driving unit.
Illustratively, the number of the longitudinal grid lines is the same as that of the transverse grid lines, and one longitudinal grid line is connected to a corresponding transverse grid line.
Illustratively, the number of the longitudinal gate lines is less than the number of the transverse gate lines, and the gate driving circuit further comprises at least one second gate driving unit, wherein at least a part of the transverse gate lines which are not connected with the longitudinal gate lines are connected to the second gate driving unit.
Illustratively, the display substrate further comprises: and the gate driving circuit is connected with the driving chip through a gate driving signal line.
Illustratively, the gate driving signal lines are disposed in the peripheral region around the display region.
Illustratively, on the opposite binding side, the peripheral region includes a gate driving circuit region and a bending region located between the display region and the gate driving circuit region, and the first gate driving unit is disposed in the gate driving circuit region; the longitudinal grid line is connected with the first grid driving unit through the routing on the bending area.
Illustratively, the bending region is bent from the display surface to the non-display surface of the display substrate to fold the gate driving circuit region to the non-display surface side of the display substrate.
Illustratively, the display substrate comprises an encapsulation layer, and the encapsulation layer does not cover and encapsulate the bending region and the gate driving circuit region.
Illustratively, the display substrate further comprises a power line, one end of the power line is connected to the driving chip, the other end of the power line extends along the peripheral region and is connected to the driving chip, and the power line is wound on one side of the gate driving signal line far away from the display region.
Illustratively, the display substrate comprises an encapsulation layer which covers and encapsulates the gate driving circuit area.
Exemplarily, the display substrate further includes a power line having one end connected to the driving chip and the other end extending along the peripheral region to be connected to the driving chip;
and the power line is positioned at one side of the bending area close to the display area and is positioned at one side of the second grid driving signal line far away from the display area.
For example, the transverse gate lines and the longitudinal gate lines are arranged in different layers, an insulating layer is arranged between the longitudinal gate lines and the transverse gate lines, and the longitudinal gate lines and the corresponding transverse gate lines are connected through via holes in the insulating layer.
The embodiment of the disclosure also provides a display device, which comprises the display substrate provided by the embodiment of the disclosure.
The beneficial effects brought by the embodiment of the disclosure are as follows:
according to the display substrate and the display device provided by the embodiment of the disclosure, at least a part of a gate driver circuit (GOA) is designed on a binding side (i.e., a lower side of the display substrate) or a binding opposite side (i.e., an upper side of the display substrate) of the display substrate, so that the gate driver circuit arrangement space of the frames on the left and right sides of the display substrate can be reduced, thereby reducing the frame width, and for high-frequency setting, since the GOA circuit size needs to be greatly increased in order to increase the driving frequency, the display substrate provided by the embodiment of the disclosure does not cause a large frame width and can be small even if the GOA size is greatly increased by designing at least a part of the GOA circuit on the upper side, and even does not affect the frame width.
Drawings
Fig. 1 is a wiring diagram of a display substrate in the related art;
FIG. 2 illustrates a wiring schematic of a display substrate in some embodiments of the present disclosure;
FIG. 3 is a schematic diagram of the layout of a display substrate before bending in a bending region according to another embodiment of the disclosure;
FIG. 4 is a schematic diagram of the layout of a display substrate after bending in a bending region according to another embodiment of the disclosure;
FIG. 5 is a schematic diagram of the layout of a display substrate after bending in a bending region according to another embodiment of the disclosure;
fig. 6 is a schematic wiring diagram of a display substrate after bending in a bending region according to another embodiment of the disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
Before a detailed description of the display substrate provided by the embodiments of the present disclosure, it is necessary to make the following description of the related art:
in the related art, the full-screen can provide an excellent visual experience, so that the market demand for an extremely narrow bezel is gradually increased. The gate driving circuit (GOA circuit) is integrally transferred from the IC to the AMOLED display panel, so that the AMOLED display panel has a narrower frame. The gate driving circuit is generally formed by cascading a plurality of GOA units, each GOA unit corresponds to a row of pixel regions, each pixel region includes a plurality of sub-pixel regions, each sub-pixel region has a thin film transistor formed therein, gates of the plurality of thin film transistors in the row of pixel regions are connected, an output end of the GOA unit may be connected to a gate of a thin film transistor in the plurality of thin film transistors, the thin film transistor is close to the GOA unit, and the GOA unit may control on and off of the plurality of thin film transistors in the row of pixel regions according to a level of a potential of a driving signal output by the GOA unit.
Taking the AMOLED display substrate as an example, as shown in fig. 1, the display substrate includes a display area AA and a peripheral area, the peripheral area further includes a binding area and a binding opposite side opposite to the binding area, the binding area is located on a lower side of the display screen, the binding opposite side is an upper side of the display screen, the gate lines are transversely disposed, and gate driver circuits (GOAs) 2 are disposed on a left side and a right side of the display area and connected to the gate lines.
Peripheral traces, such as power lines, including a VSS line (low voltage signal line) 3, a VDD line, a Vint line (initial voltage line) 4, and the like, are also provided in the peripheral region. Due to the low cost of the gate driving circuit GOA and VSS line overlap limitation, the VSS line 3 width needs to be large enough to make the frame incompressible, and the higher PPI (pixel density Per inc) products require more space for GOA wiring, which results in increased frame.
In order to solve the problem that the frame is further narrowed and limited, embodiments of the present disclosure provide a display substrate and a display device, which can achieve the purpose of further narrowing the frame.
FIG. 2 is a schematic structural diagram of some embodiments of a display substrate provided by the present disclosure; fig. 3 and 4 are schematic structural diagrams of other embodiments of the display substrate provided by the present disclosure.
As shown in fig. 2 to 4, the display substrate provided by the embodiment of the present disclosure includes a substrate 100, wherein a gate line 200, a data line 300 and a gate driving circuit are disposed on the substrate 100; wherein the gate line 200 includes: a plurality of transverse gate lines 210 crossing the data lines 300 to define a plurality of sub-pixels, and a plurality of longitudinal gate lines 220 parallel to the data lines 300; the number of the longitudinal grid lines 220 is less than or equal to that of the transverse grid lines 210, and one longitudinal grid line 220 is connected to a corresponding transverse grid line 210 which is crossed with the longitudinal grid line 220; the display substrate includes a display area AA and a peripheral area B located at the periphery of the display area AA, the peripheral area B includes a binding side and a binding opposite side opposite to the binding side, the gate driving circuit includes a first gate driving unit 410 (i.e., a first GOA unit) located at the binding side or the binding opposite side, and the longitudinal gate line 220 is connected to the first gate driving unit 410.
It should be noted that, here, the longitudinal gate line is parallel to the data line, which means that the extending directions of the longitudinal gate line and the data line are substantially the same, and the specific routing directions of the longitudinal gate line and the data line are covered in a reasonable range, and are not limited to the completely consistent case.
For convenience of description, in the following embodiments, a binding region is located on a lower side of the display screen, a binding opposite side is an upper side of the display screen, and two opposite sides located between the upper side and the lower side are a left side and a right side.
In the above scheme, the GOA routing is rearranged, and at least a part of the GOA is moved to the upper side or the lower side of the display substrate, so as to achieve the purpose of reducing the frame.
Specifically, at least a part of the gate driver circuit (GOA circuit) is designed on the binding side (i.e., the lower side of the display substrate) or the binding opposite side (i.e., the upper side of the display substrate) of the display substrate, so that the gate driver circuit layout space of the left and right side frames of the display substrate can be reduced, and thus the frame width can be reduced; moreover, for the high frequency setting, since the size of the GOA circuit needs to be greatly increased in order to increase the driving frequency, the display substrate provided in the embodiment of the disclosure can be small without causing a large frame width even though the size of the GOA is greatly increased by designing at least a part of the GOA circuit on the upper side.
In the display substrate provided by the present disclosure, a vertical gate line 220 is additionally provided, at least a portion of the horizontal gate line 210 is connected to the vertical gate line 220, and is connected to a first gate driving unit located on a binding opposite side of the display substrate, wherein to avoid interference between the vertical gate line 220 and other signal lines, the vertical gate line 220 may be disposed on a layer different from the horizontal gate line 210, and in an actual manufacturing process of the display substrate, a Mask process (i.e., a patterning process) may be added to separately form the vertical gate line 220.
For example, an insulating layer is disposed between the longitudinal gate lines 220 and the transverse gate lines 210, and the longitudinal gate lines 220 and the corresponding transverse gate lines 210 are connected through via holes in the insulating layer.
As shown in fig. 2 and 4, the number of the vertical gate lines 220 and the arrangement period of the vertical gate lines 220 (i.e., every several rows of the horizontal gate lines 210 are connected to the vertical gate lines 220) may be designed according to actual requirements, and are not limited herein.
It should be noted that, in the embodiment of the present disclosure, a part of the GOA circuits may be disposed on the upper side of the display substrate, and another part of the GOA circuits may be disposed on at least one of the left side and the right side, at this time, the driving timings of the GOA circuits on the left side and the right side and the GOA circuit on the upper side should be well matched according to the row number of the horizontal Gate line 210 connected to the vertical Gate line 220, and the driving IC is required to write Data signals (Data line signals) and corresponding EM/Gate (Gate scanning signal lines) into the Gate lines, so as to ensure normal writing.
The display substrate provided by the embodiments of the present disclosure is exemplarily described in more detail below.
As shown in fig. 3, in some embodiments of the present disclosure, the number of the vertical gate lines 220 is the same as the number of the horizontal gate lines 210, and one vertical gate line 220 is connected to a corresponding one of the horizontal gate lines 210; the display substrate further includes: the driving chip (driving IC)500 is disposed on the bonding side, the gate driving circuit is connected to the driving chip 500 through a gate driving signal line (i.e., a GOA signal line) 600, and the gate driving signal line 600 is disposed in the peripheral area B around the display area AA.
In the above scheme, the GOA circuit is only disposed on the upper side of the display substrate, that is, the GOA circuit is completely moved to the upper side of the display substrate, so that the left and right sides only have the GOA signal line 600 without the GOA circuit, thereby achieving the purpose of reducing the width of the left and right side frames.
In the above embodiment, in the aspect of driving the Gate lines 200, the vertical Gate lines 220 are connected to the horizontal Gate lines 210 through via holes, and the driving timings of the first Gate driving units 410 on the upper side and the horizontal Gate lines 210 in each row need to be matched, so that the Data signals written by the driving chip 500 and the corresponding EM/Gate (Gate scanning signal lines) are normally opened, thereby ensuring normal writing.
In addition, in the embodiment of the present disclosure, in order to further reduce the width of the upper frame, as shown in fig. 3 and 4, at the binding opposite side, the peripheral region B includes a gate driving circuit region B1 and a bending region B2 located between the display region AA and the gate driving circuit region B1, and the first gate driving unit is disposed in the gate driving circuit region; the vertical gate line 220 is connected to the first gate driving unit 410 through a trace on the bending region B2; the bending region B2 is bent from the display surface to the non-display surface of the display substrate to fold the gate driving circuit region B1 to the non-display surface side of the display substrate.
By adopting the scheme, the GOA circuit is only arranged on the upper side of the display substrate, namely, the GOA circuit is completely moved to the upper side of the display substrate, so that the left side and the right side only have GOA signal lines without the GOA circuit, and the purpose of reducing the width of the left side frame and the right side frame is achieved; meanwhile, a Bending area B2(Bending area) is added on the upper side of the display substrate for wiring layout, so that the GOA circuit can be folded to one side of the non-display surface of the display substrate without occupying the frame space of the display substrate, and the purpose of further reducing the frame is achieved. Moreover, for the high frequency setting, since the size of the GOA circuit needs to be greatly increased in order to increase the driving frequency, the display substrate provided by the embodiment of the disclosure does not affect the frame width even if the size of the GOA is greatly increased by designing at least a part of the GOA circuit on the upper side.
In addition, in the exemplary embodiment, since the gate driving circuit region B1 and the bending region B2 are folded to the non-display side of the display substrate, the display substrate includes the encapsulation layer 800, and the encapsulation layer 800 does not cover and encapsulate the bending region B2 and the gate driving circuit region B1.
In the present exemplary embodiment, as shown in fig. 3 and 4, the display substrate further includes a power line 700. In some embodiments, the package substrate of the package layer 800 may be multiplexed by a VSS line 700, one end of the power line 700 is connected to the driving chip 500, the other end extends along the peripheral region B to be connected to the driving chip 500, and the power line 700 surrounds the gate driving signal line 600 on a side away from the display region AA.
As shown, in some embodiments, the power line 700 may include a low voltage signal VSS line 700, a VDD line, etc., wherein the VSS line may be routed in an "Jiong" shape in the peripheral region B of the display substrate.
In addition, in some embodiments, the Gate driving circuit may be a bidirectional Gate driving circuit including a bidirectional scanning Gate/Reset (Reset signal) GOA circuit, a bidirectional scanning Emission (Gate scanning) GOA circuit.
In addition, in some embodiments, the VDD lines in the display area AA include a vertical VDD line and a horizontal VDD line, and the vertical VDD line and the horizontal VDD line are arranged to cross each other.
The following is a comparison between the frame trace layout space of the display substrate in the present exemplary embodiment and the frame trace layout space of the display substrate in the related art, and the following table 1 is obtained:
TABLE 1
In the above table 1, AA-Vint refers to a distance between the display area AA and the initial voltage Vint line, and Vint-GOA refers to a distance between the initial voltage Vint line and the GOA circuit; GOA-VSS refers to the distance between the GOA circuit and the low voltage signal VSS line 700; VSS-panel edge refers to the distance between the VSS line 700 in the peripheral region B and the edge of the display substrate; the Vint-GOA signal line refers to the distance between an initial voltage Vint line and a GOA circuit signal line; the GOA signal line-VSS refers to a distance between the GOA circuit signal line and the low voltage signal VSS line 700.
As can be seen from table 1 above, the GOA, Vint, and VSS wiring lines are rearranged, the GOA is completely moved to the upper side of the display substrate, the left and right sides only have the scanning signal lines of the GOA circuit, and the Bending area B2(Bending area) wiring layout is added to the upper side of the display substrate, so that the GOA circuit can be folded to the back of the panel after the display substrate is completed, the panel space is not occupied, and the purpose of reducing the frame is achieved.
Taking the data in table 1 as reference, the frame width can be further reduced by moving part of the GOA to the upper side of the display substrate under the same circuit width, so that the frame is reduced from 2.5mm to 1.7 mm.
Fig. 2 is a schematic structural diagram of other embodiments of the present disclosure.
As shown in fig. 2, in other exemplary embodiments, the number of the vertical gate lines 220 is less than the number of the horizontal gate lines 210, and the gate driving circuit further includes at least one second gate driving unit 420, wherein at least a portion of the horizontal gate lines 210 that are not connected to the vertical gate lines 220 are connected to the second gate driving unit 420. That is, in the present exemplary embodiment, the gate driving circuits are respectively disposed on at least one side and an upper side of the left and right sides of the display substrate.
In the present exemplary embodiment, as shown in fig. 2, the display substrate further includes: the gate driving circuit is connected to the driving chip 500 at the binding side through a gate driving signal line 600, and the gate driving signal line 600 is disposed in the peripheral area B around the display area AA.
In addition, in the present exemplary embodiment, as shown in fig. 2, the display substrate further includes a power line 700, for example, a low voltage signal VSS line, a VDD line, etc., one end of the power line 700 is connected to the driving chip 500, the other end extends along the peripheral region B to be connected to the driving chip 500, and the power line 700 surrounds a side of the gate driving signal line 600 away from the display region AA.
As shown in fig. 2, in some embodiments, the power line 700 includes a low voltage signal VSS line, and the low voltage signal VSS line 700 is routed in an "Jiong" shape in the peripheral region B of the display substrate.
In addition, in some embodiments, the Gate driving circuit may be a bidirectional Gate driving circuit including a bidirectional scanning Gate/Reset (Reset signal) GOA circuit, a bidirectional scanning Emission (Gate scanning) GOA circuit.
In addition, in some embodiments, the VDD lines in the display area AA include a vertical VDD line and a horizontal VDD line, and the vertical VDD line and the horizontal VDD line are arranged to cross each other.
Further, as shown in fig. 2, in the present exemplary embodiment, the display substrate includes an encapsulation layer 800, and the encapsulation layer 800 covers and encapsulates the gate driving circuit region B1.
It should be noted that, in the present exemplary embodiment, the first gate driving unit 410 on the upper side of the display substrate is covered and encapsulated by the encapsulation layer 800, in other embodiments, the peripheral region B on the upper side of the display substrate may include a gate driving circuit region and a bending region B2 between the gate driving circuit region and the display region AA, and the first gate driving unit is disposed in the gate driving circuit region; the vertical gate line 220 is connected to the first gate driving unit 410 through a trace on the bending region B2; the bending region B2 is bent from the display surface to the non-display surface of the display substrate to fold the gate driving circuit region to the non-display surface side of the display substrate.
Therefore, the GOA circuits are arranged on the upper side and the left and right sides of the display substrate, so that the purpose of reducing the width of the left and right side frames is achieved; meanwhile, a Bending area B2(Bending area) is added on the upper side of the display substrate for wiring layout, so that the GOA circuit can be folded to one side of the non-display surface of the display substrate without occupying the frame space of the display substrate, and the purpose of further reducing the frame is achieved. Moreover, for the high frequency setting, since the size of the GOA circuit needs to be greatly increased in order to increase the driving frequency, the display substrate provided by the embodiment of the disclosure does not affect the frame width even if the size of the GOA is greatly increased by designing at least a part of the GOA circuit on the upper side.
The following is a comparison between the frame trace layout space of the display substrate in the present exemplary embodiment and the frame trace layout space of the display substrate in the related art, and the following table 2 is obtained:
TABLE 2
| Item | AA-Vint | Vint-GOA | GOA-VSS | VSS-panel edge | Frame gathers |
| Design size in related art (μm) | 100 | 1000 | 1000 | 400 | 2500 |
| Item | AA-Vint | Vint-GOA | GOA-VSS | VSS-Panel edge | |
| The present embodiment shows a design size of a substrate (μm) | 100 | 600 | 1000 | 400 | 2100 |
In the above table 2, AA-Vint refers to a distance between the display area AA and the initial voltage Vint line, and Vint-GOA refers to a distance between the initial voltage Vint line and the GOA circuit; GOA-VSS refers to the distance between the GOA circuit and the low voltage signal VSS line 700; the VSS-panel edge refers to the distance between the VSS line 700 in the peripheral region B and the edge of the display substrate.
As can be seen from table 2 above, with the data in table 2 as a reference, the frame width can be further reduced by moving part of the GOA to the upper side of the display substrate under the same circuit width, so that the frame is reduced from 2.5mm to 2.1 mm.
In addition, as shown in fig. 5, in some exemplary embodiments of the present disclosure, the vertical gate line 200 and the corresponding transverse gate line are connected by a via, the via is an electrical connection position between the vertical gate line and the transverse gate line, and the extending length of the vertical gate line 220 may extend from the electrical connection position to the first gate driving unit 410.
In other embodiments, as shown in fig. 6, the vertical gate line 220 may be divided into two parts by being disconnected near the electrical connection position, that is, a first part 221 connected to the first gate driving unit 410, and a second part 222 disconnected from the first part 221, wherein the second part 222 may be a dummy line (dummy); alternatively, the second portion 222 may also access the VDD signal to improve the uniformity of the VDD signal.
In addition, it should be noted that the display substrate includes a source and drain metal layer, and the pattern of the source and drain metal layer includes a source, a drain, a data line, and the like of the thin film transistor, where the longitudinal gate line 220 may be formed by patterning with the source and drain metal layer, or the longitudinal gate line 220 may also be formed by using other conductive film layers, such as a light-shielding metal layer on the display substrate.
It should be noted that the display substrate provided in the embodiments of the present disclosure may be an AMOLED display substrate, but is not limited to the AMOLED substrate, and may also be an AMQLED substrate, for example.
In addition, the embodiment of the disclosure also provides a display device which comprises the display substrate provided by the embodiment of the disclosure. The display device may be various display products including a mobile phone, a tablet, a monitor, a television, and the like.
The following points need to be explained:
(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.
(2) For purposes of clarity, the thickness of layers or regions in the figures used to describe embodiments of the present disclosure are exaggerated or reduced, i.e., the figures are not drawn on a true scale. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.
(3) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.
The above is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be determined by the scope of the claims.
Claims (13)
1. A display substrate, comprising: a gate line, a data line and a gate driving circuit; wherein the gate line includes: a plurality of transverse gate lines crossing the data lines to define a plurality of sub-pixels, and a plurality of longitudinal gate lines parallel to the data lines; the number of the longitudinal grid lines is less than or equal to that of the transverse grid lines, and one longitudinal grid line is connected to the corresponding transverse grid line;
the display substrate comprises a display area and a peripheral area located on the periphery of the display area, the peripheral area comprises a binding side and a binding opposite side opposite to the binding side, the grid driving circuit comprises a first grid driving unit located on the binding side or the binding opposite side, and the longitudinal grid line is connected with the first grid driving unit.
2. The display substrate of claim 1,
the number of the longitudinal grid lines is the same as that of the transverse grid lines, and one longitudinal grid line is connected to the corresponding transverse grid line.
3. The display substrate of claim 1,
the number of the longitudinal grid lines is less than that of the transverse grid lines, the grid driving circuit further comprises at least one second grid driving unit, and at least one part of the transverse grid lines which are not connected with the longitudinal grid lines is connected to the second grid driving unit.
4. The display substrate according to claim 2 or 3,
the display substrate further includes: and the gate driving circuit is connected with the driving chip through a gate driving signal line.
5. The display substrate of claim 4,
the gate driving signal line is disposed in the peripheral region around the display region.
6. The display substrate according to claim 2 or 3,
on the binding opposite side, the peripheral area comprises a grid driving circuit area and a bending area positioned between the display area and the grid driving circuit area, and the first grid driving unit is arranged in the grid driving circuit area; the longitudinal grid line is connected with the first grid driving unit through the routing on the bending area.
7. The display substrate of claim 6,
the bending region is bent from the display surface to the non-display surface of the display substrate so as to fold the gate driving circuit region to one side of the non-display surface of the display substrate.
8. The display substrate of claim 6,
the display substrate comprises a packaging layer, and the packaging layer does not cover and package the bending area and the grid electrode driving circuit area.
9. The display substrate of claim 4,
the display substrate further comprises a power line, one end of the power line is connected to the driving chip, the other end of the power line extends along the peripheral area and is connected to the driving chip, and the power line is located on one side, far away from the display area, of the grid driving signal line.
10. The display substrate of claim 6,
the display substrate comprises a packaging layer, and the packaging layer covers and packages the grid electrode driving circuit area.
11. The display substrate of claim 10,
the display substrate further comprises a power line, one end of the power line is connected to the driving chip, and the other end of the power line extends along the peripheral area and is connected to the driving chip;
and the power line is positioned at one side of the bending area close to the display area and is positioned at one side of the second grid driving signal line far away from the display area.
12. The display substrate of claim 1,
the transverse grid lines and the longitudinal grid lines are arranged on different layers, an insulating layer is arranged between the longitudinal grid lines and the transverse grid lines, and the longitudinal grid lines and the corresponding transverse grid lines are connected through via holes in the insulating layer.
13. A display device comprising the display substrate according to any one of claims 1 to 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111049451.0A CN113725236A (en) | 2021-09-08 | 2021-09-08 | Display substrate and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111049451.0A CN113725236A (en) | 2021-09-08 | 2021-09-08 | Display substrate and display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114420049A (en) * | 2022-01-20 | 2022-04-29 | 电子科技大学 | Ultra-narrow frame structure of display screen |
| WO2023240518A1 (en) * | 2022-06-16 | 2023-12-21 | 京东方科技集团股份有限公司 | Display substrate and display device |
-
2021
- 2021-09-08 CN CN202111049451.0A patent/CN113725236A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114420049A (en) * | 2022-01-20 | 2022-04-29 | 电子科技大学 | Ultra-narrow frame structure of display screen |
| WO2023240518A1 (en) * | 2022-06-16 | 2023-12-21 | 京东方科技集团股份有限公司 | Display substrate and display device |
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