CN113722264B - Communication method between singlechips - Google Patents
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- CN113722264B CN113722264B CN202110976441.5A CN202110976441A CN113722264B CN 113722264 B CN113722264 B CN 113722264B CN 202110976441 A CN202110976441 A CN 202110976441A CN 113722264 B CN113722264 B CN 113722264B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Abstract
The invention provides a communication method between singlechips, which comprises the following steps: receiving a plurality of first levels transmitted by a first singlechip according to a first communication line and a plurality of second levels transmitted by a second communication line; the first level and the second level are high level or low level on average, the high level is represented by binary value 1, and the low level is represented by binary value 0; correspondingly combining the first levels and the second levels to form quaternary values; and combining the four numbers according to the transmission sequence of the first level or the second level to form data information, so as to complete communication. The method and the device effectively improve data transmission, solve the limitation that the prior singlechips can communicate only by adopting UART serial communication and IIC bus, increase the communication mode between singlechips, and are convenient for users to use.
Description
[ field of technology ]
The invention relates to the technical field of communication, in particular to a communication method between singlechips.
[ background Art ]
As is well known, the existing single-chip microcomputer and the single-chip microcomputer generally adopt two-wire communication, such as a universal asynchronous receiver transmitter (UART for short) and an integrated circuit bus (IIC for short). The UART serial port communication directly separates two wires, namely a transmitting wire and a receiving wire, which are equivalent to two wires with high speed and do not affect each other and run on the respective paths, but by adopting the UART serial port communication, the two singlechips must be in advance assigned with baud rate to realize normal communication, i.e. the communication between the two singlechips needs assigned clock pulse to be used for data segmentation. And IIC bus communication uses one line as a data clock line and the other as a data line, and the data line is used for receiving and transmitting data.
Both of the above communications are achieved by binary, wherein the distinction of symbols 0 and 1,0 and 1 is distinguished by the clock pulse. Furthermore, when one byte is transferred, 8 shifts are required for UART serial port communication and IIC bus communication. Since one bit 0 or 1 is transmitted, two time pulses, i.e., 8 shifts of UART serial port communication and IIC bus communication, are required, and 16 corresponding voltage pulses are required. The communication mode is low in efficiency, and the single chip microcomputer between the two communication modes can realize the communication between the two communication modes only by needing a UART serial port or an IIC bus, so that the communication between the single chip microcomputer has limitation.
Accordingly, the prior art is subject to improvement and development.
[ invention ]
The invention aims to provide a communication method between singlechips, which is used for solving the problem that the existing singlechips are limited in that communication between the singlechips is only possible by a UART serial port or an IIC bus, and is used for solving the problem that the existing singlechips are low in communication efficiency.
The technical scheme of the invention is as follows:
in one aspect, the present invention provides a communication method between singlechips, including:
receiving a plurality of first levels transmitted by a first singlechip according to a first communication line and a plurality of second levels transmitted by a second communication line; the first level and the second level are high level or low level, the high level is represented by binary value 1, and the low level is represented by binary value 0;
correspondingly combining the first levels and the second levels to form quaternary values;
and combining the four numbers according to the transmission sequence of the first level or the second level to form data information, so as to complete communication.
Further, in the receiving of the first plurality of levels transmitted by the first single chip microcomputer from the first communication line and the second plurality of levels transmitted by the second communication line,
if the first level transmitted by the first communication line is consistent with the first level transmitted before and the second level transmitted by the second communication line is consistent with the second level transmitted before, detecting whether the voltage on the first communication line is a first preset voltage or detecting whether the voltage on the second communication line is a second preset voltage;
if the voltage on the first communication line is the first preset voltage or if the voltage on the second communication line is the second preset voltage, the first level and the second level are distinguished twice.
Further, before the receiving the first levels transmitted by the first single chip microcomputer from the first communication line and the second levels transmitted by the second communication line, the method further includes the steps of:
the first singlechip splits communication data in a quaternary form to be transmitted into a first level and a second level.
Further, before the first singlechip splits the communication data in the quaternary form to be transferred into the first level and the second level, the method further comprises:
collecting a first voltage of a first communication line and a second voltage of a second communication line;
judging whether the first voltage is a third preset voltage or not, and judging whether the second voltage is a fourth preset voltage or not;
if the first voltage is not the third preset voltage or the second voltage is not the fourth preset voltage, the first voltage is not communicated with the first singlechip U1 or data are sent to the first singlechip.
Further, after the communication is completed, the voltage of the first communication line and the voltage of the second communication line are collected.
Further, the quaternary values include 0, 1, 2, and 3; if the first level transmitted by the first communication line and the second communication line is 0 on the average with the second level, combining to form 0 in the quaternary value; if the first level and the second level sent by the first communication line and the second communication line are 0 and 1 respectively, combining to form 1 in the quaternary value; if the first level and the second level sent by the first communication line and the second communication line are respectively 1 and 0, combining to form 2 in the quaternary value; the first level and the second level are respectively 1 and 1, and then are combined to form 3 in the quaternary value.
On the other hand, the invention also provides a communication device for executing the communication method between the singlechips.
In one aspect, the invention also provides a system for communication between singlechips, which comprises a first communication line, a second communication line, and a first singlechip and a second singlechip for executing the communication method;
one IO pin of the first singlechip is connected with one IO pin of the second singlechip through a first communication line, and the other IO pin of the first singlechip is connected with the other IO pin of the second singlechip through a second communication line; the first singlechip is also respectively connected with a first communication wire and a second communication wire for respectively detecting the voltages of the first communication wire and the second communication wire, and the second singlechip is also respectively connected with the first communication wire and the second communication wire for respectively detecting the voltages of the first communication wire and the second communication wire.
Further, the communication system further comprises a first resistor, a second resistor, a third resistor, a fourth resistor and a power supply end, wherein the power supply end is grounded after passing through the first resistor and the second resistor in sequence, the power supply end is grounded after passing through the third resistor and the fourth resistor in sequence, the first communication line is respectively connected with the output end of the first resistor and the input end of the second resistor, and the second communication line is respectively connected with the output end of the third resistor and the input end of the fourth resistor.
Further, the first singlechip is electrically connected with the first communication line and the second communication line through two AD pins respectively, and the second singlechip is electrically connected with the first communication line and the second communication line through two AD pins respectively.
The invention has the beneficial effects that: compared with the prior art, the invention splits the quaternary value into two binary values and transmits the binary values by utilizing two communication lines respectively, namely, one byte is transmitted, only 4 voltage pulses are needed, the data transmission is effectively improved, and the transmission efficiency can be improved by 2 to 4 times. And can solve all need adopt UART serial port communication and IIC bus between the current singlechip just can communicate the limitation, reduce the condition of communication between the singlechip, the user of being convenient for uses.
[ description of the drawings ]
FIG. 1 is a schematic diagram of a system for communication between singlechips according to the present invention.
FIG. 2 is a flow chart of a communication method between singlechips according to the present invention.
[ detailed description ] of the invention
The invention will be further described with reference to the drawings and embodiments.
Referring to fig. 1, a system for communication between singlechips in an embodiment of the present invention is shown.
The system for communication between the singlechips comprises a first communication line 1, a second communication line 2, a first singlechip U1 and a second singlechip U2. One IO pin IO11 of the first single-chip microcomputer U1 is connected with one IO pin IO21 of the second single-chip microcomputer U2 through a first communication line 1, and the other IO pin IO12 of the first single-chip microcomputer U1 is connected with the other IO pin IO22 of the second single-chip microcomputer U2 through a second communication line 2. The first singlechip U1 is also respectively connected with the first communication line 1 and the second communication line 2 and is used for respectively detecting the voltages of the first communication line 1 and the second communication line 2, and the second singlechip U2 is also respectively connected with the first communication line 1 and the second communication line 2 and is used for respectively detecting the voltages of the first communication line 1 and the second communication line 2.
Because the data IO port on the single chip microcomputer can only identify the logic high level 1 and the logic low level 0, the data transmission between the single chip microcomputer can be realized by utilizing the IO port, and the communication between the two single chip microcomputers is realized.
Based on the communication system between the singlechips, the communication method between the singlechips can be obtained.
Referring to fig. 2, the first single-chip microcomputer U1 sends data to the second single-chip microcomputer U2, wherein the second single-chip microcomputer U2 is used as an operation object for execution, and a communication method between the single-chip microcomputers is described, and specifically includes the following steps:
s10, receiving a plurality of first levels transmitted by the first singlechip U1 according to the first communication line 1 and a plurality of second levels transmitted by the second communication line 2.
Namely, the first single-chip microcomputer U1 sends a plurality of first levels of transmission to the second single-chip microcomputer U2 through the first communication line 1, and sends a plurality of second levels of transmission to the second single-chip microcomputer U2 through the second communication line 2. The first level and the second level are high level or low level, that is, the second single-chip microcomputer U2 can obtain two pulse signals sent from the first single-chip microcomputer U1 through the first communication line 1 and the second communication line 2, so that high level 1 or low level 0 continuously sent from the first single-chip microcomputer U1 can be obtained, the periods of the two groups of pulse signals are the same, the periods are consistent, but the levels may not be consistent.
S20, correspondingly combining the first levels and the second levels to form a plurality of quaternary values.
The second singlechip U2 combines the high level 1 or the low level 0 acquired from the first communication line 1 and the second communication line 2 respectively, wherein the combined first level and the period of the second level are consistent and correspondingly combined. If the first level and the second level sent by the first communication line 1 and the second communication line 2 are 0, the corresponding combination forms 0 in the quaternary value; if the first level and the second level sent by the first communication line 1 and the second communication line 2 are respectively 0 and 1, correspondingly combining to form 1 in the quaternary value; if the first level and the second level sent by the first communication line 1 and the second communication line 2 are respectively 1 and 0, correspondingly combining to form 2 in the quaternary numerical value; if the first level transmitted by the first communication line 1 and the second communication line 2 is equal to 1 with the second level, the first level and the second level are combined to form 3 in the quaternary values, namely, the existing quaternary values are corresponding to 0, 1, 2 and 3.
S30, combining the four numbers according to the transmission sequence of the first level or the second level to form data information, and completing communication.
In order to facilitate understanding of the above technical solution, an example will now be described. For example, the first single-chip microcomputer U1 transmits a decimal 238 to the second single-chip microcomputer U2 through the first communication line 1 and the second communication line 2, and the quaternary is 3232, and the first single-chip microcomputer U1 divides the quaternary 3 into a first level and a second level in advance, namely two binary 1; splitting the quaternary 2 into a first level and a second level, namely 0 and 1 of binary, and transmitting the split binary values through the first communication line 1 and the second communication line 2, as shown in the following table:
| logic level transferred by first communication line | 1 | 1 | 1 | 1 |
| Logic level transferred by second communication line | 1 | 0 | 1 | 0 |
| Quaternary value | 3 | 2 | 3 | 2 |
And sends the result to the second singlechip U2 according to the sequence of the quaternary system 3232. The second singlechip U2 sequentially executes steps S10, S20, and S30 to combine the first level and the second level sent by the first communication line 1 and the second communication line 2 to form a quaternary 3232, so as to realize data transmission and complete communication.
That is, before the second singlechip U2 executes step S10, the communication method further includes the steps of: the first singlechip U1 splits the communication data in a quaternary form to be transmitted to the second singlechip U2 into a first level and a second level, and transmits the first level and the second level through the first communication line 1 and the second communication line 2 respectively so as to realize communication in the quaternary form between the singlechips.
In an embodiment, in order to prevent the first single-chip microcomputer U1 from transmitting the same quaternary number to the second single-chip microcomputer U2 sequentially and twice, that is, using two first levels transmitted sequentially by the first communication line 1 and two second levels transmitted sequentially by the second communication line 2 to be consistent, that is, the levels transmitted sequentially are consistent and cannot be distinguished by the second single-chip microcomputer U2, so as to inform the second single-chip microcomputer U2 that two same quaternary numbers are transmitted sequentially and facilitate the distinguishing of the second single-chip microcomputer U2. If the voltage on the first communication line is the first preset voltage or the voltage on the second communication line is the second preset voltage, the first level and the second level are divided twice before and after, namely, the first level and the second level are distinguished twice before and after.
Because the high-level voltage transmitted by the first single chip microcomputer U1 is VCC, the low-level voltage is 0V, in order to generate a segmentation signal, the voltage transmitted by the first communication line 1 or the second communication line 2 can be changed, the voltage on the first communication line 1 and the voltage on the second communication line 2 can be detected in real time by utilizing the second single chip microcomputer U2, namely, when the second single chip microcomputer U2 detects that the voltage on the first communication line 1 is the first preset voltage and the voltage on the second communication line 2 is the second preset voltage, the first single chip microcomputer U1 can be judged to sequentially transmit two identical quaternary values. For example, when the first singlechip U1 needs to send a decimal 255, that is, a quaternary 3333, and then needs to divide between every two adjacent quaternary values, as shown in the following table:
therefore, according to the communication method between the singlechips, the quaternary values are split into the two binary values, and the two binary values are transmitted by using the two communication lines, namely one byte is transmitted, so that only four pulses are needed under the condition that data segmentation is not needed, such as 3232, and time pulse assistance is not needed. In the state that one data division is required for each pulse transmission, for example, 3333, only 4 pulses are required, but the data division is realized by using the power supply terminal +vcc in the period, which is equivalent to 8 voltage pulses. However, compared with the prior art that UART serial port communication and IIC bus communication are adopted for communication between single-chip computers, 16 voltage pulses are needed, so that data transmission can be effectively improved, and transmission efficiency is improved by 2 to 4 times. The communication method between the singlechips can solve the limitation that the existing singlechips can only communicate by adopting UART serial communication and IIC bus, so that the communication mode between the singlechips is increased, and the method is convenient for users to use.
In order to generate a voltage different from VCC and 0V on the first communication line 1 or the second communication line 2, the system for communication between the single-chip microcomputer of the present invention further includes: the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4 and the power supply terminal +VCC. The power supply end +VCC is grounded after passing through the first resistor R1 and the second resistor R2 in sequence, the power supply end +VCC is grounded after passing through the third resistor R3 and the fourth resistor R4 in sequence, the first communication line 1 is connected with the output end of the first resistor R1 and the input end of the second resistor R2 respectively, and the second communication line 2 is connected with the output end of the third resistor R3 and the input end of the fourth resistor R4 respectively.
When the split signal is required to be generated, the power supply end +VCC is electrified, namely the first communication line 1 or the second communication line 2 is electrified, the voltage required by the user definition of the first communication line 1 or the second communication line 2 can be input by utilizing the partial pressure of the second resistor R2 and the fourth resistor R4, and the voltage on the first communication line 1 or the second communication line 2 is detected in real time by combining the second singlechip U2, so that the consistency of quaternary values informing the second singlechip U2 of sequential transmission can be realized.
It should be noted that, the voltage of the first preset voltage may be set to be different from VCC and 0V, and the second preset voltage keeps the voltage output by the first singlechip U1 consistent (high level VCC or low level 0V). Or the voltage of the second preset voltage is different from VCC and 0V, and the first preset voltage keeps the voltage output by the first single chip microcomputer U1 consistent (high level VCC or low level 0V), etc., which is not limited herein.
In order to simplify a communication system between the singlechips, the first singlechips U1 are directly and respectively electrically connected with the first communication line 1 and the second communication line 2 through two AD pins, and the second singlechips U2 are directly and respectively electrically connected with the first communication line 1 and the second communication line 2 through two AD pins, so that the voltage on the first communication line 1 and the voltage on the second communication line 2 are detected.
In one embodiment of the communication method between the singlechips, whether the first singlechip U1 transmits data to the second singlechip U2 or the second singlechip U2 transmits data to the first singlechip U1 is confirmed for confirming the communication direction. Before executing step S10, the method further comprises the steps of:
s01, collecting a first voltage of a first communication line 1 and a second voltage on a second communication line 2;
s02, judging whether the first voltage is a third preset voltage or not, and judging whether the second voltage is a fourth preset voltage or not;
s03, if the first voltage is not the third preset voltage or the second voltage is not the fourth preset voltage, not communicating with the first singlechip U1, and continuously detecting the voltage; or sending data to the first singlechip.
When the first single-chip microcomputer U1 and the second single-chip microcomputer U2 are not in communication, namely, the IO pins on the first single-chip microcomputer U1 and the second single-chip microcomputer U2 have no output logic level, and the power supply end +VCC can be utilized to provide a first preset voltage or a second preset voltage different from the logic level for the first communication line 1 and the second communication line 2 through artificial switch or software program control and the like, namely, the third preset voltage and the fourth preset voltage are different from the logic level.
Therefore, the first singlechip U1 and the second singlechip U2 judge that the first singlechip U1 and the second singlechip U2 are not communicated at the moment according to the voltages on the first communication line 1 and the second communication line 2 detected in real time. If the voltages on the first communication line 1 and the second communication line 2 are respectively 0V and voltages different from the logic level, i.e. the first single-chip microcomputer U1 sends data to the second single-chip microcomputer U2; when the first preset voltage or the second preset voltage is different from the voltage of the logic level and 0V respectively, the second single-chip microcomputer U2 sends data and the like to the first single-chip microcomputer, wherein the first preset voltage and the second preset voltage can be defined as required, and the first preset voltage and the second preset voltage are not limited herein.
In addition, in an embodiment, the communication method between the singlechips in the embodiment of the invention further comprises the following steps:
after the communication is completed, detecting that the voltage of the first communication line 1 is a third preset voltage and detecting that the voltage of the second communication line 2 is a fourth preset voltage, and transmitting data to the first single chip microcomputer U1 through the first communication line 1 and the second communication line 2.
After the first single-chip microcomputer U1 transmits data to the second single-chip microcomputer U2, after the communication is completed, the first single-chip microcomputer U1 and the second single-chip microcomputer U2 do not have communication, and according to the mode, the power supply end +VCC can provide a voltage for the first communication line 1 and the second communication line 2 through manual switching or software program control and the like, namely, a third preset voltage and a fourth preset voltage, namely, the third preset voltage and the fourth preset voltage are respectively 0V and voltages different from logic levels, namely, the first single-chip microcomputer U1 sends data to the second single-chip microcomputer U2; when the third preset voltage or the sixth preset voltage is different from the logic level and 0V, respectively, the second single-chip microcomputer U2 sends data to the first single-chip microcomputer U2, which is not limited herein.
On the other hand, the embodiment of the invention also provides a communication device for executing the communication method between the singlechips, wherein the communication device is the second singlechip U2. In addition, it should be noted that the communication device may also be the first single chip microcomputer U1, and the "first" and the "second" are only used for distinguishing, so as to explain the technical scheme of the embodiment.
While the invention has been described with respect to the above embodiments, it should be noted that modifications can be made by those skilled in the art without departing from the inventive concept, and these are all within the scope of the invention.
Claims (9)
1. The communication method between the singlechips is characterized by comprising the following steps:
receiving a plurality of first levels transmitted by the singlechip according to the first communication line and a plurality of second levels transmitted by the second communication line; the first level and the second level are high level or low level, the high level is represented by binary value 1, and the low level is represented by binary value 0;
correspondingly combining the first levels and the second levels to form quaternary values;
combining the four numbers according to the transmission sequence of the first level or the second level to form data information, completing communication,
wherein the quaternary values include 0, 1, 2, and 3; if the first level transmitted by the first communication line and the second communication line is 0 on the average with the second level, combining to form 0 in the quaternary value; if the first level and the second level sent by the first communication line and the second communication line are 0 and 1 respectively, combining to form 1 in the quaternary value; if the first level and the second level sent by the first communication line and the second communication line are respectively 1 and 0, combining to form 2 in the quaternary value; if the first level transmitted by the first communication line and the second communication line is 1 with the second level, then the first level and the second level are combined to form 3 in the quaternary value.
2. The method of claim 1, wherein among the first plurality of levels transmitted by the receiving single-chip microcomputer from the first communication line and the second plurality of levels transmitted by the second communication line,
if the first level transmitted by the first communication line is consistent with the first level transmitted before and the second level transmitted by the second communication line is consistent with the second level transmitted before, detecting whether the voltage on the first communication line is a first preset voltage or detecting whether the voltage on the second communication line is a second preset voltage;
if the voltage on the first communication line is the first preset voltage or if the voltage on the second communication line is the second preset voltage, the first level and the second level are distinguished twice.
3. The method for communication between single-chip microcomputer according to claim 2, further comprising the step of, before said receiving the plurality of first levels transmitted by the single-chip microcomputer from the first communication line and the plurality of second levels transmitted by the second communication line:
the singlechip splits the communication data in a quaternary form to be transmitted into a first level and a second level.
4. The method for communication between single-chip computers according to claim 3, further comprising, before the single-chip computer splits the communication data in quaternary form to be transferred into the first level and the second level:
collecting a first voltage of a first communication line and a second voltage of a second communication line;
judging whether the first voltage is a third preset voltage or not, and judging whether the second voltage is a fourth preset voltage or not;
if the first voltage is not the third preset voltage or the second voltage is not the fourth preset voltage, the single chip microcomputer is not communicated with or data is sent to the single chip microcomputer.
5. The method of claim 4, wherein the voltage on the first communication line and the voltage on the second communication line are collected after the communication is completed.
6. A communication device, characterized by being configured to perform a communication method between the singlechips according to any one of claims 1-5.
7. A system for communication between single-chip microcomputer, characterized by comprising a first communication line, a second communication line, a single-chip microcomputer for executing the communication method according to any one of claims 1-5, wherein the single-chip microcomputer comprises a first single-chip microcomputer and a second single-chip microcomputer;
one IO pin of the first singlechip is connected with one IO pin of the second singlechip through a first communication line, and the other IO pin of the first singlechip is connected with the other IO pin of the second singlechip through a second communication line; the first singlechip is also respectively connected with a first communication wire and a second communication wire for respectively detecting the voltages of the first communication wire and the second communication wire, and the second singlechip is also respectively connected with the first communication wire and the second communication wire for respectively detecting the voltages of the first communication wire and the second communication wire.
8. The system of claim 7, wherein the communication system further comprises a first resistor, a second resistor, a third resistor, a fourth resistor and a power supply end, the power supply end is grounded after passing through the first resistor and the second resistor in sequence, the power supply end is grounded after passing through the third resistor and the fourth resistor in sequence, the first communication line is respectively connected with the output end of the first resistor and the input end of the second resistor, and the second communication line is respectively connected with the output end of the third resistor and the input end of the fourth resistor.
9. The system according to claim 8, wherein the first single-chip microcomputer is electrically connected to the first communication line and the second communication line through two AD pins, respectively, and the second single-chip microcomputer is electrically connected to the first communication line and the second communication line through two AD pins, respectively.
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| Noncoherent receivers for multichip differentially encoded DS-CDMA;R. Schober等;《IEEE Transactions on Wireless Communications》;全文 * |
| 单片机与PC机的串行通信设计;孙建鑫;《中国科技信息》;全文 * |
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| CN113722264A (en) | 2021-11-30 |
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