CN113721130A

CN113721130A - Test system abnormal interrupt recovery method and device for wafer test

Info

Publication number: CN113721130A
Application number: CN202111014452.1A
Authority: CN
Inventors: 阚紫为; 杨颖超; 李鹏宇
Original assignee: Zhejiang Quean Technology Co ltd
Current assignee: Zhejiang Quean Technology Co ltd
Priority date: 2021-06-25
Filing date: 2021-08-31
Publication date: 2021-11-30

Abstract

The invention discloses a test system abnormal interruption recovery method and device for wafer testing, and relates to the field of chip manufacturing. The method comprises the following steps: when the test system is abnormally interrupted, reading the stored wafer information from the test machine, and extracting the tested wafer test result from the wafer information; modifying the blank test result graph according to the wafer test result to obtain a partial test result graph; and calling a part of test result graphs through the probe station, and testing the untested part of the wafer according to the part of test result graphs to obtain a complete test result graph. The invention is suitable for test recovery after abnormal interruption of a wafer test system, can enable the probe station to continue to test the rest part of the wafer according to part of the wafer map, and does not need to test the tested area again, thereby reducing the scrappage of products which cannot be retested, reducing the risk of yield reduction after increasing the number of needle marks and improving the yield.

Description

Test system abnormal interrupt recovery method and device for wafer test

Technical Field

The invention relates to the field of chip manufacturing, in particular to a test system abnormal interruption recovery method and device for wafer testing.

Background

In the Chip manufacturing process, each IC Chip must be subjected to a CP (Chip probe, wafer test) before the post-process, and its main functions are to detect problems occurring in the IC Chip manufacturing process and find out reasons, to verify whether the functions of the product are normal, to pick out bad products, and to distinguish performance levels. In the testing process, if the testing system is abnormal, the testing is interrupted, at this time, because the testing is not completed, and the wafer map is not generated, after the fault is eliminated, the probe station does not determine which position of the wafer to continue the testing, and only can give up the tested partial data, and the whole wafer is tested again, so that the complete wafer map is obtained.

However, in the testing process, the probe card needs to be pricked onto the wafer to connect the integrated circuit in the probe card and the wafer, and the tester tests again, so that the tested wafer part needs to be tested repeatedly before a fault occurs, the number of needle marks of the part is increased, and the yield is seriously affected after the number of needle marks of some products is increased; some products can not be retested due to the test program, and can only be tested once, for example, part of the ID can only be burned once, and retesting can cause the first half of the tested piece to be scrapped, so the existing recovery scheme for abnormal interruption of the test system has obvious disadvantages.

Disclosure of Invention

The invention provides a method and a device for recovering abnormal interruption of a test system for wafer test, aiming at the defects of the prior art.

The technical scheme for solving the technical problems is as follows:

a test system abnormal interruption recovery method for wafer test comprises the following steps:

when the test system is abnormally interrupted, reading the stored wafer information from the test machine, and extracting the tested wafer test result from the wafer information;

modifying the blank test result graph according to the wafer test result to obtain a partial test result graph;

and calling the partial test result graph through a probe station, and testing the untested part of the wafer according to the partial test result graph to obtain a complete test result graph.

The recovery method provided by the invention is suitable for test recovery after the abnormal interruption of the wafer test system, and after the abnormal interruption, the wafer information obtained by testing and stored in a hard disk of a test machine is read, then the wafer test result required for constructing the wafer map is extracted, and the blank wafer map is combined to generate the partial wafer map containing the partial test result, so that the probe station can continue to test the rest part of the wafer according to the partial wafer map, the tested area does not need to be tested again, the scrappage of products which cannot be retested is reduced, the risk of yield reduction after the increase of the pin marks is reduced, and the yield is improved.

Based on the technical scheme, the invention can be further improved as follows:

before modifying the blank test result graph according to the wafer test result, the method further comprises the following steps:

and the probe card is not contacted with the wafer, and the wafer is subjected to a whole-wafer test to obtain a connectivity failure test result graph, namely a blank test result graph.

By carrying out the whole-wafer test on the wafer, a blank test result graph can be obtained quickly, a part of test result graphs are generated directly according to the blank test result graph, and the blank test result graphs do not need to be led in from the outside, so that the interrupt recovery efficiency is improved.

the wafer test result comprises: the lot, the serial number, the test coordinate of the wafer and the test result corresponding to the test coordinate.

modifying the blank test result graph according to the wafer test result to obtain a partial test result graph, which specifically comprises the following steps:

and determining a corresponding position in a blank test result graph according to the test coordinate, and modifying a bin value of the corresponding position in the blank test result graph according to the test result of the corresponding test coordinate to obtain a partial test result graph.

calling the partial test result graph through a probe station, and testing the untested part of the wafer according to the partial test result graph to obtain a complete test result graph, wherein the test result graph specifically comprises the following steps:

calling the partial test result graph through a probe station, and determining the position and the direction of starting testing according to the partial test result graph;

and testing the untested part of the wafer according to the position and the direction of the starting test to obtain a complete test result graph.

Another technical solution of the present invention for solving the above technical problems is as follows:

a test system abnormal interruption recovery device for wafer test comprises: reading unit, processing unit and control unit, wherein:

the reading unit is used for reading the stored wafer information from the testing machine and extracting the tested wafer test result from the wafer information after the test system is abnormally interrupted;

the processing unit is used for modifying the blank test result graph according to the wafer test result to obtain a partial test result graph;

the control unit is used for calling the partial test result graph through the probe station and testing the untested part of the wafer according to the partial test result graph to obtain a complete test result graph.

The recovery device provided by the invention is suitable for test recovery after abnormal interruption of a wafer test system, and after the abnormal interruption, the wafer information obtained by testing and stored in a hard disk of a test machine is read, then the wafer test result required for constructing a wafer map is extracted, and a partial wafer map containing partial test results is generated by combining a blank wafer map, so that a probe station can continue to test the rest part of a wafer according to the partial wafer map, the tested area does not need to be tested again, the scrappage of products which cannot be retested is reduced, the risk of yield reduction after increase of pin marks is reduced, and the yield is improved.

the control unit is also used for enabling the probe card not to contact with the wafer, and carrying out the whole-wafer test on the wafer to obtain a connectivity failure test result graph, namely a blank test result graph.

the processing unit is specifically configured to determine a corresponding position in a blank test result graph according to the test coordinate, and modify a bin value of the corresponding position in the blank test result graph according to the test result of the corresponding test coordinate to obtain a partial test result graph.

the control unit is specifically used for calling the partial test result graph through the probe station and determining the position and the direction of starting testing according to the partial test result graph;

Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a flow chart illustrating a test system abort recovery method according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a wafer file according to an embodiment of the method for recovering an abnormal interrupt of a test system according to the present invention;

FIG. 3 is a schematic diagram of a csv file according to an embodiment of the method for recovering from an abnormal interrupt of a test system of the present invention;

FIG. 4 is a schematic diagram of a blank map provided by an embodiment of the method for recovering from an abort of a test system according to the present invention;

FIG. 5 is a partial map diagram provided by an embodiment of the method for recovering from an abort of a test system according to the present invention;

FIG. 6 is a schematic diagram of a complete map provided by an embodiment of the method for recovering from an abort of a test system according to the present invention;

FIG. 7 is a block diagram of an embodiment of an abort recovery device for a test system according to the present invention.

Detailed Description

The principles and features of this invention are described below in conjunction with the following drawings, which are set forth to illustrate, but are not to be construed to limit the scope of the invention.

An IC chip is a chip formed by placing an integrated circuit formed by a large number of microelectronic devices (such as transistors, resistors, capacitors, etc.) on a plastic substrate. The IC chip comprises a wafer chip and a packaging chip, and the corresponding IC chip production line consists of a wafer production line and a packaging production line.

The wafer is a silicon wafer used for manufacturing a silicon semiconductor integrated circuit, and is called a wafer because it has a circular shape. Various circuit element structures can be processed on a silicon wafer to form an IC product with specific electrical functions. Due to the process design or the characteristics of the material itself, the final wafer has normal chips and defective chips. Generally, a test machine, a probe station, and a probe card are used to test each chip on a wafer to ensure that the electrical characteristics and performance of the chip meet the design specifications.

Wafer testing is the first station of semiconductor subsequent packaging testing, which refers to testing the voltage, current, timing sequence and the like of chip grains on a wafer before packaging, and is used for verifying whether each chip meets the product specification. After the wafer test, a wafer map file for displaying the wafer test result distribution can be obtained. The test procedure is briefly described below in connection with a test system.

The test machine is used for placing a wafer, a probe card is fixed on the probe station, a communication end of the probe card is connected to the test machine, the probe station moves the wafer to enable the probe card to be communicated with a part of integrated circuits in the wafer during testing, the test machine starts testing, after the current part of integrated circuits are tested, the probe station moves the wafer to enable the probe card to be communicated with other parts of integrated circuits in the wafer, the test machine starts testing, and the test is carried out sequentially according to the mode until all integrated circuits on the wafer are tested.

In the testing process, the testing machine stores the testing process file in a hard disk in a text format, and after the testing is finished, a wafer map file for displaying the distribution of the wafer testing result is obtained.

After the probe card is stuck on the wafer, a trace, called a needle mark, is left at the corresponding position. If the pin mark is too much and too deep, the IC performance will be damaged. After the existing test system is interrupted, due to the lack of the test results of the rest parts, a complete wafer map cannot be generated, only the complete test can be performed on the whole wafer again, the yield can be seriously influenced after the number of pin marks of part of products is increased, and the retest of part of products cannot be performed.

As shown in fig. 1, a schematic flow chart provided by an embodiment of the method for recovering from abnormal interruption of a test system according to the present invention is shown, where the method for recovering from abnormal interruption of a test system includes:

and S1, when the test system is abnormally interrupted, reading the stored wafer information from the test machine, and extracting the tested wafer test result from the wafer information.

It should be understood that the wafer information is generated during the testing of the wafer by the tester, and usually includes the basic information of the wafer and the tester, and the test result of each die of each wafer, which are stored in the hard disk of the tester in real time in the format of wafer, and can be directly copied and read by using a specific program.

Taking the test of a T2000 series tester as an example, each time 1 TD (Touch Down, test area) is tested, the result is saved locally in the tester.

It should be understood that due to the large size of the wafer, the testing needs to be performed in different regions, and each region is called as 1 TD for testing.

Under the directory of D: \ T2000 Instalk \ tmp \ wafer MapData of the hard disk, the content of the wafer file opened by using notepad + + is shown in FIG. 2.

In fig. 2, the first 12 rows are wafer and tester basic information, starting from row 13 for test results for each die on each wafer. Taking the 13 th row example, W2, X6, Y41, and C17 represent the position test result HardBin of the lot number 2 wafer coordinate (6, 41) as Bin17 and SoftBin 15. Bin represents the test result of each coordinate, different bins of the test result are different, and the meaning of each Bin is different according to products.

The information of the first 12 rows is not much helpful to recovery, so the information of the 13 th and later rows can be extracted as the wafer test result.

It should be understood that testing typically includes voltage, current, and timing tests to verify that each chip meets product specifications.

And S2, modifying the blank test result graph according to the wafer test result to obtain a partial test result graph.

Optionally, a csv file may be generated according to the wafer test result, and as shown in fig. 3, the data in the rows 13 to 21 in fig. 2 are extracted and saved in the csv file in batches by Softbin. In FIG. 3, LOT is LOT, WAFER is WAFER number, X and Y are test coordinates, and BIN is test result.

The csv file may be used to modify a blank test result map, which is a blank map, also referred to as a connectivity failure test result map, or a connectivity failure map, as shown in fig. 4, an exemplary blank map diagram is given, and the dies in the diagram are not tested, so that each die may be set as a default value, and a corresponding position may be modified according to a BIN value of a corresponding coordinate in the csv file. For example, since the blank map has many grains, each grain has a corresponding coordinate, assuming that the coordinate (6, 41) is bin15, the grain at the coordinate (6, 41) in the blank map is changed to bin 15.

The modified map is a partial map, which is also called a partial test result map. As can be seen from the figure, the grains on the left have been modified. In actual operation, in order to distinguish different test results, different values of BIN may be displayed in different colors to visually distinguish different test results.

And S3, calling a part of test result graph through the probe station, and testing the untested part of the wafer according to the part of test result graph to obtain a complete test result graph.

As can be seen from fig. 5, after the partial map is obtained from the subsequent start position and test direction, the partial map is placed on the probe station to call the map, and the start position of the second half of the start position is set, and the test direction is downward, so that the test can be started. Specifically, the probe station is manually operated, the wafer is moved to the starting position of the rear half wafer, the determining button is clicked, the testing direction is modified downwards, and the starting button is clicked to start testing.

The complete map, i.e. the complete test result map, after testing is shown in fig. 6.

The recovery method provided by the embodiment is suitable for test recovery after the abnormal interruption of the wafer test system, and after the abnormal interruption, the wafer information obtained by testing and stored in the hard disk of the test machine is read, then the wafer test result required for constructing the wafer map is extracted, and the partial wafer map containing the partial test result is generated by combining the blank wafer map, so that the probe station can continue to test the rest part of the wafer according to the partial wafer map, the tested area does not need to be tested again, the scrappage of products which cannot be retested is reduced, the risk of yield reduction after the increase of the pin marks is reduced, and the yield is improved.

Optionally, in some possible embodiments, before modifying the blank test result graph according to the wafer test result, the method further includes:

and (4) enabling the probe card not to contact the wafer, and carrying out the whole-wafer test on the wafer to obtain a connectivity failure test result graph, namely a blank test result graph.

Optionally, in some possible embodiments, the wafer test result includes: the lot, the serial number, the test coordinate of the wafer and the test result corresponding to the test coordinate.

Optionally, in some possible embodiments, modifying the blank test result graph according to the wafer test result to obtain a partial test result graph, specifically including:

and determining a corresponding position in the blank test result graph according to the test coordinate, and modifying a bin value of the corresponding position in the blank test result graph according to the test result of the corresponding test coordinate to obtain a partial test result graph.

Optionally, in some possible embodiments, a probe station calls a partial test result diagram, and the untested portion of the wafer is tested according to the partial test result diagram to obtain a complete test result diagram, which specifically includes:

calling a part of test result graphs through a probe station, and determining the position and the direction of starting testing according to the part of test result graphs;

It is to be understood that some or all of the various embodiments described above may be included in some embodiments.

As shown in fig. 7, a structural framework diagram provided for an embodiment of the device for recovering from an abnormal interrupt of a test system according to the present invention is provided, where the device for recovering from an abnormal interrupt of a test system includes: reading unit, processing unit and control unit, wherein:

the reading unit 10 is configured to read stored wafer information from the testing machine and extract a tested wafer test result from the wafer information after the test system is abnormally interrupted;

the processing unit 20 is configured to modify the blank test result graph according to the wafer test result to obtain a partial test result graph;

the control unit 30 is configured to retrieve a part of the test result graph through the probe station, and test the untested part of the wafer according to the part of the test result graph to obtain a complete test result graph.

The recovery device provided by the embodiment is suitable for test recovery after abnormal interruption of a wafer test system, and after the abnormal interruption, by reading wafer information obtained by testing and stored in a hard disk of a test machine, then extracting a wafer test result required for constructing a wafer map, and combining a blank wafer map to generate a partial wafer map containing partial test results, a probe station can continue to test the rest part of a wafer according to the partial wafer map, and the tested area does not need to be tested again, so that scrappage of products which cannot be retested is reduced, the risk of yield reduction after increase of pin marks is reduced, and the yield is improved.

Optionally, in some possible embodiments, the control unit 30 is further configured to perform a full-wafer test on the wafer without the probe card contacting the wafer, so as to obtain a connectivity failure test result map, i.e., a blank test result map.

Optionally, in some possible embodiments, the processing unit 20 is specifically configured to determine a corresponding position in the blank test result graph according to the test coordinate, and modify a bin value of the corresponding position in the blank test result graph according to the test result of the corresponding test coordinate, so as to obtain a partial test result graph.

Optionally, in some possible embodiments, the control unit 30 is specifically configured to retrieve, by the probe station, a partial test result diagram, and determine a position and a direction to start testing according to the partial test result diagram;

It should be noted that the above embodiments are product embodiments corresponding to previous method embodiments, and for the description of the product embodiments, reference may be made to corresponding descriptions in the above method embodiments, and details are not repeated here.

The reader should understand that in the description of this specification, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described method embodiments are merely illustrative, and for example, the division of steps into only one logical functional division may be implemented in practice in another way, for example, multiple steps may be combined or integrated into another step, or some features may be omitted, or not implemented.

The above method, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A test system abnormal interruption recovery method for wafer test is characterized by comprising the following steps:

2. The method as claimed in claim 1, wherein before modifying the blank test result graph according to the wafer test result, the method further comprises:

3. The method as claimed in claim 1, wherein the wafer test result comprises: the lot, the serial number, the test coordinate of the wafer and the test result corresponding to the test coordinate.

4. The method for recovering abnormal interruption of a test system for wafer testing as claimed in claim 3, wherein the modifying the blank test result graph according to the wafer test result to obtain a partial test result graph specifically comprises:

5. The method as claimed in any one of claims 1 to 4, wherein the step of retrieving the partial test result diagram by a probe station and testing the untested portion of the wafer according to the partial test result diagram to obtain a complete test result diagram includes:

6. A test system abnormal interruption recovery device for wafer test is characterized by comprising: reading unit, processing unit and control unit, wherein:

7. The apparatus as claimed in claim 6, wherein the control unit is further configured to perform a full-wafer test on the wafer without the probe card contacting the wafer, so as to obtain a connectivity failure test result map, i.e. a blank test result map.

8. The apparatus as claimed in claim 6, wherein the wafer test result comprises: the lot, the serial number, the test coordinate of the wafer and the test result corresponding to the test coordinate.

9. The apparatus as claimed in claim 8, wherein the processing unit is configured to determine a corresponding position in a blank test result graph according to the test coordinates, and modify bin values of the corresponding position in the blank test result graph according to the test result of the corresponding test coordinates to obtain a partial test result graph.

10. The apparatus as claimed in any one of claims 6 to 9, wherein the control unit is specifically configured to retrieve the partial test result map through a probe station, and determine a position and a direction of starting the test according to the partial test result map;