CN113708761A - Data weighted average algorithm and digital-to-analog conversion circuit - Google Patents
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- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
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- H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
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Abstract
The invention provides a data weighted average algorithm and a digital-to-analog conversion circuit, wherein the algorithm comprises the following steps: defining an initial index PA of an odd number period and an initial index PB of an even number period; if the current cycle is an odd cycle, starting from the position of the initial index PA, according to the input signal number S of the digital-to-analog converterinSelecting the number of corresponding elements, and calculating the index moving step number Sstep＝M‑SinObtaining a new index of the next odd cycle as PA ═ PA-Sstep(ii) a If the number of cycles is even, the index shift step number S is calculated from the position of the initial index PBstep＝M‑SinGet the new index of the next even cycle as PB ═ PB-Sstep(ii) a M is the number of elements in the digital-to-analog converter, and the position shift directions of the initial index PA of the odd period and the initial index PB of the even period are opposite. The invention can eliminate the mismatch error of the passive device and reduce the switching rate of the elementThe linearity is improved and the intersymbol interference effect is reduced.
Description
Technical Field
The present disclosure relates to the field of dynamic element matching technologies, and in particular, to a data weighted average algorithm and a digital-to-analog conversion circuit.
Background
Elements in the analog-to-digital converter and the digital-to-analog converter, such as a resistor, a capacitor and a current source, can generate gradient errors and random deviations due to limited process manufacturing precision and layout, so that conversion linearity is influenced, and a stray-free dynamic range is reduced.
Dynamic Element Matching (DEM) is a temperature code-wise selection of unit elements, typically equal-valued resistors, capacitors or current sources, usually added using a randomized selection of temperature code inputs. The Data Weighted Average (DWA) algorithm is one of DEM algorithms, and has the advantages of high rotation speed and capability of realizing rapid error calibration. The DWA algorithm adopts indexes, and as with all input codes, the content updating is realized by adding new input codes into an input register, so that the mismatch in space is converted into the mismatch in time, the harmonic waves in the output frequency spectrum are converted into noise, and the spurious-free dynamic range is improved.
A conventional DWA algorithm element selection diagram is shown in fig. 1, represented for simplicity by 7 elements (EL1, EL2, …, EL7), where selected elements are indicated by shaded boxes and unselected elements are indicated by blank boxes. Sin represents the input of the DAC, and Nseli is 1 when an element i (1 ≦ i ≦ 7) is selected; when element i is selected again, Nseli is 2, after all 7 elements have been used 1 pass. When DAC inputs (S)in) In the order of 2, 3, 4, 5, 6, 5, 4, and 3, as shown in fig. 1, the switching rates (toggle rates) are 5, 7, 5, 3, 5, and 7 from the second input of the DAC, respectively, and the total switching rate is 35.
Therefore, the conventional DWA method has a high switching rate, which aggravates an inter-symbol interference (ISI) effect and deteriorates linearity. Furthermore, the conventional DWA has only one index, which may produce tones associated with the input signal, reducing SFDR.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a data weighted average algorithm and a digital-to-analog conversion circuit, which can eliminate mismatch errors of passive devices, reduce the switching rate of elements, and reduce inter-symbol interference (ISI) effects while improving linearity.
In order to achieve the above purpose, the invention provides the following technical scheme:
a data weighted average algorithm is applied to a digital-to-analog converter and comprises the following steps:
defining an initial index PA of odd cycles and an initial index PB of even cycles in elements of the digital-to-analog converter;
judging whether the current period is an odd period or an even period;
if the odd cycle is the same, starting from the position of the initial index PA, according to the input signal number S of the digital-to-analog converterinSelecting the number of corresponding elements, and determining whether S is presentin+PA>M, if yes, calculating index moving step number Sstep＝M-SinAnd shifting the initial index PA position by SstepAn element, obtaining a new index for the next odd cycle as PA ═ PA-Sstep；
If the number of cycles is even, starting from the position of the initial index PB, the number S of input signals of the D/A converter is determinedinSelecting the number of corresponding elements, and determining whether S is presentin>PB, if yes, calculating index moving step number Sstep＝M-SinAnd shifts the position of the initial index PB by SstepAn element to obtain a new index of the next even cycle as PB ═ PB-Sstep；
Wherein, M is the number of elements in the digital-to-analog converter, and the position moving directions of the initial index PA of the odd period and the initial index PB of the even period are opposite.
Further, the method also comprises the step of judging whether S is present or not if the odd cycle is presentin+PA>M, if not, obtaining a new index of the next odd number period as PA ═ PA + Sin。
Further, the method also comprises the step of judging whether S is present or not if the cycle is an even cyclein>If not, obtaining a new index of the next even cycle as PB ═ PB-Sin。
Further, the initial index PA of the odd cycle is set to 1, and the initial index PB of the even cycle is set to M.
The invention also provides a digital-to-analog conversion circuit applying the data weighted average algorithm, which comprises,
the index register is used for receiving an input signal and defining an initial index PA of an odd period and an initial index PB of an even period;
the clock cycle counter circuit is connected with the index register and is used for counting the input clock cycle, judging that the current cycle is an odd cycle or an even cycle and outputting a result to the index register;
the step number calculation circuit is connected with the index register and used for receiving an input signal, the initial index PA of the odd cycle or the initial index PB of the even cycle output by the index register and calculating the index moving step number S of the initial index PA of the odd cycle or the initial index PB of the even cyclestep；
And the selection circuit is respectively connected with the clock period counter circuit and the step number calculation circuit and is used for controlling elements in the digital-to-analog conversion circuit and selecting corresponding elements as new indexes of the next period according to the index moving step number output by the step number calculation circuit.
Further, the method also comprises the following steps of,
a comparison circuit connected with the selection circuit and used for receiving the input signal and then counting the number S of the input signalsinCompared with the number M of elements in the digital-to-analog conversion circuit, whether the initial index PA of the odd period and the initial index PB of the even period need to be moved or not is judged.
Further, the number S of input signalsinAfter comparing with the number M of elements in the digital-to-analog conversion circuit,
if Sin<N, obtaining a new index of the next period after the initial index PA of the odd period and the initial index PB of the even period need to move;
if SinN, the index register does not work, and all the next cycleThe elements are all selected.
Further, the method also comprises the following steps of,
and the input end of the odd-even accumulator is connected with the selection circuit, and the output end of the odd-even accumulator is connected with the step number calculation circuit, is used for accumulating the using number of the elements in an odd number period and an even number period, judging whether all the elements are used up once in the period, and feeding back the elements to the step number calculation circuit.
Further, if all elements are used up once in the cycle, the parity accumulator sends a trigger signal to the step count calculation circuit, which calculates the index move step count Sstep＝M-SinIf not, Sstep＝0。
The data weighted average algorithm and the digital-to-analog conversion circuit can overcome the inter-symbol interference effect and reduce the tone by introducing two indexes and moving the indexes after all elements are used each time, thereby improving the spurious-free dynamic range of the digital-to-analog converter.
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In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a diagram of conventional DWA algorithm component selection;
FIG. 2 is a flow chart of the algorithm proposed by the present invention;
FIG. 3 is a circuit diagram of the algorithm proposed by the present invention;
FIG. 4 is a schematic diagram of a DAC device according to the present invention;
FIG. 5 is a schematic diagram of the selection of algorithm elements in the present invention.
Detailed Description
The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present disclosure, and the drawings only show the components related to the present disclosure rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
As shown in fig. 2, which is a flowchart of an algorithm proposed in this embodiment, a data weighted average algorithm in an embodiment of the present disclosure is applied to a digital-to-analog converter, a multi-bit signal is input to a DAC after a system is powered on, the DAC has M elements, and an initial index PA of an odd cycle is set to 1, and an initial index PB of an even cycle is set to M. Then the counter judges whether the current period is an odd period. If the period is odd number, starting from the position of index PA, the corresponding element number is selected according to the input of DAC. Firstly, whether S is present or not is judgedin+PA>M, if so, the step count calculation circuit calculates Sstep＝M-SinAnd shifts the index initial PA position to the right by SstepAn element, obtaining a new index for the next odd cycle as PA ═ PA-Sstep. If S isin+ PA ≦ M, and the new index for the next odd cycle is PA ═ PA + Sin. And finally, selecting the number of corresponding elements from the new index to the right. If the period is an even number, starting from the position of the index PB, selecting the number of corresponding elements according to the input of the DAC, and judging whether S is the number of the corresponding elements or notin>PB, if so, the step count calculating circuit calculates Sstep＝M-SinAnd shift the position of index PB to the left by SstepAn element, new index PB ═ PB-Sstep. If Sin is less than PB, obtaining the new index of the next even cycle as PB ═ PB-SinAnd finally, selecting the number of corresponding elements from the new index to the left.
As shown in fig. 3, fig. 3 is a circuit structure diagram of the present embodiment to which the above-mentioned data weighted average algorithm is applied. DAC input SinEntering the index register 410, the initial index of the odd cycles is defined as PA and the initial index of the even cycles is defined as PB. Odd cycles have element selection from left to right (or right to left as well), and even cycles have element selection in the opposite direction as the odd cycles. The clock CLK is provided as an input to a clock cycle counter circuit 420 having a parity cycle decision that counts CLK cycles, separating odd and even cycles for the index register 410 to generate PA and PB. The comparison circuit 430 compares SinAnd the size of M, M being the total number of DAC elements, if SinIndex register as MNot working, all elements are selected in the next period; if S isin<M, the index register works normally. SinPA and PB are inputs to step count calculation circuit 440, step count S if all elements are used in their entirety during an odd cyclestep＝M-SinIf further components are not used, S step0; the method for even cycles is the same as for odd cycles, Sstep＝M-SinThe use of odd-cycle elements requires moving S to the right each time the element is used up and overstep(and also to the left) the even cycles are shifted in the opposite direction to the odd cycles. The selection of elements is accomplished by selection circuit 450, and parity accumulator 460 provides a trigger signal S each time N elements have been selected over a full passSTThe step number calculating circuit starts to calculate Sstep＝M-Sin(ii) a If any elements are not used in the selection, SSTWhen the step number is 0, the step number calculation circuit will calculate SstepIs set to 0. The elements 401 are M elements of a DAC (EL1, EL2, …, ELM), controlled by a selection circuit 450.
As shown in fig. 4, a DAC element schematic is shown in fig. 4. Taking X +4 cells as an example, selected elements are represented by shaded boxes, and unselected elements are represented by blank boxes.
As shown in fig. 5, fig. 5 shows a schematic diagram of the selection of the algorithm elements proposed by the present invention. As in the conventional method, 7 elements (EL1, EL2, …, EL7) are also shown, wherein selected elements are indicated by shaded boxes and non-selected elements are indicated by blank boxes. The DAC input (Sin) is also 2, 3, 4, 5, 6, 5, 4, 3 in turn, as shown in fig. 5, the switching rate (toggle rate) is 5, 3 from the second DAC input, respectively, the total switching rate is 23, whereas the conventional DWA algorithm of fig. 1 has a total switching rate of 35. It can be seen that the switching rate of the inventive DWA algorithm is significantly lower than that of the conventional DWA algorithm, reducing the influence of ISI effects.
The invention provides for the rotation in opposite directions by introducing two indices (PA, PB), the direction of rotation alternating with each period. The odd cycles can be defined as right rotations and the even cycles as left rotations, and likewise the even cycles are right rotations if the odd cycles are defined as left rotations. There is a separate index pointer for both directions and the rotation is independent. The tones associated with the input are attenuated. And, after all elements are used during the PA index period (assuming PA corresponds to odd period), the pointer is advanced at the next odd period; after all elements are used during the PB index period (assuming PB corresponds to an even period), the pointer is advanced for the next even period. Thus, when a new component appears, the cycle begins with the previously selected component being reused. Thus reducing the switching rate and the variation is randomized, reducing the ISI effect. Therefore, the data weighted average algorithm of the invention reduces the switching rate of elements so as to weaken the ISI effect, can weaken the tone related to the input at the same time, and is suitable for a multi-bit DAC.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (9)
1. A data weighted average algorithm applied to a digital-to-analog converter, comprising:
defining an initial index PA of odd cycles and an initial index PB of even cycles in elements of the digital-to-analog converter;
judging whether the current period is an odd period or an even period;
if the odd cycle is the same, starting from the position of the initial index PA, according to the input signal number S of the digital-to-analog converterinSelecting the number of corresponding elements, and determining whether S is presentin+PA>M, if yes, calculating index moving step number Sstep＝M-SinAnd shifting the initial index PA position by SstepAn element, obtaining a new index for the next odd cycle as PA ═ PA-Sstep；
In the case of an even cycle, starting from the position of the initial index PB, the number is based onNumber of input signals S of analog-to-digital converterinSelecting the number of corresponding elements, and determining whether S is presentin>PB, if yes, calculating index moving step number Sstep＝M-SinAnd shifts the position of the initial index PB by SstepAn element to obtain a new index of the next even cycle as PB ═ PB-Sstep；
Wherein, M is the number of elements in the digital-to-analog converter, and the position moving directions of the initial index PA of the odd period and the initial index PB of the even period are opposite.
2. The data weighted average algorithm of claim 1, further comprising, if the odd cycle is determined to be Sin+PA>M, if not, obtaining a new index of the next odd number period as PA ═ PA + Sin。
3. The data weighted average algorithm of claim 1 or 2, further comprising, if the period is an even number, determining whether S is presentin>If not, obtaining a new index of the next even cycle as PB ═ PB-Sin。
4. The data weighted average algorithm of claim 3, wherein the initial index PA of the odd cycles is set to 1, and the initial index PB of the even cycles is set to M.
5. A digital-to-analog conversion circuit applying the data weighted average algorithm of claim 1, comprising,
the index register is used for receiving an input signal and defining an initial index PA of an odd period and an initial index PB of an even period;
the clock cycle counter circuit is connected with the index register and is used for counting the input clock cycle, judging that the current cycle is an odd cycle or an even cycle and outputting a result to the index register;
a step count calculation circuit connected with the index register for receiving input signalAnd the initial index PA of odd cycle or the initial index PB of even cycle output by the index register, and calculating the index shift step number S of the initial index PA of odd cycle or the initial index PB of even cyclestep；
And the selection circuit is respectively connected with the clock period counter circuit and the step number calculation circuit and is used for controlling elements in the digital-to-analog conversion circuit and selecting corresponding elements as new indexes of the next period according to the index moving step number output by the step number calculation circuit.
6. The digital-to-analog conversion circuit of claim 5, further comprising,
a comparison circuit connected with the selection circuit and used for receiving the input signal and then counting the number S of the input signalsinCompared with the number M of elements in the digital-to-analog conversion circuit, whether the initial index PA of the odd period and the initial index PB of the even period need to be moved or not is judged.
7. The digital-to-analog conversion circuit according to claim 6, wherein the number S of input signals is setinAfter comparing with the number M of elements in the digital-to-analog conversion circuit,
if Sin<N, obtaining a new index of the next period after the initial index PA of the odd period and the initial index PB of the even period need to move;
if SinN, the index register is inactive and all elements are selected for the next cycle.
8. The digital-to-analog conversion circuit of claim 7, further comprising,
and the input end of the odd-even accumulator is connected with the selection circuit, and the output end of the odd-even accumulator is connected with the step number calculation circuit, is used for accumulating the using number of the elements in an odd number period and an even number period, judging whether all the elements are used up once in the period, and feeding back the elements to the step number calculation circuit.
9. The DAC circuit of claim 8 wherein the odd-even accumulator sends a trigger signal to the step count calculation circuit if all elements are used up once in the cycle, the step count calculation circuit calculating the index shift step count Sstep＝M-SinIf not, Sstep＝0。
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