CN113707780B - Micro light-emitting diode chip and preparation method thereof - Google Patents

Micro light-emitting diode chip and preparation method thereof Download PDF

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Publication number
CN113707780B
CN113707780B CN202110870153.1A CN202110870153A CN113707780B CN 113707780 B CN113707780 B CN 113707780B CN 202110870153 A CN202110870153 A CN 202110870153A CN 113707780 B CN113707780 B CN 113707780B
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layer
electrode
semiconductor layer
emitting diode
diode chip
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CN113707780A (en
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兰叶
王江波
吴志浩
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HC Semitek Zhejiang Co Ltd
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HC Semitek Zhejiang Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/387—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes

Abstract

The present disclosure provides a micro light emitting diode chip and a method of manufacturing the same. The micro light emitting diode chip includes: a first semiconductor layer, a multiple quantum well layer, a second semiconductor layer, a transparent conductive layer, a passivation layer, a first electrode, and a second electrode; the second semiconductor layer, the multiple quantum well layer, the first semiconductor layer and the passivation layer are sequentially laminated on the transparent conductive layer, the passivation layer is provided with a through hole, the through hole exposes the first semiconductor layer and is opposite to the middle part of the first semiconductor layer, and the first electrode is positioned in the through hole; the second electrode is located on the surface, far away from the second semiconductor layer, of the transparent conductive layer, and the second electrode comprises a plurality of first electrode blocks which are arranged at intervals along the edge of the transparent conductive layer. The size of the miniature light-emitting diode chip can be reduced, and the light emitting effect of the miniature light-emitting diode chip is ensured.

Description

Micro light-emitting diode chip and preparation method thereof
Technical Field
The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular, to a micro light emitting diode chip and a method for manufacturing the same.
Background
The Micro light emitting diode (Micro Light Emitting Diode, micro LED) is an ultra-small light emitting diode with a side length of 10-100 μm, has small volume, can be arranged more densely to greatly improve resolution, has self-luminous property, and has the characteristics of high brightness, high contrast, high reactivity and power saving.
In the related art, a micro light emitting diode chip generally includes an epitaxial structure including a second semiconductor layer, a multiple quantum well layer, and a first semiconductor layer stacked in this order, a first electrode, and a second electrode. Wherein, the first electrode and the second electrode are both arranged on the same side of the epitaxial structure.
Because the first electrode and the second electrode are arranged on the same side of the epitaxial structure, the first electrode and the second electrode need to be accommodated on the side surface of the epitaxial structure, and a certain interval is ensured between the two electrodes, so that the size of the miniature light-emitting diode chip is larger and is difficult to further reduce; the first electrode and the second electrode are respectively arranged on different sides of the epitaxial structure, so that the electrode positioned on the light emitting side can shield light and influence the light emitting effect of the miniature light emitting diode chip.
Disclosure of Invention
The embodiment of the disclosure provides a micro light emitting diode chip and a preparation method thereof, which can reduce the size of the micro light emitting diode chip and ensure the light emitting effect of the micro light emitting diode chip. The technical scheme is as follows:
embodiments of the present disclosure provide a micro light emitting diode chip including: a first semiconductor layer, a multiple quantum well layer, a second semiconductor layer, a transparent conductive layer, a passivation layer, a first electrode, and a second electrode; the second semiconductor layer, the multiple quantum well layer, the first semiconductor layer and the passivation layer are sequentially laminated on the transparent conductive layer, the passivation layer is provided with a through hole, the through hole exposes the first semiconductor layer and is opposite to the middle part of the first semiconductor layer, and the first electrode is positioned in the through hole; the second electrode is located on the surface, far away from the second semiconductor layer, of the transparent conducting layer, the second electrode comprises a plurality of first electrode blocks, and the plurality of first electrode blocks are arranged at intervals along the edge of the transparent conducting layer.
In one implementation manner of the embodiment of the disclosure, the second electrode further includes a plurality of second electrode blocks, the second electrode blocks are located in the middle of the transparent conductive layer, the second electrode blocks are distributed at intervals, and the number of the second electrode blocks is smaller than that of the first electrode blocks.
In another implementation of an embodiment of the present disclosure, a plurality of the second electrode block arrays are distributed.
In another implementation of an embodiment of the disclosure, the first electrode block and the second electrode block each include a first chromium layer, a tin-indium alloy layer, and an indium layer sequentially laminated to the transparent conductive layer.
In another implementation of the disclosed embodiments, the tin component of the tin-indium alloy layer gradually decreases in duty cycle from a side proximate to the first chromium layer to a side proximate to the indium layer.
In another implementation of an embodiment of the present disclosure, the rate of decrease of the ratio of tin component in the tin-indium alloy layer increases gradually from a side near the first chromium layer to a side near the indium layer.
In another implementation of the embodiment of the disclosure, the first chromium layer has a thickness of 400 angstroms to 600 angstroms, the tin-indium alloy layer has a thickness of 0.8 μm to 1.2 μm, and the indium layer has a thickness of 0.8 μm to 1.2 μm.
In another implementation of an embodiment of the present disclosure, the first electrode includes a second chromium layer, a titanium layer, and a gold layer sequentially stacked on the first semiconductor layer.
In another implementation of the embodiment of the disclosure, the thickness of the second chromium layer is 100to 300 angstroms, the thickness of the titanium layer is 100to 300 angstroms, and the thickness of the gold layer is 2000 to 4000 angstroms.
The embodiment of the disclosure provides a preparation method of a miniature light-emitting diode chip, which comprises the following steps: providing a substrate; sequentially growing a second semiconductor layer, a multiple quantum well layer, a first semiconductor layer and a first electrode on the substrate; forming a passivation layer on the first semiconductor layer, wherein the passivation layer is provided with a through hole, the through hole exposes the first semiconductor layer and is opposite to the middle part of the first semiconductor layer, and the first electrode is positioned in the through hole; and sequentially forming a transparent conducting layer and a second electrode on the surface, far away from the multi-quantum well layer, of the second semiconductor layer, wherein the second electrode is positioned on the surface, far away from the second semiconductor layer, of the transparent conducting layer, and comprises a plurality of first electrode blocks, and the plurality of first electrode blocks are distributed at intervals along the edge of the transparent conducting layer.
The technical scheme provided by the embodiment of the disclosure has the beneficial effects that at least:
the embodiment of the disclosure provides a micro light emitting diode chip, which comprises a transparent conductive layer, a second semiconductor layer, a multiple quantum well layer, a first semiconductor layer and a passivation layer which are sequentially laminated, wherein a first electrode is connected with the first semiconductor layer through a through hole positioned on the passivation layer, and a second electrode is arranged on the surface of the transparent conductive layer and is connected with the second semiconductor layer through the transparent conductive layer. In this way, the first electrode and the second electrode are respectively arranged on the opposite sides of the epitaxial structure of the micro light emitting diode, so that the surface of the epitaxial structure only needs to meet the size capable of accommodating one electrode, and the size of the micro light emitting diode chip can be effectively reduced. Meanwhile, the second electrode on the transparent conductive layer comprises a plurality of first electrode blocks which are arranged at intervals along the edge of the transparent conductive layer. Thus, the second electrode is designed into a plurality of scattered first electrode blocks, and the purpose of conducting electricity of the second electrode can be achieved by manufacturing a small number of first electrode blocks. Meanwhile, the first electrode blocks are distributed at intervals on the edge of the transparent conducting layer, so that shielding of the second electrode to light can be avoided to the greatest extent, and the light emitting effect of the miniature light emitting diode chip is guaranteed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a micro light emitting diode chip according to an embodiment of the disclosure;
fig. 2 is a bottom view of a micro light emitting diode chip provided in an embodiment of the present disclosure;
FIG. 3 is a top view of a micro light emitting diode chip provided in an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a micro light emitting diode chip according to an embodiment of the disclosure;
FIG. 5 is a graph of tin composition in a tin-indium alloy layer versus thickness of the tin-indium alloy layer provided by embodiments of the present disclosure;
fig. 6 is a flowchart of a method for manufacturing a micro light emitting diode chip according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a manufacturing process of a micro light emitting diode chip according to an embodiment of the disclosure;
fig. 8 is a schematic diagram of a manufacturing process of a micro light emitting diode chip according to an embodiment of the disclosure;
fig. 9 is a schematic diagram of a manufacturing process of a micro light emitting diode chip according to an embodiment of the disclosure.
The various labels in the figures are described below:
10-a first semiconductor layer;
20-multiple quantum well layers;
30-a second semiconductor layer;
40-a transparent conductive layer;
50-passivation layer, 51-via;
60-a first electrode, 61-a second chromium layer, 62-a titanium layer, 63-a gold layer;
70-second electrode, 71-first electrode block, 72-second electrode block, 73-first chromium layer, 74-tin-indium alloy layer, 75-indium layer;
81-sapphire substrate, 82-double polished sapphire substrate 82.
Detailed Description
For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.
Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," "third," and the like in the description and in the claims, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, is intended to mean that elements or items that are present in front of "comprising" or "comprising" are included in the word "comprising" or "comprising", and equivalents thereof, without excluding other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", "top", "bottom" and the like are used only to indicate relative positional relationships, which may be changed accordingly when the absolute position of the object to be described is changed.
Fig. 1 is a schematic structural diagram of a micro light emitting diode chip according to an embodiment of the disclosure. As shown in fig. 1, the micro light emitting diode chip includes: the first semiconductor layer 10, the multiple quantum well layer 20, the second semiconductor layer 30, the transparent conductive layer 40, the passivation layer 50, the first electrode 60, and the second electrode 70.
As shown in fig. 1, the second semiconductor layer 30, the multiple quantum well layer 20, the first semiconductor layer 10, and the passivation layer 50 are sequentially stacked on the transparent conductive layer 40, the passivation layer 50 has a via hole 51, the via hole 51 exposes the first semiconductor layer 10, and the first electrode 60 is located in the via hole 51 opposite to the middle of the first semiconductor layer 10.
Fig. 2 is a bottom view of a micro light emitting diode chip provided in an embodiment of the present disclosure. As shown in fig. 2, the second electrode 70 is located on a surface of the transparent conductive layer 40 remote from the second semiconductor layer 30, and the second electrode 70 includes a plurality of first electrode blocks 71, and the plurality of first electrode blocks 71 are spaced apart along an edge of the transparent conductive layer 40.
The embodiment of the disclosure provides a micro light emitting diode chip comprising a transparent conductive layer 40, a second semiconductor layer 30, a multiple quantum well layer 20, a first semiconductor layer 10 and a passivation layer 50 sequentially stacked, wherein a first electrode 60 is connected with the first semiconductor layer 10 through a through hole 51 on the passivation layer 50, and a second electrode 70 is disposed on the surface of the transparent conductive layer 40 and is connected with the second semiconductor layer 30 through the transparent conductive layer 40. In this way, the first electrode 60 and the second electrode 70 are respectively arranged at the opposite sides of the epitaxial structure of the micro light emitting diode, so that the surface of the epitaxial structure only needs to meet the size capable of accommodating one electrode, and the size of the micro light emitting diode chip can be effectively reduced. Meanwhile, the second electrode 70 on the transparent conductive layer 40 includes a plurality of first electrode blocks 71, and the plurality of first electrode blocks 71 are spaced apart along an edge of the transparent conductive layer 40. By designing the second electrode 70 as a plurality of dispersed first electrode blocks 71 in this way, the purpose of conducting electricity of the second electrode 70 can be achieved by making only a small number of first electrode blocks 71. Meanwhile, the first electrode blocks 71 are distributed at intervals on the edge of the transparent conductive layer 40, so that the shielding of the second electrode 70 to light can be avoided to the greatest extent, and the light emitting effect of the micro light emitting diode chip is ensured.
Wherein the edge refers to the peripheral edge region of the transparent conductive layer 40. For example, if the transparent conductive layer 40 is rectangular, the edges of the transparent conductive layer 40 are rectangular frame-shaped regions extending inward from four sides of the transparent conductive layer 40 by a set distance.
In the embodiment of the present disclosure, one of the first semiconductor layer 10 and the second semiconductor layer 30 is a p-type layer, and the other of the first semiconductor layer 10 and the second semiconductor layer 30 is an n-type layer.
As an example, the first semiconductor layer 10 is a p-type layer, and the first electrode 60 is a p-type electrode. The second semiconductor layer 30 is an n-type layer and the second electrode 70 is an n-type electrode.
Fig. 3 is a top view of a micro led chip provided in an embodiment of the present disclosure. As shown in fig. 3, the first electrode 60 is located in the middle of the first semiconductor layer 10. Therefore, the current can focus on flowing in the central area of the micro light emitting diode chip, the current density of the edge area of the micro light emitting diode chip is lower, and the luminous intensity of the edge area of the micro light emitting diode chip can be effectively reduced.
The orthographic projection of the first electrode 60 on the transparent conductive layer 40 is located in the middle of the transparent conductive layer 40, and the second electrode 70 is located at the edge of the transparent conductive layer 40. Even if a part of the light is blocked by the first electrode block 71 arranged at the edge position, the light-emitting intensity of the blocked part of the light is low, so that the whole light-emitting effect of the micro light-emitting diode chip is not affected.
As can be seen in fig. 1, the orthographic projection of the first electrode 60 on the transparent conductive layer 40 is located in the area surrounded by each first electrode block 71. The light emitting intensity of the middle region of the micro led chip is high and the light is not blocked by the first electrode block 71, so that the light emitting effect can be ensured.
Illustratively, as shown in fig. 3, the first electrode 60 is rectangular. The rectangular first electrode 60 can be spread over the central area of the micro led chip more fully to effectively increase the luminous intensity of the edge area of the micro led chip.
It should be noted that, in other implementations, the first electrode 60 may also have various shapes such as a circle, a polygon, etc., which are not limited by the embodiments of the present disclosure.
Fig. 4 is a schematic structural diagram of a micro light emitting diode chip according to an embodiment of the disclosure. As shown in fig. 4, the first electrode 60 includes a second chromium layer 61, a titanium layer 62, and a gold layer 63 sequentially laminated on the surface of the first semiconductor layer 10.
Wherein the thickness of the second chromium layer 61 may be 100to 300 angstroms, the thickness of the titanium layer 62 may be 100to 300 angstroms, and the thickness of the gold layer 63 may be 2000 to 4000 angstroms.
By way of example, in the presently disclosed embodiment, the second chromium layer 61 has a thickness of 200 angstroms, the titanium layer 62 has a thickness of 200 angstroms, and the gold layer 63 has a thickness of 3000 angstroms.
Optionally, as shown in fig. 2, the second electrode 70 further includes a second electrode block 72, where a plurality of second electrode blocks 72 are located at a middle portion of the transparent conductive layer 40, and the plurality of second electrode blocks 72 are spaced apart, and the number of second electrode blocks 72 is less than the number of first electrode blocks 71.
In this way, the second electrode 70 is designed into a plurality of scattered first electrode blocks 71, and a small number of second electrode blocks 72 are arranged in the area surrounded by the first electrode blocks 71, so that the whole area of the second electrode 70 is increased to the greatest extent while the light emitting effect is not affected, the purpose of conducting electricity of the second electrode 70 can be achieved only by manufacturing a small number of first electrode blocks 71 and second electrode blocks 72, and the shielding of the second electrode 70 to light is reduced to the greatest extent.
Optionally, a plurality of second electrode blocks 72 are distributed in an array.
Illustratively, as shown in fig. 2, the transparent conductive layer 40 has a rectangular shape, and the first electrode blocks 71 are arranged at intervals along the edges of the rectangular frame shape of the transparent conductive layer 40 such that the plurality of first electrode blocks 71 are arranged in the rectangular shape. Four second electrode blocks 72 are further disposed in the area surrounded by the plurality of first electrode blocks 71, and the four second electrode blocks 72 are also distributed in an array and are arranged in a rectangular shape at intervals.
Wherein the arrangement pitch of the adjacent two second electrode blocks 72 is larger than the arrangement pitch of the adjacent two first electrode blocks 71. That is, the arrangement pitch of the second electrode blocks 72 is less dense than the arrangement pitch of the first electrode blocks 71, so that the influence of light-emitting effect due to the shielding of light by the excessive arrangement of the second electrode blocks 72 is avoided.
In the embodiment of the present disclosure, both the first electrode block 71 and the second electrode block 72 may have a cylindrical shape.
As shown in fig. 4, each of the first electrode block 71 and the second electrode block 72 includes a first chromium layer 73, a tin-indium alloy layer 74, and an indium layer 75, which are sequentially laminated on the transparent conductive layer 40. An indium-tin alloy layer 74 is disposed between the first chromium layer 73 and the indium layer 75, and since the indium metal is contained in the indium-tin alloy layer 74, the indium-tin alloy layer 74 and the indium layer 75 can be well connected together, so that the shape-retaining effect of the three laminated metal layers is improved.
Wherein the thickness of the first chromium layer 73 may be 400 to 600 angstroms, the thickness of the tin-indium alloy layer 74 may be 8000 to 12000 angstroms, and the thickness of the indium layer 75 may be 8000 to 12000 angstroms.
As an example, in the embodiment of the present disclosure, the thickness of the first chromium layer 73 is 500 angstroms, the thickness of the tin-indium alloy layer 74 is 10000 angstroms, and the thickness of the indium layer 75 is 10000 angstroms.
Fig. 5 is a graph of tin composition in a tin-indium alloy layer versus thickness of the tin-indium alloy layer provided by embodiments of the present disclosure. As shown in fig. 5, the ratio of the tin component in the tin-indium alloy layer 74 gradually decreases from the side near the first chromium layer 73 to the side near the indium layer 75. And, the rate of decrease in the ratio of tin component gradually increases.
Wherein the composition of tin decreases with increasing thickness of the tin-indium alloy layer 74 and the rate of decrease becomes progressively greater. Referring to fig. 5, the composition of tin is changed according to a flat-cast curve, and the decreasing rate is the absolute value of the slope of the flat-cast curve, and the absolute value of the slope gradually increases as the thickness of the tin-indium alloy layer 74 increases, so that the tin-indium alloy layer 74 and the indium layer 75 can be well fused to obtain the second electrode 70 with a better shape.
Optionally, the transparent conductive layer 40 is an Indium Tin Oxide (ITO) film layer. The indium tin oxide film layer has good transmittance and low resistivity, and the adoption of the indium tin oxide film layer as the transparent conductive layer 40 can enable more light to be transmitted out of the transparent conductive layer 40, so that the effect is ensured; meanwhile, due to low resistivity, carrier conduction is facilitated, and injection efficiency is improved.
Illustratively, the transparent conductive layer 40 has a thickness of 800 angstroms to 1200 angstroms.
The thickness of the transparent conductive layer 40 may affect the light transmission effect and the resistance value of the transparent conductive layer 40, and if the thickness is too low or too high, the light transmission effect of the transparent conductive layer 40 may be poor, which is not beneficial to the injection of carriers. In this thickness range, the transparent conductive layer 40 having a high light transmission effect and a low resistance value can be formed, which is advantageous for improving the light emitting effect of the light emitting diode.
By way of example, in the presently disclosed embodiment, transparent conductive layer 40 has a thickness of 1000 angstroms.
Alternatively, the second semiconductor layer 30 is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer may be 0.5 μm to 3 μm.
Alternatively, the multiple quantum well layer 20 includes InGaN quantum well layers and GaN quantum barrier layers alternately grown. Among them, the multiple quantum well layer 20 may include InGaN quantum well layers and GaN quantum barrier layers of 3 to 8 periods alternately stacked.
As an example, in the presently disclosed embodiment, the multiple quantum well layer 20 includes 5 periods of InGaN quantum well layers and GaN quantum barrier layers alternately stacked.
Alternatively, the thickness of the multiple quantum well layer 20 may be 150nm to 200nm.
Alternatively, the first semiconductor layer 10 is a p-type GaN layer doped with magnesium. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.
Optionally, the passivation layer 50 is a silicon oxide layer. And the passivation layer 50 has a thickness of 1800 angstroms to 2200 angstroms.
By way of example, in the presently disclosed embodiment, the passivation layer 50 has a thickness of 2000 angstroms.
Fig. 6 is a flowchart of a method for manufacturing a micro light emitting diode chip according to an embodiment of the disclosure. As shown in fig. 6, the preparation method includes:
step S11: a substrate is provided.
Step S12: sequentially growing a second semiconductor layer 30, a multiple quantum well layer 20, a first semiconductor layer 10, and a first electrode 60 on a substrate;
step S13: a passivation layer 50 is formed on the first semiconductor layer 10, the passivation layer 50 having a via 51.
Wherein the through hole 51 exposes the first semiconductor layer 10, and the through hole 51 is opposite to the middle of the first semiconductor layer 10, and the first electrode 60 is located in the through hole 51.
Step S14: a transparent conductive layer 40 and a second electrode 70 are sequentially formed on a surface of the second semiconductor layer 30 remote from the multiple quantum well layer 20.
The second electrode 70 is located on a surface of the transparent conductive layer 40 away from the second semiconductor layer 30, and the second electrode 70 includes a plurality of first electrode blocks 71, where the plurality of first electrode blocks 71 are arranged at intervals along an edge of the transparent conductive layer 40.
The micro light emitting diode chip manufactured by the manufacturing method of the micro light emitting diode chip according to the embodiment of the present disclosure includes a transparent conductive layer 40, a second semiconductor layer 30, a multiple quantum well layer 20, a first semiconductor layer 10 and a passivation layer 50 which are sequentially stacked, wherein a first electrode 60 is connected with the first semiconductor layer 10 through a through hole 51 located on the passivation layer 50, and a second electrode 70 is disposed on the surface of the transparent conductive layer 40 and is connected with the second semiconductor layer 30 through the transparent conductive layer 40. In this way, the first electrode 60 and the second electrode 70 are respectively arranged at the opposite sides of the epitaxial structure of the micro light emitting diode, so that the surface of the epitaxial structure only needs to meet the size capable of accommodating one electrode, and the size of the micro light emitting diode chip can be effectively reduced. Meanwhile, the second electrode 70 on the transparent conductive layer 40 includes a plurality of first electrode blocks 71, and the plurality of first electrode blocks 71 are spaced apart along an edge of the transparent conductive layer 40. By designing the second electrode 70 as a plurality of dispersed first electrode blocks 71 in this way, the purpose of conducting electricity of the second electrode 70 can be achieved by making only a small number of first electrode blocks 71. Meanwhile, the first electrode blocks 71 are distributed at intervals on the edge of the transparent conductive layer 40, so that the shielding of the second electrode 70 to light can be avoided to the greatest extent, and the light emitting effect of the micro light emitting diode chip is ensured.
In step S11, the substrate is a sapphire substrate 81, a silicon substrate, or a silicon carbide substrate. The substrate may be a flat substrate or a patterned substrate.
As an example, in embodiments of the present disclosure, the substrate is a sapphire substrate. The sapphire substrate is a common substrate, the technology is mature, and the cost is low. Specifically, the substrate can be a patterned sapphire substrate or a sapphire flat substrate.
Wherein, the sapphire substrate can be pretreated, placed in an MOCVD (Metal-organic Chemical Vapor Deposition, metal organic chemical vapor deposition) reaction chamber, and baked for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.
Specifically, the baking temperature may be 1000 ℃ to 1200 ℃, and the pressure in the MOCVD reaction chamber during baking may be 100mbar to 200mbar.
Fig. 7 is a schematic diagram of a manufacturing process of a micro light emitting diode chip according to an embodiment of the disclosure. As shown in fig. 7, growing the second semiconductor layer 30 in step S12 may include: the second semiconductor layer 30 is formed on the sapphire substrate 81 by the MOCVD technique.
Wherein the second semiconductor layer 30 is an n-type GaN layer. The growth temperature of the n-type GaN layer may be 1000 ℃ to 1100 ℃, and the growth pressure of the n-type GaN layer may be 100torr to 300torr.
Alternatively, the thickness of the n-type GaN layer is 0.5 μm to 3 μm. For example, the thickness of the n-type GaN layer may be 1 μm.
As shown in fig. 7, growing the multiple quantum well layer 20 in step S12 may include: a multiple quantum well layer 20 is formed on the n-type GaN layer.
The multiple quantum well layer 20 includes InGaN quantum well layers and GaN quantum barrier layers alternately grown therein. Among them, the multiple quantum well layer 20 may include InGaN quantum well layers and GaN quantum barrier layers of 3 to 8 periods alternately stacked.
As an example, in the presently disclosed embodiment, the multiple quantum well layer 20 includes 5 periods of InGaN quantum well layers and GaN quantum barrier layers alternately stacked.
Alternatively, the thickness of the multiple quantum well layer 20 may be 150nm to 200nm.
When the multi-quantum well layer 20 is grown, the pressure of the MOCVD reaction chamber is controlled at 200torr. When the InGaN quantum well layer is grown, the temperature of the reaction chamber is 760-780 ℃. When the GaN quantum barrier layer is grown, the temperature of the reaction chamber is 860-890 ℃. The quality of the multiple quantum well layer 20 grown under the process conditions is better.
As shown in fig. 7, growing the first semiconductor layer 10 in step S12 may include: a p-type GaN layer is formed on the multiple quantum well layer 20.
Alternatively, the thickness of the p-type GaN layer is 0.5 μm to 3 μm. For example, the thickness of the p-type GaN layer is 1 μm.
When the p-type GaN layer is grown, the growth pressure of the p-type GaN layer may be 200Torr to 600Torr, and the growth temperature of the p-type GaN layer may be 800 ℃ to 1000 ℃.
As shown in fig. 7, growing the first electrode 60 in step S12 may include: the first electrode 60 is vapor deposited on the surface of the first semiconductor layer 10. The first electrode 60 may include a second chromium layer 61, a titanium layer 62, and a gold layer 63 sequentially laminated on the surface of the first semiconductor layer 10.
Wherein the thickness of the second chromium layer 61 may be 100to 300 angstroms, the thickness of the titanium layer 62 may be 100to 300 angstroms, and the thickness of the gold layer 63 may be 2000 to 4000 angstroms.
By way of example, in the presently disclosed embodiment, the second chromium layer 61 has a thickness of 200 angstroms, the titanium layer 62 has a thickness of 200 angstroms, and the gold layer 63 has a thickness of 3000 angstroms.
Fig. 8 is a schematic diagram of a manufacturing process of a micro light emitting diode chip according to an embodiment of the disclosure. As shown in fig. 8, growing the passivation layer 50 in step S13 may include: silicon oxide is deposited on the surface of the first semiconductor layer 10 by atomic layer deposition (Atomic layer deposition, ALD for short).
Wherein the deposited silicon oxide has a film thickness of 1800 to 2200 angstroms. In the embodiment of the disclosure, the thickness of the film layer of silicon oxide is 2000 angstroms.
Wherein the passivation layer 50 is formed with a via hole 51 exposing the first semiconductor layer 10, at least a portion of the first electrode 60 is located outside the via hole 51.
As shown in fig. 8, step S13 may further include: the prepared epitaxial structure is bonded to the double-polished sapphire substrate 82 with the passivation layer 50 and the first electrode 60 facing the double-polished sapphire substrate 82.
The bonding material can be photoresist, SOG (Silicon On Glass) and silica gel.
As shown in fig. 9, before sequentially forming the transparent conductive layer 40 and the second electrode 70 on the surface of the second semiconductor layer 30 remote from the multi-quantum well layer 20 in step S14 may include: the laser lift-off removes the sapphire substrate 81 located under the second semiconductor layer 30.
Wherein the laser wavelength is 266 nm, and the Ga metal needs to be rinsed by acid after stripping.
As shown in fig. 9, step S14 may include: the transparent conductive layer 40 is processed and annealed at a surface of the second semiconductor layer 30 remote from the first semiconductor layer 10.
Optionally, the transparent conductive layer 40 is an indium tin oxide film layer. Illustratively, the transparent conductive layer 40 has a thickness of 800 angstroms to 1200 angstroms.
As shown in fig. 9, step S14 may include: a second electrode 70 is fabricated on the transparent conductive layer 40.
The second electrode 70 includes a plurality of first electrode blocks 71, and the plurality of first electrode blocks 71 are arranged at intervals along an edge of the transparent conductive layer 40.
As shown in fig. 2, the second electrode 70 further includes second electrode blocks 72, the second electrode blocks 72 are located in an area surrounded by the first electrode blocks 71, and the second electrode blocks 72 are spaced apart from each other. In this way, a small amount of second electrode blocks 72 are arranged between the areas surrounded by the first electrode blocks 71, so that the whole area of the second electrode 70 is increased to the greatest extent while the light emitting effect is not affected, the purpose of conducting electricity of the second electrode 70 can be achieved only by manufacturing a small amount of first electrode blocks 71 and second electrode blocks 72, and shielding of the second electrode 70 to light is reduced to the greatest extent.
The first electrode block 71 and the second electrode block 72 each include a first chromium layer 73, a tin-indium alloy layer 74, and an indium layer 75, which are sequentially laminated on the transparent conductive layer 40. An indium-tin alloy layer 74 is disposed between the first chromium layer 73 and the indium layer 75, and since the indium metal is contained in the indium-tin alloy layer 74, the indium-tin alloy layer 74 and the indium layer 75 can be well connected together, so that the shape-retaining effect of the three laminated metal layers is improved.
Illustratively, the first chromium layer 73 may be 400 to 600 angstroms thick, the tin-indium alloy layer 74 may be 8000 to 12000 angstroms thick, and the indium layer 75 may be 8000 to 12000 angstroms thick.
Wherein the composition of tin decreases with increasing thickness of the tin-indium alloy layer 74 and the decreasing rate becomes gradually larger, i.e. the composition of tin changes in a flat-cast curve manner, so that the tin-indium alloy layer 74 and the indium layer 75 can be well fused to obtain the second electrode 70 with a relatively good shape.
After step S14, a passivation structure may be fabricated, and the double polished sapphire substrate 82 is removed to complete the fabrication of the micro led chip.
The foregoing disclosure is not intended to be limited to any form of embodiment, but is not intended to limit the disclosure, and any simple modification, equivalent changes and adaptations of the embodiments according to the technical principles of the disclosure are intended to be within the scope of the disclosure, as long as the modifications or equivalent embodiments are possible using the technical principles of the disclosure without departing from the scope of the disclosure.

Claims (9)

1. A micro light emitting diode chip, the micro light emitting diode chip comprising: a first semiconductor layer (10), a multiple quantum well layer (20), a second semiconductor layer (30), a transparent conductive layer (40), a passivation layer (50), a first electrode (60), and a second electrode (70);
the second semiconductor layer (30), the multiple quantum well layer (20), the first semiconductor layer (10) and the passivation layer (50) are sequentially laminated on the transparent conductive layer (40), the passivation layer (50) is provided with a through hole (51), the through hole (51) exposes the first semiconductor layer (10) and is opposite to the middle part of the first semiconductor layer (10), and the first electrode (60) is positioned in the through hole (51);
the second electrode (70) is located the surface that transparent conductive layer (40) kept away from second semiconductor layer (30), second electrode (70) include a plurality of first electrode piece (71), and a plurality of first electrode piece (71) are followed the edge interval arrangement of transparent conductive layer (40), second electrode (70) still include a plurality of second electrode piece (72), and a plurality of second electrode piece (72) are located the middle part of transparent conductive layer (40), and a plurality of second electrode piece (72) interval distribution, the quantity of second electrode piece (72) is less than the quantity of first electrode piece (71).
2. The micro light emitting diode chip according to claim 1, wherein a plurality of the second electrode blocks (72) are distributed in an array.
3. The micro light emitting diode chip according to claim 1, wherein the first electrode block and the second electrode block each comprise a first chromium layer (73), a tin-indium alloy layer (74) and an indium layer (75) laminated in this order on the transparent conductive layer (40).
4. A micro light emitting diode chip as claimed in claim 3, characterized in that the ratio of tin component in the tin-indium alloy layer (74) gradually decreases from the side close to the first chromium layer (73) to the side close to the indium layer (75).
5. The micro light emitting diode chip according to claim 4, wherein a rate of decrease of a tin component in the tin-indium alloy layer (74) gradually increases from a side near the first chromium layer (73) to a side near the indium layer (75).
6. A micro light emitting diode chip according to claim 3, characterized in that the thickness of the first chromium layer (73) is 400 to 600 angstroms, the thickness of the tin-indium alloy layer (74) is 0.8 to 1.2 μm, and the thickness of the indium layer (75) is 0.8 to 1.2 μm.
7. The micro light emitting diode chip according to any one of claims 1 to 6, wherein the first electrode (60) comprises a second chromium layer (61), a titanium layer (62) and a gold layer (63) sequentially laminated to the first semiconductor layer (10).
8. The micro light emitting diode chip according to claim 7, wherein the thickness of the second chromium layer (61) is 100to 300 a, the thickness of the titanium layer (62) is 100to 300 a, and the thickness of the gold layer (63) is 2000 to 4000 a.
9. The preparation method of the miniature light-emitting diode chip is characterized by comprising the following steps of:
providing a substrate;
sequentially growing a second semiconductor layer, a multiple quantum well layer, a first semiconductor layer and a first electrode on the substrate;
forming a passivation layer on the first semiconductor layer, wherein the passivation layer is provided with a through hole, the through hole exposes the first semiconductor layer and is opposite to the middle part of the first semiconductor layer, and the first electrode is positioned in the through hole;
the surface that the second semiconductor layer kept away from many quantum well layer forms transparent conducting layer and second electrode in proper order, the second electrode is located transparent conducting layer keeps away from the surface of second semiconductor layer, the second electrode includes a plurality of first electrode pieces, and is a plurality of first electrode pieces follow transparent conducting layer's edge interval arrangement, the second electrode still includes a plurality of second electrode pieces, and a plurality of second electrode pieces are located transparent conducting layer's middle part, and a plurality of second electrode piece interval distribution, the quantity of second electrode piece is less than the quantity of first electrode piece.
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