CN113707565B - 具有用于减小应力的成角度柱的半导体装置封装 - Google Patents

具有用于减小应力的成角度柱的半导体装置封装 Download PDF

Info

Publication number
CN113707565B
CN113707565B CN202110549392.7A CN202110549392A CN113707565B CN 113707565 B CN113707565 B CN 113707565B CN 202110549392 A CN202110549392 A CN 202110549392A CN 113707565 B CN113707565 B CN 113707565B
Authority
CN
China
Prior art keywords
semiconductor die
angled
pillar
long axis
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110549392.7A
Other languages
English (en)
Other versions
CN113707565A (zh
Inventor
S·U·阿里芬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of CN113707565A publication Critical patent/CN113707565A/zh
Application granted granted Critical
Publication of CN113707565B publication Critical patent/CN113707565B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/14177—Combinations of arrays with different layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1451—Function
    • H01L2224/14515—Bump connectors having different functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1451—Function
    • H01L2224/14515—Bump connectors having different functions
    • H01L2224/14517—Bump connectors having different functions including bump connectors providing primarily mechanical bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Wire Bonding (AREA)

Abstract

本申请涉及具有用于减小应力的成角度柱的半导体装置封装。本文公开半导体装置和相关联系统和方法，所述半导体装置具有例如成角度柱的机械柱结构，其为矩形且相对于半导体裸片取向以减小所述成角度柱附接到的半导体裸片处的弯曲应力和平面内剪应力。所述半导体装置可包含连接到所述半导体裸片且连接到封装衬底的成角度柱。所述成角度柱可经配置以使得其相对于局部应力方向取向，从而增加截面模量。

Description

具有用于减小应力的成角度柱的半导体装置封装
技术领域
本发明技术大体上涉及具有柱的半导体装置，且更具体地说在一些实施例中，涉及针对裸片到裸片、裸片到衬底和/或封装到封装互连件的成角度柱取向。
背景技术
微电子装置，例如存储器装置、微处理器和发光二极管，通常包含安装到衬底的一或多个半导体裸片。半导体裸片可包含功能特征，例如存储器单元、处理器电路和互连电路系统。半导体裸片还通常包含电耦合到功能特征的接合垫、电耦合到作用接合垫的作用柱，以及用于结构支撑的虚设柱。作用柱可以是引脚或用于将半导体裸片连接到总线、电路或其它组件的其它类型的结构。
半导体裸片可经由倒装芯片裸片附接工艺(例如，热压缩接合(TCB)或质量回流焊(mass reflow)操作)电耦合到另一衬底，其中导电柱形成于接合垫上，或裸片的其它区域经由安置在导电柱与衬底之间的接合材料耦合到衬底。举例来说，作用柱附接到衬底上的导电端子。为了将接合材料附接到衬底，加热半导体封装以回流焊接合材料且形成稳固连接。然而，加热半导体封装和/或随后冷却半导体封装以及在产品可靠性测试期间的热循环和终端客户使用期间的电力循环可引发半导体裸片与衬底之间因这些部件的热膨胀系数(CTE)的失配所致的显著热机械应力。通常，应力可引发一或多个接合垫附近的半导体裸片钝化材料中的界面分层和裂纹生长，这可导致半导体封装不可操作。
发明内容
本公开的一方面针对一种半导体装置，所述半导体装置包括：封装衬底，其包含电路元件；半导体裸片，其包含集成电路系统、电耦合到所述集成电路系统的作用接合垫以及与所述集成电路系统电隔离的非作用接合区域，其中所述半导体裸片具有作用表面，所述作用表面具有参考长轴、与所述参考长轴正交的参考短轴以及裸片中心坐标；以及成角度柱，其处于所述衬底与所述半导体裸片之间，其中所述成角度柱具有非圆形横截面形状，所述非圆形横截面形状具有柱长轴、柱短轴以及柱中心坐标，其中所述柱长轴至少大致与穿过所述裸片中心坐标和所述柱中心坐标的线正交，且其中所述线相对于所述参考长轴和所述参考短轴成倾斜角。
本公开的另一方面针对一种形成半导体装置的方法，所述方法包括：在半导体裸片上形成成角度柱，所述半导体裸片包含集成电路系统、电耦合到所述集成电路系统的作用接合垫和与所述集成电路系统电隔离的非作用接合区域，其中所述半导体裸片还具有作用表面，所述作用表面具有参考长轴、与所述参考长轴正交的参考短轴和裸片中心坐标，且所述成角度柱具有非圆形横截面形状，所述非圆形横截面形状具有柱长轴、柱短轴和柱中心坐标，且其中所述柱长轴至少大致与穿过所述裸片中心坐标和所述柱中心坐标的线正交，所述线相对于所述参考长轴和所述参考短轴成倾斜角；以及将所述成角度柱附接到封装衬底。
本公开的又一方面针对一种半导体装置，所述半导体装置包括：封装衬底，其包含电路元件；半导体裸片，其包含集成电路系统、电耦合到所述集成电路系统的作用接合垫以及与所述集成电路系统电隔离的非作用接合区域，其中所述半导体裸片还具有纵向尺寸和横向尺寸；以及成角度柱，其处于所述衬底与所述半导体裸片之间，其中所述成角度柱具有非圆形横截面形状，所述非圆形横截面形状具有第一尺寸、与所述第一尺寸正交且小于所述第一尺寸的第二尺寸以及柱中心坐标，其中所述第二尺寸沿着相对于所述纵向尺寸和所述横向尺寸两者成非零角度的轴线延伸。
附图说明
参考以下各图可更好地理解本发明技术的许多方面。图中部件未必按比例绘制。实际上，重点在于清楚地说明本发明技术的原理。
图1A是具有根据本发明技术的实施例配置的成角度柱的半导体封装的平面图；图1B是具有图1A的参考轴和半导体裸片的成角度柱的取向示例的坐标系图；以及图1C是图1A中所展示的半导体封装沿着线1C-1C的横截面图。
图2A和2B分别是图1C中所展示的半导体封装的一部分和根据本发明技术的实施例配置的成角度柱的横截面图和透视图。
图3A是展示相对于根据本发明技术的实施例配置的成角度柱的应力方向性的图，且图3B是展示相对于常规圆形柱的应力方向性的图。
图4A-4C是根据本发明技术的实施例的具有各种形状的成角度柱的横截面图。
图5A-5D说明根据本发明技术的实施例的具有各种形状的半导体封装的成角度柱和接合垫。
图6是包含根据本发明技术的实施例配置的半导体组件的系统的示意图。
具体实施方式
公开了具有机械矩形柱的半导体装置的若干实施例的特定细节，所述机械矩形柱基于应力的局部方向性而成角度以增加截面模量，且由此减少所述成角度柱与半导体裸片之间的界面处的弯曲应力和平面内剪应力。术语“半导体装置”一般指包含一或多种半导体材料的固态装置。半导体装置的实例包含逻辑装置、存储器装置、微处理器和二极管等等。此外，术语“半导体装置”可指成品装置或成为成品装置之前的各个处理阶段时的组件或其它结构。取决于其使用情境，术语“衬底”可指晶片级衬底或可指单分的裸片级衬底。相关领域的一般技术人员将认识到，可在晶片级或在裸片级执行本文所描述的方法。此外，除非上下文另有指示，否则可使用常规的半导体制造技术来形成本文公开的结构。举例来说，材料可使用化学气相沉积、物理气相沉积、原子层沉积、旋涂和/或其它合适的技术沉积。类似地，例如，可使用等离子蚀刻、湿式蚀刻、化学机械平坦化或其它合适的技术来移除材料。相关领域的技术人员还将理解，所述技术可具有额外实施例，且所述技术可在没有下文参考图1A-3A和4A-6描述的实施例的若干细节的情况下予以实践。
在下文描述的若干实施例中，半导体装置可包含含有电路元件的半导体衬底、作用接合垫和/或非作用接合区域以及相对于参考正交轴以倾斜角取向的成角度柱。所述半导体装置还可包含平行于或垂直于所述参考正交轴的对准柱。所述半导体装置的柱可通过接合材料附接到封装衬底的端子。成角度柱中的一些可连接到电学非作用接合区域，例如半导体衬底上的钝化材料上的区域。此类柱称为虚设柱。其它柱可电连接到与半导体衬底的电力、接地和/或其它电路元件电耦合的电学作用接合垫。此类柱是作用柱，且其可为成角度柱和/或对准柱。所述成角度柱可具有矩形横截面，且相对于参考正交轴以倾斜角(例如，除了平行于或垂直于与半导体衬底边缘对准的正交轴之外的角度)取向。在一些实施例中，成角度柱中的一些或全部可以不同倾斜角取向，或成角度柱中的一些或全部可以相同的倾斜角取向。成角度柱可基于由例如半导体裸片的热膨胀系数(CTE)与封装衬底的CTE之间的失配引起的芯片-封装界面(CPI)应力的局部方向而以某一角度取向。因此，成角度柱可减小接合垫和/或接合区域周围在例如已执行倒装芯片裸片附接处理(例如，热压缩接合(TCB)或质量回流焊)之后和/或在操作期间(例如，电力循环或极端温度环境)发生机械故障的可能性。
在TCB操作开始时，加热会使互连件中的接合材料回流焊且将导电柱电连接到封装衬底。半导体封装通常被加热到200℃或更高(例如高于约217℃)以使接合材料回流焊。在TCB操作期间，还施加压缩力以将互连件附接到封装衬底。TCB操作的一个缺点是，半导体封装的冷却可使半导体裸片和封装衬底相对于彼此扭曲或弯曲，这可能对柱施加应力。举例来说，半导体裸片的CTE可不同于封装衬底的CTE，且CTE差异性可使所述半导体裸片和封装衬底在半导体封装的冷却和/或加热期间相对于彼此扭曲。因此，封装衬底102在冷却后可能具有扭曲的非平面形状。在其它实施例中，半导体裸片或半导体裸片和封装衬底两者在冷却之后可能具有非平面扭曲形状。半导体裸片与封装衬底之间的CTE差异性可使互连件横向受压且弯曲。这可使裂纹在半导体衬底内形成且扩展，这可导致机械故障和/或电故障。
下文在具有矩形横截面且相对于应力方向成角度以提供能够承受CPI应力的充足截面模量的机械柱结构的上下文中描述本发明技术的许多实施例。相关领域的一般技术人员还将理解，本发明技术可具有用于在衬底组件的第一侧或第二侧形成具有矩形横截面的机械柱结构的实施例，且所述机械柱结构可在与半导体组件相关联的其它电连接器的上下文中使用。因此，本发明技术可在不具有本文中参考图1A-3A和4A-6所描述的实施例的若干细节的情况下予以实践。举例来说，已省略所属领域中众所周知的半导体装置和/或封装的一些细节，以免使本发明技术模糊不清。一般来说，应理解，除了本文公开的那些具体实施例之外的各种其它装置和系统可在本发明技术的范围内。
为了易于参考，贯穿本公开，相同附图标记用于标识类似或相似部件或特征，但使用相同附图标记并不暗示特征应理解为相同的。实际上，在本文中所描述的许多实例中，相同编号的特征具有在结构和/或功能上彼此不同的多个实施例。此外，除非本文中具体地标注，否则相同着色可用以指示横截面中可在成分上类似的材料，但使用相同着色并不暗示材料应理解为相同的。
如本文所使用，术语“竖直”、“横向”、“上部”、“下部”、“上方”和“下方”可指半导体装置中的特征鉴于图中所展示取向的相对方向或位置。举例来说，“上”或“最上”可指比另一特征更接近页面顶部定位的特征。然而，这些术语应在广义上予以解释以包含具有例如颠倒或倾斜取向的其它取向的半导体装置，其中顶部/底部、上/下、上方/下方、向上/向下和左/右可取决于取向而互换。
图1A是具有根据本发明技术的实施例配置的成角度柱120的半导体封装100(“封装100”)的平面图。封装100可包含封装衬底102、半导体裸片110，以及在封装衬底102与半导体裸片110之间延伸的成角度柱120。成角度柱120可相对于参考轴以倾斜角取向，所述倾斜角例如相对于由半导体裸片110的边缘限定的参考正交轴的非垂直且非平行角度。在一些实施例中，成角度柱120可称作外伸支腿(outrigger)。封装100可进一步包含至少基本上垂直于或平行于参考轴的对准柱130。取决于应用，成角度柱120和/或对准柱130可以是电耦合到封装衬底102和/或半导体裸片110中的电路系统的“作用柱”，或成角度柱120和/或对准柱130可以是未电耦合到封装衬底102和/或半导体裸片110中的一者或两者的“虚设柱”。
图1B是根据本发明技术的实施例的具有图1A的参考轴和半导体裸片110的成角度柱120的取向实例的坐标系图。如图1A和1B中展示，成角度柱120可具有非圆形横截面形状(例如，矩形、卵形、椭圆形、方形、直线或不规则形状)，其具有长轴140、短轴142和中心坐标144。成角度柱120的边缘可限定成角度柱120的平面图。中心坐标144可由成角度柱120的平面图的质心限定。在所说明的实施例中，长轴140和短轴142限定成角度柱120的平面，所述平面平行于半导体裸片110的作用表面。在一些其它实施例中，长轴140和短轴142可限定成角度柱120的平面，所述平面与半导体裸片110的作用表面正交。半导体裸片110的作用表面可具有参考长轴150、参考短轴152以及在作用表面中心处的中心坐标154。参考长轴150和参考短轴152可限定参考正交轴。当半导体裸片110具有直线覆盖区时，参考长轴150可至少基本平行于半导体裸片110的一个边缘，且参考短轴152可至少基本平行于半导体裸片110的正交边缘。半导体裸片110的边缘可限定半导体裸片110的平面图。中心坐标154可由半导体裸片110的平面图的质心限定。成角度柱120经取向以使得穿过中心坐标144和中心坐标154的线148(a)至少大致与成角度柱120的长轴140正交，且(b)相对于参考长轴150和短轴152成某一倾斜角。在一些实施例中，大致正交包含90度加减2到8度、3到7度、4到6度以及5度。在一些实施例中，成角度柱120可以标示为θi的旋转角156配置在半导体裸片110上。旋转角156可定义为θi＝tan-1(hi/wi)，其中(hi,wi)是成角度柱120相对于半导体裸片110的作用表面的中心坐标154的坐标位置。
在图1A所展示的实施例中，存在36个成角度柱120和20个作用柱130，但封装100可包含更少或更多的成角度柱120和作用柱130。举例来说，封装100可包含排列在半导体裸片100与封装衬底102之间的几十、几百、几千或更多个成角度柱120以及几十、几百、几千或更多个作用柱130。在一些实施例中，半导体裸片110上的成角度柱120可具有相同的尺寸(例如，长度、宽度和高度)。在其它实施例中，半导体裸片110上的一些成角度柱120可具有相同的尺寸，而其它成角度柱120可具有不同尺寸。在其它实施例中，半导体裸片110上的每个成角度柱120可具有不同尺寸。
图1C是图1A中所展示的封装100沿着线1C-1C的横截面图。在所说明的实施例中，半导体裸片110包含半导体衬底112(例如，硅衬底、砷化镓衬底、有机层压衬底等)，所述半导体衬底具有第一侧/表面113a和与第一侧113a相对的第二侧/表面113b。半导体衬底112的第一侧113a可为作用侧，其包含形成于第一侧113a中和/或其上的一或多个电路元件114(例如，示意性地示出的导线、迹线、互连件、晶体管等)和作用接合垫118。电路元件114可包含例如存储器电路(例如，动态随机存储器(DRAM)或其它类型的存储器电路)、控制器电路(例如，DRAM控制器电路)、逻辑电路和/或其它电路。在其它实施例中，半导体衬底112可为“空白”衬底，其不包含集成电路部件，且由例如晶体、半晶体和/或陶瓷衬底材料形成，这些材料例如硅、多晶硅、氧化铝(Al2O3)、蓝宝石和/或其它合适的材料。
封装衬底102可包含中介层、印刷电路板、电介质间隔物、另一半导体裸片(例如，逻辑裸片)或具有例如重布结构等电路系统的另一合适衬底。封装衬底102可进一步包含作用接合垫105以及电耦合到作用接合垫105的电连接器103(例如，焊球、导电凸块、导电柱、导电环氧树脂和/或其它合适的导电元件)。作用接合垫105和电连接器103经配置以将封装100电耦合到外部装置或电路系统(未展示)。封装衬底102还可包含未电耦合到电路系统的非作用垫108。
在所说明的实施例中，半导体衬底112的第一侧113a面向封装衬底102(例如，在直接芯片附接(DCA)配置中)。在其它实施例中，半导体裸片110可以不同方式布置。举例来说，半导体衬底112的第二侧113b可面向封装衬底102，且半导体裸片110可包含延伸穿过半导体衬底112以将电路元件114电耦合到作用柱120的一或多个TSV。此外，虽然图1C中仅展示单个半导体裸片110，但在其它实施例中，封装100可包含堆叠于半导体裸片110上和/或上方的一或多个额外半导体裸片。
在所说明的实施例中，半导体裸片110可通过经由接合材料106将非作用成角度柱120连接到非作用接合垫108而以机械方式连接到封装衬底102。成角度柱120可与半导体裸片110电隔离且由例如铜的材料形成。作用柱130可经由接合材料106电连接到半导体裸片110的作用接合垫118。作用柱130可由例如铜、镍、金、硅、钨、导电环氧树脂、其组合等任何合适的导电材料形成，且可通过使用电镀、化学镀(electroless-plating)或其它合适的工艺形成。在一些实施例中，例如镍、镍基金属间化合物和/或金的阻隔材料(未展示)可形成于作用柱130的端部分之上。阻隔材料可促进接合，和/或阻止或至少抑制用于形成作用柱130的铜或其它金属的电迁移。
在一些实施例中，封装100可进一步包含在封装衬底102上和/或至少部分地围绕半导体裸片110形成的底部填充物或模制材料。在一些实施例中，封装100可包含例如外部散热器、壳体(例如，导热壳体)、电磁干扰(EMI)屏蔽部件等其它部件。
图2A和2B分别是图1C中所展示的半导体封装100的一部分和根据本发明技术的实施例配置的成角度柱120的横截面图和透视图。成角度柱120可具有矩形横截面形状，而非具有长方形、圆形或方形横截面形状。图2B说明通过接合材料106连接到半导体裸片110的钝化材料以及封装衬底102的非作用垫108的成角度柱120。在一些实施例中，成角度柱120可通过接合材料和接合垫连接到半导体裸片110。作用柱130可包含大体上与成角度柱120的特征类似的特征。如图2A和2B中展示，成角度柱120相对于半导体裸片110的参考长轴150和参考短轴152以某一倾斜角取向。
图3A是展示相对于根据本发明技术的实施例配置的成角度柱120的应力方向性的图，且图3B是展示相对于常规圆形柱320的应力方向性的图。在图3A中，成角度柱120可成角度地取向，使得成角度柱的长轴至少基本上垂直于局部应力的方向，以增加截面模量。由于CTE失配和扭曲是导致热机械应力的两个主要成分，因此半导体裸片110处的裂纹萌生和裂纹扩展主要发生在混合模式断裂中(例如，模式I：剥离，以及模式II：平面内剪切)。归因于在各种组装和测试事件期间的热负载情形，最大局部应力的方向在成角度柱120中不是水平的或竖直的，而是基于成角度柱120相对于半导体裸片110的中心的位置而改变。当成角度柱120在应力的方向上成角度地取向时，与圆形柱相比，矩形横截面可提供更大截面模量。增大的截面模量可帮助减少半导体裸片100处的弯曲应力和平面内剪应力，这预期会减少开裂、分层和其它不合需要的事件。成角度柱120的横截面积可取决于间距而恒定或增加，以减小法向应力。
比较图3A和3B，在成角度柱120(图3A)例如在最外拐角的成角度柱处的情况下钝化材料中的应力轮廓显著地小于圆形柱320(图3B)的应力轮廓。更具体地说，成角度柱120的右上方区域处所指示的应力的大小和量值小于圆形柱320的应力的大小和量值。因此，与圆形柱相比，成角度柱102预期提供剥离和平面内剪应力的改进。
表1展示与圆形柱相比，当矩形成角度柱在半导体封装的最外拐角中时剥离应力和平面内剪应力减小的显著改进。举例来说，圆形柱的最大剥离应力和最大平面内剪应力分别是625MPa和191MPa。方形柱的最大剥离应力和最大平面内剪应力分别比圆形柱的所述应力高15％(721MPa)以及低27％(139MPa)。矩形成角度柱120的最大剥离应力和最大平面内剪应力分别比圆形柱的所述应力低24％(478MPa)以及低42％(110MPa)。
图4A-4C是根据本发明技术的实施例的具有各种形状的成角度柱的横截面图。图4A说明包含矩形横截面形状的成角度柱120。图4B说明包含卵形或椭圆形横截面形状的成角度柱402。图4C说明包含长方形横截面形状的成角度柱404。在这些说明的实施例中，沿着长轴140的成角度柱120、402和404的长度长于宽度。成角度柱的形状可包含但不限于不规则形状、直线和梯形。
图5A-5D说明具有各种形状且根据本发明技术的实施例配置的半导体封装100的成角度柱和接合垫。可使用接合垫的各种形状和大小，以覆盖成角度柱的整个横截面。图5A说明覆盖矩形成角度柱120的整个横截面的矩形接合垫108。图5B说明覆盖矩形成角度柱120的整个横截面的圆形接合垫508。图5C说明覆盖卵形或椭圆形成角度柱402的整个横截面的圆形接合垫508。图5D说明覆盖长方形成角度柱404的整个横截面的圆形接合垫508。作用柱130可同样拥有与图5A-5D中说明的成角度柱的特征类似的特征。图5A-5D说明垫上柱(pillar on pad)的形成；然而，这些实施例也可结合迹线上柱(pillar on trace)的应用来使用。
图6是包含根据本发明技术的实施例配置的半导体组件的系统的示意图。具有上文参考图1A-1C、2A-2B、3A、4A-4C、5A-5D所描述的特征的半导体装置和/或封装中的任一者可并入到大量更大和/或更复杂的系统中的任一者中，所述系统的代表性实例是在图6中示意性地展示的系统600。系统600可包含处理器602、存储器604(例如，SRAM、DRAM、快闪和/或其它存储器装置)、输入/输出装置606，和/或其它子系统或部件608。上文参考图1A-1C、2A-2B、3A、4A-4C、5A-5D描述的半导体裸片和/或封装可包含在图6中展示的任一个元件中。所得系统600可经配置以执行广泛多种合适的计算、处理、存储、感测、成像和/或其它功能中的任一者。相应地，系统600的代表性实例包含但不限于，计算机和/或其它数据处理器，例如，台式计算机、笔记本电脑、网络家电、手持式装置(例如，掌上计算机、可穿戴计算机、蜂窝或移动电话、个人数字助理、音乐播放器等)、平板电脑、多处理器系统、基于处理器的或可编程的消费型电子装置、网络计算机和微型计算机。系统600的额外代表性实例包含灯、相机、车辆等。关于这些和其它实例，系统600可容纳在单个单元中或例如通过通信网络分布在多个互连单元上。相应地，系统600的部件可包含本地和/或远程存储器存储装置和广泛多种合适的计算机可读媒体中的任一者。
从前文应了解，本文中已出于说明的目的描述了所述技术的具体实施例，但可在不偏离本公开的情况下进行各种修改。因此，本发明不受所附权利要求书之外的限制。此外，在特定实施例的上下文中描述的新技术的某些方面也可在其它实施例中组合或去除。此外，尽管已在那些实施例的上下文中描述了与新技术的某些实施例相关联的优势，但其它实施例也可展现此类优势，且并非所有实施例都要展现此类优势以落入所述技术的范围内。因此，本公开和相关联的技术可涵盖未明确地在本文中展示或描述的其它实施例。

Claims (18)

1.一种半导体装置，其包括：
封装衬底，其包含电路元件；
半导体裸片，其包含集成电路系统、电耦合到所述集成电路系统的作用接合垫以及与所述集成电路系统电隔离的非作用接合区域，其中所述半导体裸片具有作用表面，所述作用表面具有参考长轴、与所述参考长轴正交的参考短轴以及裸片中心坐标；以及
成角度柱，其处于所述衬底与所述半导体裸片之间，其中所述成角度柱具有非圆形横截面形状，所述非圆形横截面形状具有柱长轴、柱短轴以及柱中心坐标，其中所述柱长轴至少大致与穿过所述裸片中心坐标和所述柱中心坐标的线正交，且其中所述线相对于所述参考长轴和所述参考短轴成倾斜角，
其中所述成角度柱中的第一组电耦合到所述半导体裸片的作用接合垫。
2.根据权利要求1所述的半导体装置，其中大致正交是90度加减2到8度、3到7度、4到6度或5度。
3.根据权利要求1所述的半导体装置，其中所述非圆形横截面形状是矩形。
4.根据权利要求1所述的半导体装置，其中所述非圆形横截面形状包含卵形、椭圆形、方形、直线或不规则形状。
5.根据权利要求1所述的半导体装置，其中所述成角度柱中的第二组连接到所述半导体裸片的非作用接合区域。
6.根据权利要求1所述的半导体装置，其进一步包括对准柱，所述对准柱具有至少基本上平行于所述参考长轴或所述参考短轴中的一者的柱长轴，且其中所述对准柱电耦合到所述半导体裸片的作用接合垫。
7.根据权利要求1所述的半导体装置，其进一步包括对准柱，所述对准柱具有至少基本上平行于所述参考长轴或所述参考短轴中的一者的柱长轴，且其中所述对准柱电耦合到所述半导体裸片的作用接合垫，且所述成角度柱中的第二组耦合到所述半导体裸片的非作用接合区域。
8.根据权利要求1所述的半导体装置，其进一步包括对准柱，所述对准柱具有至少基本上平行于所述参考长轴或所述参考短轴的柱长轴，且其中所述对准柱电耦合到所述半导体裸片的作用接合垫，且所述成角度柱中的第二组耦合到所述半导体裸片的非作用接合区域。
9.一种形成半导体装置的方法，所述方法包括：
在半导体裸片上形成成角度柱，所述半导体裸片包含集成电路系统、电耦合到所述集成电路系统的作用接合垫和与所述集成电路系统电隔离的非作用接合区域，其中所述半导体裸片还具有作用表面，所述作用表面具有参考长轴、与所述参考长轴正交的参考短轴和裸片中心坐标，且所述成角度柱具有非圆形横截面形状，所述非圆形横截面形状具有柱长轴、柱短轴和柱中心坐标，且其中所述柱长轴至少大致与穿过所述裸片中心坐标和所述柱中心坐标的线正交，所述线相对于所述参考长轴和所述参考短轴成倾斜角；以及
将所述成角度柱附接到封装衬底，
其中所述成角度柱中的第一组电耦合到所述半导体裸片的作用接合垫。
10.根据权利要求9所述的方法，其中大致正交是90度加减2到8度、3到7度、4到6度或5度。
11.根据权利要求9所述的方法，其中所述非圆形横截面形状是矩形。
12.根据权利要求9所述的方法，其中所述非圆形横截面形状包含卵形、椭圆形、方形、直线或不规则形状。
13.根据权利要求9所述的方法，其中所述成角度柱中的第二组连接到所述半导体裸片的非作用接合区域。
14.根据权利要求9所述的方法，其进一步包括对准柱，所述对准柱具有至少基本上平行于所述参考长轴或所述参考短轴中的一者的柱长轴，且其中所述对准柱电耦合到所述半导体裸片的作用接合垫。
15.根据权利要求9所述的方法，其进一步包括对准柱，所述对准柱具有至少基本上平行于所述参考长轴或所述参考短轴中的一者的柱长轴，且其中所述对准柱电耦合到所述半导体裸片的作用接合垫，且所述成角度柱中的第二组耦合到所述半导体裸片的非作用接合区域。
16.根据权利要求9所述的方法，其进一步包括对准柱，所述对准柱具有至少基本上平行于所述参考长轴或所述参考短轴的柱长轴，且其中所述对准柱电耦合到所述半导体裸片的作用接合垫，且所述成角度柱中的第二组耦合到所述半导体裸片的非作用接合区域。
17.一种半导体装置，其包括：
封装衬底，其包含电路元件；
半导体裸片，其包含集成电路系统、电耦合到所述集成电路系统的作用接合垫以及与所述集成电路系统电隔离的非作用接合区域，其中所述半导体裸片还具有纵向尺寸和横向尺寸；以及
成角度柱，其处于所述衬底与所述半导体裸片之间，其中所述成角度柱具有非圆形横截面形状，所述非圆形横截面形状具有第一尺寸、与所述第一尺寸正交且小于所述第一尺寸的第二尺寸以及柱中心坐标，其中所述第二尺寸沿着相对于所述纵向尺寸和所述横向尺寸两者成非零角度的轴线延伸，
其中所述成角度柱中的第一组电耦合到所述半导体裸片的作用接合垫。
18.根据权利要求17所述的半导体装置，其进一步包括对准柱，所述对准柱具有至少基本上平行于所述纵向尺寸或所述横向尺寸的柱长轴，且其中所述对准柱电耦合到所述半导体裸片的作用接合垫，且所述成角度柱中的第二组耦合到所述半导体裸片的非作用接合区域。
CN202110549392.7A 2020-05-20 2021-05-20 具有用于减小应力的成角度柱的半导体装置封装 Active CN113707565B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/879,637 US11164837B1 (en) 2020-05-20 2020-05-20 Semiconductor device packages with angled pillars for decreasing stress
US16/879,637 2020-05-20

Publications (2)

Publication Number Publication Date
CN113707565A CN113707565A (zh) 2021-11-26
CN113707565B true CN113707565B (zh) 2024-04-12

Family

ID=78331395

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110549392.7A Active CN113707565B (zh) 2020-05-20 2021-05-20 具有用于减小应力的成角度柱的半导体装置封装

Country Status (3)

Country Link
US (2) US11164837B1 (zh)
CN (1) CN113707565B (zh)
TW (1) TWI785607B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11404390B2 (en) * 2020-06-30 2022-08-02 Micron Technology, Inc. Semiconductor device assembly with sacrificial pillars and methods of manufacturing sacrificial pillars

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367293A (zh) * 2012-03-27 2013-10-23 联发科技股份有限公司 半导体封装
CN103748679A (zh) * 2011-07-21 2014-04-23 高通股份有限公司 具有取决于在裸片上的位置的定向或几何形状或在支柱与裸片垫片之间形成有图案化结构以用于减少热应力的顺应互连支柱

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7433201B2 (en) * 2000-09-08 2008-10-07 Gabe Cherian Oriented connections for leadless and leaded packages
US20070045812A1 (en) * 2005-08-31 2007-03-01 Micron Technology, Inc. Microfeature assemblies including interconnect structures and methods for forming such interconnect structures
KR101388538B1 (ko) * 2007-09-28 2014-04-23 테세라, 인코포레이티드 이중 포스트를 사용하여 플립칩 상호연결한 마이크로전자 어셈블리
US20120098120A1 (en) * 2010-10-21 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Centripetal layout for low stress chip package
US8288871B1 (en) * 2011-04-27 2012-10-16 Taiwan Semiconductor Manufacturing Company, Ltd. Reduced-stress bump-on-trace (BOT) structures
US9053989B2 (en) * 2011-09-08 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Elongated bump structure in semiconductor device
US9233835B2 (en) * 2011-12-06 2016-01-12 Intel Corporation Shaped and oriented solder joints
US9437534B2 (en) * 2012-02-29 2016-09-06 Mediatek Inc. Enhanced flip chip structure using copper column interconnect
US9159695B2 (en) * 2013-01-07 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Elongated bump structures in package structure
US9515002B2 (en) * 2015-02-09 2016-12-06 Micron Technology, Inc. Bonding pads with thermal pathways
KR102109569B1 (ko) * 2015-12-08 2020-05-12 삼성전자주식회사 전자부품 패키지 및 이를 포함하는 전자기기
US10790254B2 (en) * 2018-05-09 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure
US11515232B2 (en) * 2019-04-09 2022-11-29 Intel Corporation Liquid cooling through conductive interconnect

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103748679A (zh) * 2011-07-21 2014-04-23 高通股份有限公司 具有取决于在裸片上的位置的定向或几何形状或在支柱与裸片垫片之间形成有图案化结构以用于减少热应力的顺应互连支柱
CN103367293A (zh) * 2012-03-27 2013-10-23 联发科技股份有限公司 半导体封装

Also Published As

Publication number Publication date
US11721658B2 (en) 2023-08-08
US20210366859A1 (en) 2021-11-25
CN113707565A (zh) 2021-11-26
TWI785607B (zh) 2022-12-01
US20220028814A1 (en) 2022-01-27
TW202147535A (zh) 2021-12-16
US11164837B1 (en) 2021-11-02

Similar Documents

Publication Publication Date Title
US11848282B2 (en) Semiconductor devices having crack-inhibiting structures
US11616028B2 (en) Semiconductor devices having crack-inhibiting structures
US20230145473A1 (en) Semiconductor assemblies with redistribution structures for die stack signal routing
US20210066148A1 (en) Semiconductor package
US20230154868A1 (en) Semiconductor devices with reinforced substrates
JP2022016372A (ja) 半導体パッケージの接合構造およびその製造方法
CN113707565B (zh) 具有用于减小应力的成角度柱的半导体装置封装
US9478482B2 (en) Offset integrated circuit packaging interconnects
TWI610403B (zh) 基板結構及其製法與電子封裝件
CN113130328B (zh) 具有变窄部分的半导体互连结构，以及相关联系统及方法
US11728307B2 (en) Semiconductor interconnect structures with conductive elements, and associated systems and methods
US12068303B2 (en) Package structure
US11804445B2 (en) Method for forming chip package structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant