CN113707204B - Memory programming method and system - Google Patents
Memory programming method and system Download PDFInfo
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- CN113707204B CN113707204B CN202111011940.7A CN202111011940A CN113707204B CN 113707204 B CN113707204 B CN 113707204B CN 202111011940 A CN202111011940 A CN 202111011940A CN 113707204 B CN113707204 B CN 113707204B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The application provides a memory and a programming method thereof, comprising the following steps: applying an initial programming pulse to a memory cell in a programmed state among the plurality of memory cells; selecting a memory cell of a first memory state among memory cells to which an initial program pulse is applied, wherein a threshold voltage of the memory cell of the first memory state is the smallest among the memory cells of the plurality of memory states; determining a first storage subunit and a second storage subunit from the storage units in the first storage state; in response to the number of first memory sub-cells being greater than a predetermined value, repeatedly applying a high programming pulse and a low programming pulse to the first memory sub-cells and the second memory sub-cells, respectively, until the number of first memory sub-cells is less than the predetermined value; and starting verification from the memory cell in the second memory state.
Description
Technical Field
The present application relates to the field of semiconductor design and fabrication, and more particularly, to a structure of a three-dimensional memory (3D NAND) and a method of fabricating the same.
Background
The NAND flash memory chip has the characteristics of multiple times of programming, high storage density, high reading and writing speed, suitability for storing a large amount of data and the like, and is widely and increasingly applied. For example, flash memory devices have been widely used in smart phones, cloud storage, solid state drives of computers, and other fields.
Existing NAND is often programmed using a progressive step pulse programming (Incremental Step Pulse Programming, ISPP) method in combination with a fail bit count (Fail Bit Counting, FBC) method. In the whole programming process, a plurality of programming pulses are required to be applied to the memory cell, verification operation is required to be performed after each programming operation, and if the threshold voltage of the memory cell is greater than or equal to a preset verification voltage, the verification is passed, and the programming operation is finished; otherwise, if the threshold voltage of the memory cell is smaller than the verification voltage, the verification fails, the number of the failed memory cells needs to be counted, and the higher pulse programming voltage is applied to the failed memory cells until the verification passes, and programming is finished.
However, the number of failed memory cells and the verification of the threshold voltage of the memory cells need to occupy a lot of time, which reduces the read-write speed of the memory, so that the reduction of the number of times of verifying the threshold voltage of the memory cells is a problem to be solved at present on the premise of ensuring the accuracy of data storage. In addition, there is a limit to the memory fail bit counting capability, and increasing the upper limit of the memory fail bit counting capability requires a larger circuit area and time for counting. Therefore, reducing the upper limit requirement for memory fail bit counting capability is also a problem that needs to be addressed at present.
Disclosure of Invention
The present application provides a memory programming method and system that at least partially addresses the above-identified problems of the prior art.
According to one aspect of the present application, there is provided a method of programming a memory, the memory including a plurality of memory cells, the method may include: applying an initial programming pulse to a memory cell in a programmed state among the plurality of memory cells; selecting a memory cell of a first memory state among the memory cells to which the initial programming pulse is applied, wherein a threshold voltage of the memory cell of the first memory state is the smallest among the memory cells of the plurality of memory states; determining a first storage subunit and a second storage subunit from the storage units in the first storage state, wherein the threshold voltage of the first storage subunit is smaller than a first verification voltage, and the threshold voltage of the second storage subunit is larger than the first verification voltage and smaller than a second verification voltage; in response to the number of first memory sub-cells being greater than a predetermined value, repeatedly applying a high programming pulse and a low programming pulse to the first memory sub-cells and the second memory sub-cells, respectively, until the number of first memory sub-cells is less than a predetermined value; and verifying from the memory cells of the second memory state, wherein the threshold voltage of the memory cells of the second memory state is only greater than the threshold voltage of the first memory state.
In one embodiment of the present application, the method may further include: the number of the first sub-memory cells is confirmed while high and low program pulses are applied to the first and second memory sub-cells, respectively.
In one embodiment of the present application, after repeatedly applying the high programming pulse and the low programming pulse to the first memory subunit and the second memory subunit, respectively, the method may further include: the threshold voltage of the first memory sub-cell and the threshold voltage of the second memory sub-cell are compared with the first verification voltage and the second verification voltage, respectively, to reconfirm the number of the first memory sub-cells.
In one embodiment of the present application, the memory cell of the first memory state may further include a third memory sub-cell having a threshold voltage greater than the second verification voltage, wherein the method may further include: a program inhibit pulse is applied to the third memory cell.
In one embodiment of the present application, the method may further include: for a memory cell of the plurality of memory cells to be programmed to a highest memory state, in response to the number of the first memory sub-cells being greater than a predetermined value, a programming pulse that is not less than the high programming pulse is applied to the memory cell, wherein a threshold voltage of the memory cell to be programmed to the highest memory state is greater than a threshold voltage of the memory cells in the remaining memory states.
In one embodiment of the present application, the predetermined value may be determined according to a maximum value of error correction capability of the memory.
Another aspect of the present application provides a memory, the system may include: a memory array including a plurality of memory cells; a voltage supply circuit; and a controller configured to: controlling the voltage supply circuit to apply an initial programming pulse to a memory cell in a programmed state among the plurality of memory cells; selecting a memory cell of a first memory state among the memory cells to which the initial programming pulse is applied, wherein a threshold voltage of the memory cell of the first memory state is the smallest among the memory cells of the plurality of memory states; determining a first storage subunit and a second storage subunit from the storage units in the first storage state, wherein the threshold voltage of the first storage subunit is smaller than a first verification voltage, and the threshold voltage of the second storage subunit is larger than the first verification voltage and smaller than a second verification voltage; in response to the number of first memory sub-cells being greater than a predetermined value, repeatedly applying a high programming pulse and a low programming pulse to the first memory sub-cells and the second memory sub-cells, respectively, until the number of first memory sub-cells is less than a predetermined value; and verifying from the memory cells of the second memory state, wherein the threshold voltage of the memory cells of the second memory state is only greater than the threshold voltage of the first memory state.
In one embodiment of the present application, the controller may be configured to: the number of the first memory subcells is confirmed while a high programming pulse is applied to the first memory subcell and a low programming pulse is applied to the second memory subcell.
In one embodiment of the present application, the controller may be configured to: after the high programming pulse and the low programming pulse are repeatedly applied to the first memory sub-cell and the second memory sub-cell, respectively, using the voltage supply circuit, the threshold voltage of the first memory sub-cell and the threshold voltage of the second memory sub-cell are compared with the first verification voltage and the second verification voltage, respectively, to reconfirm the number of the first memory sub-cells.
In one embodiment of the present application, the memory cell of the first memory state may further include a third memory subunit having a threshold voltage greater than the second verification voltage, and the controller may be configured to: a program inhibit pulse is applied to the third memory subunit with the voltage supply circuit.
In one embodiment of the present application, the controller may be configured to: for a memory cell of the plurality of memory cells to be programmed to a highest memory state, in response to the number of the first memory sub-cells being greater than a predetermined value, a programming pulse that is not less than the high programming pulse is applied to the memory cell, wherein a threshold voltage of the memory cell to be programmed to the highest memory state is greater than a threshold voltage of the memory cells in the remaining memory states.
In one embodiment of the present application, the predetermined value may be determined according to a maximum value of error correction capability of the memory.
The present application also provides a memory system, which may include: a memory storing computer-executable instructions; and a processor for executing the computer executable instructions stored in the memory to implement the above method.
According to the memory programming method and system, through counting the number of the first sub-memory units, when the number of the first sub-memory units is smaller than the preset value, programming is started from the memory units in the second memory state, so that the threshold voltage verification time of the memory units in the first memory state is saved, the programming time of the memory is shortened to a certain extent, and the efficiency of the memory is improved. And only the number of the first sub-storage units is counted, the number to be counted is small, and the corresponding counting circuit is simple. In addition, the conventional fail bit count approach is to count the sum of the numbers of the first and second sub-memory cells. The embodiment of the application is to count the number of the first sub-memory units, so that the upper limit requirement on the memory failure bit counting capability is greatly reduced. The method is beneficial to reducing the area and counting time of the memory circuit, and can also reduce the programming time of the memory to a certain extent and improve the programming efficiency of the memory.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments, made with reference to the following drawings. Wherein:
FIG. 1 is a schematic flow chart of a programming method of a memory according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a memory block according to an embodiment of the present application;
FIG. 3 is a schematic diagram of threshold voltage distribution after TLC memory cell programming according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a memory cell in the same memory state divided into memory sub-cells according to an embodiment of the present application;
FIG. 5 is a flow chart of a memory cell programming portion according to an embodiment of the present application; and
fig. 6 is a schematic diagram of a memory system according to an embodiment of the present application.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed description are merely illustrative of exemplary embodiments of the application and are not intended to limit the scope of the application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.
In the drawings, the size, dimensions and shape of elements have been slightly adjusted for convenience of description. The figures are merely examples and are not drawn to scale. As used herein, the terms "about," "approximately," and the like are used as terms of a table approximation, not as terms of a table degree, and are intended to account for inherent deviations in measured or calculated values that will be recognized by one of ordinary skill in the art. In addition, in this application, the order in which the processes of the steps are described does not necessarily indicate the order in which the processes occur in actual practice, unless explicitly defined otherwise or the context may be inferred.
It will be further understood that terms such as "comprises," "comprising," "includes," "including," "having," "containing," "includes" and/or "including" are open-ended, rather than closed-ended, terms that specify the presence of the stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of the following" appears after a list of features listed, it modifies the entire list of features rather than just modifying the individual elements in the list. Furthermore, when describing embodiments of the present application, use of "may" means "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless otherwise defined, all terms (including engineering and technical terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In addition, embodiments and features of embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1 is a flowchart of a method for programming a memory according to an embodiment of the present application. As shown in fig. 1, a method 1000 of programming a memory may include:
step S110: an initial programming pulse is applied to a memory cell in a programmed state among the plurality of memory cells.
Step S120: selecting a memory cell of a first memory state among memory cells to which an initial program pulse is applied; wherein the threshold voltage of the memory cell of the first memory state is the smallest among the memory cells of the plurality of memory states.
Step S130: and determining a first storage subunit and a second storage subunit from the storage units in the first storage state, wherein the threshold voltage of the first storage subunit is smaller than the first verification voltage, and the threshold voltage of the second storage subunit is larger than the first verification voltage and smaller than the second verification voltage.
Step S140: in response to the number of first memory sub-cells being greater than a predetermined value, repeatedly applying a high programming pulse and a low programming pulse to the first memory sub-cells and the second memory sub-cells, respectively, until the number of first memory sub-cells is less than the predetermined value.
Step S150: verification begins with a memory cell in a second memory state, wherein the threshold voltage of the memory cell in the second memory state is only greater than the threshold voltage of the first memory state.
The steps of the above-described preparation method 1000 will be specifically described below in conjunction with fig. 2 to 6.
The programming method 1000 of the memory according to the embodiment of the present application starts at step S110, where an initial programming pulse is applied to a memory cell in a programmed state among a plurality of memory cells of the memory. As understood in the art, a memory may generally include a plurality of memory cells arranged in an array. Fig. 2 shows a schematic diagram of a memory 200 that may be suitable for use in the method 1000 described above. As shown in fig. 2, the memory 200 may include a plurality of memory blocks, each of which includes a plurality of memory cells 201 arrayed in a three-dimensional space, and a plurality of memory strings 210 are configured such that channels of the memory cells located in the same memory string 210 are physically connected. The gates of the plurality of memory cells 201 are controlled by the same word line WL, and the memory cells 201 can be in an erased state or a programmed state by applying different programming voltages to the word line WL. The memory cell 201 may be connected to a word line WL and a bit line BL, while the memory cell 201 may also be connected to other select lines, such as a string select line SSL, a ground select line GSL, a common source line CSL, and the like. The number of memory cells, the number of word lines WL, and the bit lines BL are exemplary illustrations, and the present application is not limited thereto.
The memory 200 may be classified according to the number of bits that each memory cell can store, and the number of bits that each memory cell can store may also determine the number of memory states that the memory contains. For example, one memory cell of a single-level cell SLC (single-level cell) memory can store one bit, having two memory states; a multi-level cell (MLC) memory has one memory cell capable of storing two bits, with four memory states; three-level cell (TLC) memory has eight memory states, one memory cell can store three bits; a four-level cell QLC (quad-level cell) memory has one memory cell capable of storing four bits, with sixteen memory states; five-level cell PLC (penta-level cell) memory one memory cell can store five bits, with thirty-two memory states. However, it will be appreciated by those skilled in the art that embodiments of the present application are not particularly limited in terms of the type of memory, and that any suitable memory is permissible without departing from the present invention.
In step S120, a memory cell in the first memory state is selected. Specifically, each memory cell may be divided into an erase state and a program state according to whether or not data is written, in which an initial program pulse is applied to the memory cells in the program state, and a memory cell of a first memory state, of which a threshold voltage is the smallest among the memory cells of a plurality of memory states, is selected among the memory cells to which the initial program pulse is applied. The present application is described with reference to TLC memory. FIG. 3 is a schematic diagram of threshold voltage distribution after TLC memory cell programming according to an embodiment of the present application. As shown in fig. 3, the horizontal axis represents the threshold voltage of the memory cell, the vertical axis represents the number of memory cells, and the curve represents the normal distribution of the number of memory cells at different threshold voltages. One memory cell of the TLC flash memory may store 3 bits of data, i.e., each memory cell may have 8 different memory states, including an erased state P0 and programmed states P1-P7. The memory cell threshold voltages in different memory states are different. The threshold voltage of the memory cell of the first memory state, i.e., the P1 state, is smallest among the memory cells of the plurality of memory states.
After selecting the memory cell of the first memory state from among the memory cells to which the program pulse is applied, a first memory sub-cell and a second memory sub-cell are determined from among the memory cells of the first memory state in step S130, wherein a threshold voltage in the first memory sub-cell is less than a first verification voltage and a threshold voltage of the second memory sub-cell is greater than the first verification voltage and less than a second verification voltage. Fig. 4 is a schematic diagram of dividing a memory cell in the same memory state into memory sub-cells according to an embodiment of the present application. As shown in fig. 4, the solid line represents a memory state that may be a distribution of threshold voltages after a program pulse is applied to any one of the memory cells in a programmed state, and the dotted line represents a state in which the memory cell corresponding to the solid line is finally required to be programmed. PVL is the first verification voltage, PV is the second verification voltage, when the threshold voltage of the memory cell is greater than the second verification voltage PV, it is indicated that the memory cell has completed programming of the current memory state. Taking the first memory state, i.e., the P1 state as an example, after the programming pulse is applied to the memory cells, the distribution of the memory cells is shown as a solid line in fig. 4, and the memory cells are verified, i.e., the threshold voltages of the memory cells are compared with the first verifying voltage PVL and the second verifying voltage PV, respectively, the memory cells having the threshold voltages smaller than the first verifying voltage PVL are denoted as the first memory sub-cells 410, the memory cells having the threshold voltages larger than the first verifying voltage PVL and smaller than the second verifying voltage PV are denoted as the second memory sub-cells 420, and the memory cells having the threshold voltages larger than the second verifying voltage PV are denoted as the third memory sub-cells 430.
FIG. 5 is a flow chart of a memory cell programming portion according to an embodiment of the present application. In one embodiment, after a program pulse is applied to a memory cell in a programmed state, threshold voltages of memory cells to be programmed to P1, P2 and P3 states are verified, i.e., the threshold voltages of the memory cells are compared with first and second verifying voltages PVL and PV in P1, P2 and P3 states, respectively, and the memory cells to be programmed to P1, P2 and P3 states are divided into first, second and third memory sub-cells 410, 420 and 430.
After the first, second and third memory sub-units 410, 420 and 430 are distinguished, different program pulses are applied to the first, second and third memory sub-units 410, 420 and 430, respectively. As shown in fig. 5, the process node 510 determines the number of the first memory cells 410 by Fail Bit Count (FBC) method, and applies a high program pulse to the first memory sub-cells 410, a low program pulse to the second memory sub-cells 420, and a program inhibit pulse to the third memory sub-cells 430. In response to the number of first memory sub-units 410 being greater than the predetermined value, the threshold voltage of the first memory sub-units 410 and the threshold voltage of the second memory sub-units 420 are compared with the first verification voltage PVL and the second verification voltage PV, respectively, to reconfirm the number of the first memory sub-units 410 in step S150, wherein the predetermined value may be a fixed value or a voltage interval, for example, 200-400 mV millivolts, and the predetermined value in the present application may be determined according to the maximum value of the error correction capability of the memory, i.e., error checking and correction (Error Checking and Correcting, ECC for short) of the memory system. Since the fail bit count counts the number of the first memory sub-cells 410 while the high program pulse is continuously applied to the first memory sub-cells 410, the fail bit count counts the number of the first memory sub-cells 410 to be greater than the actual number of the first memory sub-cells 410. The number of actual first memory sub-units 410 should be smaller than the maximum value of the error correction capability, and the size of the high programming pulse that is continuously applied to the first memory sub-units 410 can be adjusted according to the actual application, which further affects the number of actual first memory sub-units 410. The predetermined value can be confirmed based on the maximum value of the error correction capability and engineering experience.
By using the progressive step pulse programming (Incremental Step Pulse Programming, abbreviated ISPP) method, the high programming pulse and the low programming pulse are repeatedly applied to the first memory sub-unit 410 and the second memory sub-unit 420, respectively, the threshold voltages of the first memory sub-unit 410 and the second memory sub-unit 420 are further increased, and the number of the first memory sub-units 410 is reduced until the number of the first memory sub-units is smaller than a predetermined value.
In the prior art, the number of the first memory cells 410 and the second memory cells 420 is determined by using a Fail Bit Count (FBC) method, compared with the number of the first memory cells 410 counted in the prior art, the number of the memory cells counted in the prior art is more, the corresponding counting circuit for counting the number of the memory cells is relatively complex, the counting range of the corresponding counting circuit for counting the number of the memory cells is limited, and the predetermined value is at a risk of exceeding the capability of the counting circuit.
In another embodiment of the present application, for the memory cell in the highest memory state, i.e., the memory cell in the plurality of memory states, the threshold voltage is the largest, e.g., the memory cell in fig. 3 that needs to be programmed to the P7 state, if the number of the first memory sub-cells in the memory cell that needs to be programmed to the P7 state is greater than the predetermined value, the final programming pulse may be directly applied to the first memory sub-cell and the second memory sub-cell, where the final programming pulse may be one larger programming pulse, e.g., the final programming pulse is greater than the high programming pulse. The threshold voltages of the first memory sub-unit and the second memory sub-unit can be greatly increased, and the number of the first memory sub-units is smaller than a preset value.
As shown in fig. 5, in the process node 520 and subsequent processes, in step 150, the number of first memory sub-cells is less than a predetermined value, and verification is started from a memory cell in a second memory state (i.e., a memory cell that needs to be programmed to a P2 state), wherein the threshold voltage of the memory cell in the second memory state is only greater than the threshold voltage of the first memory state. When the number of the first memory sub-units is smaller than a predetermined value, that is, the threshold voltage of the memory unit does not reach the second verification voltage, the memory can execute ECC during the reading process, and the first memory sub-units can be corrected to further obtain correct memory data. However, it will be appreciated by those skilled in the art that the P1 and P2 memory cells are illustrated in the embodiments of the present application, and the subsequent programming process is similar to the above-mentioned P1 and P2 processes, and will not be repeated here.
In one embodiment of the application, the predetermined value is reasonably set according to the error correction capability of the memory system, so that after the number of the first memory sub-units is smaller than the predetermined value, the verification is directly started from the memory unit in the next memory state, the time for re-verifying the memory unit is reduced, the programming time of the memory is further reduced, and the programming speed of the memory is improved to a certain extent. And only the number of the first storage sub-units is counted, so that a corresponding counting circuit is simplified.
Another aspect of the present application provides a memory 100, and fig. 6 is a schematic diagram of the memory system 100 according to an embodiment of the present application. As shown in fig. 6, the memory 100 may include a memory array 10, a voltage supply circuit 20, and a controller 30. Wherein the memory array 10 comprises a plurality of memory cells 201.
The voltage supply circuit 20 is coupled to the memory array 10 and is configured to apply a program pulse and a verifying voltage (including a first verifying voltage PVL and a second verifying voltage PV, hereinafter collectively referred to as verifying voltages) to a predetermined word line. The voltage supply circuit 20 may generate various voltages for performing operations of erasing, programming, reading and writing, verifying, etc. on the memory cell array 10 in response to a control signal from the controller 30.
The controller 30 is coupled to the memory array 10 and the voltage supply circuit 20 and is configured to control the voltage supply circuit 20 to apply programming pulses (including high programming pulses and low programming pulses, hereinafter collectively referred to as programming pulses) to memory cells of the plurality of memory cells that are in a programmed state. The controller 30 applies a programming pulse to the memory cells in the memory array 10 by sending programming signals, selecting the bit lines and word lines, to place the memory cells in different memory states. For example, during a programming operation, a programming pulse and a verify voltage may be applied to the word line where the memory cell of the selected programming state is located, and a program inhibit voltage may be applied to the bit line where the memory cell of the unselected programming state is located. During a read operation, a read voltage may be applied to the word line where the selected programmed memory cell is located, and for memory cells that are inhibited from reading, a read inhibit voltage is applied to the bit line where the memory cell is located.
In one embodiment of the present application, the controller 30 is configured to control the voltage supply circuit 20 to apply an initial program pulse to a memory cell in a programmed state among the plurality of memory cells; selecting a memory cell of a first memory state among memory cells to which an initial program pulse is applied, wherein a threshold voltage of the memory cell of the first memory state is the smallest among the memory cells of the plurality of memory states; determining a first storage subunit and a second storage subunit from the storage units in the first storage state, wherein the threshold voltage of the first storage subunit is smaller than the first verification voltage, and the threshold voltage of the second storage subunit is larger than the first verification voltage and smaller than the second verification voltage; in response to the number of first memory sub-cells being greater than a predetermined value, repeatedly applying a high programming pulse and a low programming pulse to the first memory sub-cells and the second memory sub-cells, respectively, until the number of first memory sub-cells is less than a predetermined value; and verifying from the memory cells of the second memory state, wherein the threshold voltage of the memory cells of the second memory state is only greater than the threshold voltage of the first memory state.
In one embodiment, the controller 30 is configured to: the number of first memory sub-cells is verified while applying a high programming pulse to the first memory sub-cells and a low programming pulse to the second memory sub-cells.
In one embodiment, the controller 30 is configured to: after the high program pulse and the low program pulse are repeatedly applied to the first memory sub-cell and the second memory sub-cell, respectively, using the voltage supply circuit 20, the threshold voltage of the first memory sub-cell and the threshold voltage of the second memory sub-cell are compared with the first verification voltage and the second verification voltage, respectively, to reconfirm the number of the first memory sub-cells.
In one embodiment, the memory cells of the first memory state further include a third memory subunit having a threshold voltage greater than the second verify voltage, the controller 30 being configured to: a program inhibit pulse is applied to the third memory subcell using voltage supply circuit 20.
In one embodiment, the controller 30 may be configured to: for a memory cell of the plurality of memory cells that is to be programmed to a highest memory state, in response to the number of first memory sub-cells being greater than a predetermined value, a programming pulse that is greater than the high programming pulse is applied to the memory cell, wherein a threshold voltage of the memory cell that is to be programmed to the highest memory state is greater than a threshold voltage of the memory cells in the remaining memory states.
In one embodiment, the predetermined value is determined based on a maximum value of error correction capability of the memory.
The present application also provides a memory system that may include a memory storing computer-executable instructions; and a processor for executing the computer-executable instructions stored by the memory to implement the memory programming method described above.
The purpose, technical scheme and beneficial effects of the invention are further described in detail in the detailed description. It is to be understood that the above description is only of specific embodiments of the present invention and is not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (13)
1. A method of programming a memory, the memory comprising a plurality of memory cells, the method comprising:
applying an initial programming pulse to a memory cell in a programmed state among the plurality of memory cells;
selecting a memory cell of a first memory state among the memory cells to which the initial programming pulse is applied, wherein a threshold voltage of the memory cell of the first memory state is the smallest among the memory cells of the plurality of memory states;
determining a first storage subunit and a second storage subunit from the storage units in the first storage state, wherein the threshold voltage of the first storage subunit is smaller than a first verification voltage, and the threshold voltage of the second storage subunit is larger than the first verification voltage and smaller than a second verification voltage;
in response to the number of first memory sub-cells being greater than a predetermined value, repeatedly applying a high programming pulse and a low programming pulse to the first memory sub-cells and the second memory sub-cells, respectively, until the number of first memory sub-cells is less than a predetermined value; and
verification begins with a memory cell of a second memory state, wherein a threshold voltage of the memory cell of the second memory state is only greater than a threshold voltage of the first memory state.
2. The method according to claim 1, wherein the method further comprises:
the number of the first memory sub-cells is confirmed while high and low program pulses are applied to the first and second memory sub-cells, respectively.
3. The method of claim 2, wherein after repeatedly applying the high programming pulse and the low programming pulse to the first memory subunit and the second memory subunit, respectively, the method further comprises:
the threshold voltage of the first memory sub-cell and the threshold voltage of the second memory sub-cell are compared with the first verification voltage and the second verification voltage, respectively, to reconfirm the number of the first memory sub-cells.
4. The method of any of claims 1-3, wherein the memory cell of the first memory state further comprises a third memory subunit having a threshold voltage greater than the second verify voltage, wherein the method further comprises:
a program inhibit pulse is applied to the third memory subunit.
5. The method according to claim 1, wherein the method further comprises:
for a memory cell of the plurality of memory cells to be programmed to a highest memory state, in response to the number of the first memory sub-cells being greater than a predetermined value, a programming pulse that is not less than the high programming pulse is applied to the memory cell, wherein a threshold voltage of the memory cell to be programmed to the highest memory state is greater than a threshold voltage of the memory cells in the remaining memory states.
6. The method of claim 1, wherein the predetermined value is determined based on a maximum value of error correction capability of the memory.
7. A memory, comprising:
a memory array including a plurality of memory cells;
a voltage supply circuit; and
a controller configured to:
controlling the voltage supply circuit to apply an initial programming pulse to a memory cell in a programmed state among the plurality of memory cells;
selecting a memory cell of a first memory state among the memory cells to which the initial programming pulse is applied, wherein a threshold voltage of the memory cell of the first memory state is the smallest among the memory cells of the plurality of memory states;
determining a first storage subunit and a second storage subunit from the storage units in the first storage state, wherein the threshold voltage of the first storage subunit is smaller than a first verification voltage, and the threshold voltage of the second storage subunit is larger than the first verification voltage and smaller than a second verification voltage;
in response to the number of first memory sub-cells being greater than a predetermined value, repeatedly applying a high programming pulse and a low programming pulse to the first memory sub-cells and the second memory sub-cells, respectively, until the number of first memory sub-cells is less than a predetermined value; and
verification begins with a memory cell of a second memory state, wherein a threshold voltage of the memory cell of the second memory state is only greater than a threshold voltage of the first memory state.
8. The memory system of claim 7, wherein the controller is configured to: the number of the first memory subcells is confirmed while a high programming pulse is applied to the first memory subcell and a low programming pulse is applied to the second memory subcell.
9. The memory system of claim 8, wherein the controller is configured to: after the high programming pulse and the low programming pulse are repeatedly applied to the first memory sub-cell and the second memory sub-cell, respectively, using the voltage supply circuit, the threshold voltage of the first memory sub-cell and the threshold voltage of the second memory sub-cell are compared with the first verification voltage and the second verification voltage, respectively, to reconfirm the number of the first memory sub-cells.
10. The memory system of any of claims 7-9, wherein the memory cell of the first memory state further comprises a third memory subunit having a threshold voltage greater than the second verify voltage, the controller configured to: a program inhibit pulse is applied to the third memory subunit with the voltage supply circuit.
11. The memory system of claim 7, wherein the controller is configured to: for a memory cell of the plurality of memory cells to be programmed to a highest memory state, in response to the number of the first memory sub-cells being greater than a predetermined value, a programming pulse that is not less than the high programming pulse is applied to the memory cell, wherein a threshold voltage of the memory cell to be programmed to the highest memory state is greater than a threshold voltage of the memory cells in the remaining memory states.
12. The memory system of claim 7, wherein the predetermined value is determined based on a maximum value of error correction capability of the memory.
13. A memory system, comprising:
a memory storing computer-executable instructions; and
a processor for executing computer-executable instructions stored by the memory to implement the method of any one of claims 1-6.
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