CN113705004B - Real-time system behavior level software simulation method suitable for DSP - Google Patents
Real-time system behavior level software simulation method suitable for DSP Download PDFInfo
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Abstract
A real-time system behavior-level software simulation method suitable for a DSP belongs to the technical field of computer simulation, solves the problems that simulation time is long for software development of a real-time system of the DSP by adopting simulation software and large-scale task software simulation is not available, takes a function behavior result as a simulation assessment basis, and completes the DSP function behavior-level simulation by adopting a high-level language; taking a dynamic array of memory and control quantity pointers as a tie, and adopting a processing node modeling instantiation and multithreading technology to complete the real-time system simulation of the DSP; taking the actually measured time consumption of the chip as a reference, and independently counting the transmission time and the calculation time to complete the performance evaluation of the task software; only the behavior result of task software is concerned, and the specific implementation process in the software is not concerned; only the approximate cost of transmission and calculation of each processing node is concerned, and the accurate time consumption of transmission and calculation of each processing node is not concerned; the method ensures that the function is consistent with the actual operation result after the function is operated on the simulation software, improves the simulation efficiency and reduces the simulation time consumption.
Description
Technical Field
The invention belongs to the technical field of computer simulation, and relates to a real-time system behavior level software simulation method suitable for a DSP.
Background
Along with the diversification and the complexity development of the functions of the real-time system, the difficulty of ensuring the real-time performance and the stability of the system realization is also continuously improved. The single-core chip is limited by various aspects such as processing capacity, power consumption, physical limit and the like, and the improvement of system performance creates a bottleneck. In order to meet the performance requirement of the real-time system, the digital signal processor has gradually developed from single core and single processor to multiprocessor or multi-core, the development workload of the real-time system is increasingly heavy, and the contradiction between the software quality and the development period is increasingly prominent.
Because of high design cost and long production period of real system hardware, development of system software by adopting simulation software in advance is a popular method at present. The programming development environment provided by the DSP manufacturer can realize the instruction level simulation of the software. The simulation accuracy is high, the states of all registers in the chip can be determined at any time, but the cost is that the simulation is too long, and the feasibility of large-scale task software simulation is basically not achieved.
To solve the time consuming problem of simulation, a number of solutions are proposed in the industry. Wherein MATLAB real-time simulation toolboxes (including SIMULINK, RTW, etc.) provided by Mathworks are most typical. A typical software development flow using MATLAB real-time simulation toolbox is: modeling under a SIMULINK environment, performing simulation analysis under MATLAB, and finally converting the SIMULINK model into C or Ada code by using RTW and converting the C or Ada code into target code by a target language compiler. During which a user can use the external mode of SIMULINK to monitor and adjust parameters in real time while the object code is running in the object environment. The development flow has the defects that task allocation needs to be completed under a target environment, target code efficiency is limited by code conversion performance of RTW, and target code debugging is limited by hardware range supported by Mathworks.
In the prior art, the Chinese patent application publication No. CN104866373A, with publication date of 2015, 8 and 26, discloses a cross-platform technology-based real-time operating system simulation method, which is based on the cross-platform technology, a micro sandbox is built in a cross-platform middleware, threads with real-time requirements are put into the sandbox during simulation operation, uniformly scheduled by a sandbox management program, and a scheduling algorithm is adjusted according to an operating system of target simulation, so that accurate simulation operation of real-time software on a host operating system is realized, and the execution efficiency is high, but the document does not solve the problems.
Disclosure of Invention
The invention aims at designing a real-time system behavior-level software simulation method suitable for a DSP, and solves the problems that in the prior art, simulation software is long in time consumption and large-scale task software simulation is not available for performing software development on a real-time system of the DSP by adopting simulation software.
The invention solves the technical problems through the following technical scheme:
a real-time system behavior level software simulation method suitable for DSP uses function behavior result as simulation check basis, and uses high-level language to complete DSP function behavior level simulation; taking a dynamic array of memory and control quantity pointers as a tie, and adopting a processing node modeling instantiation and multithreading technology to complete the real-time system simulation of the DSP; and taking the actually measured time consumption of the chip as a reference, and independently counting the transmission time and the calculation time to complete the performance evaluation of the task software.
The technical scheme only concerns the behavior result of task software and does not concern the specific implementation process in the software; only the approximate cost of transmission and calculation of each processing node is concerned, and the accurate time consumption of transmission and calculation of each processing node is not concerned; the method ensures that the function is consistent with the actual operation result after the function is operated on the simulation software, improves the simulation efficiency and reduces the simulation time consumption.
As a further improvement of the technical scheme of the invention, the function behavior result is taken as a simulation check basis, and the high-level language is adopted to complete the DSP function behavior level simulation, which comprises the following steps: constructing a corresponding simulation function by adopting a high-level language aiming at each DSP original function; the corresponding relation between the actual system storage space and the simulation platform storage space is ensured by utilizing address mapping; for functions causing memory image change by calculation transmission class, the consistency of the memory image after function operation is utilized to ensure the correctness of function simulation; and for functions of the control operation flow such as synchronous mutual exclusion, the consistency of the flow execution after the function operation is utilized to ensure the function simulation correctness.
As a further improvement of the technical scheme of the invention, the dynamic array of the memory and the control quantity pointer is used as a tie, and the modeling and instantiation of the processing nodes and the multithreading technology are adopted to complete the simulation of the DSP real-time system, specifically: the processing nodes are individually modeled and packaged into a class, the simulation function of the DSP function and the task program entry function are packaged in the processing node class as internal functions, dynamic allocation of corresponding memory and control quantity pointer dynamic arrays is completed according to the actual system scale in the process of instantiation of the processing node class, free expansion of the simulation scale is realized by utilizing the instantiation of the processing node class in the simulation, and synchronous and exclusive simulation among multiple processing nodes is realized by adopting control quantities such as mutex, semaphore and event; and the simulation of full parallel work of the multi-processing nodes is realized by adopting multithreading, and the processing nodes are in one-to-one correspondence with threads.
As a further improvement of the technical scheme of the invention, the task software performance evaluation is completed by adopting independent statistics of transmission time and calculation time based on the actual measurement time consumption of the chip, and the method specifically comprises the following steps: calculating operation time according to the actual measurement transmission and calculation time consumption of the processing chip and the conditions of transmission quantity or calculation quantity, and the like, packaging related calculation codes in all DSP functions of the processing nodes, adding two independent time counters for transmission and calculation in each processing node, and adjusting the counts of the two time counters according to the time calculation result by each operation function in the actual simulation operation, wherein a user evaluates the actual system performance and adjusts the task allocation strategy of each processing node in the simulation process.
As a further improvement of the technical scheme of the invention, the simulation function keeps consistent function names, consistent input or return parameters and consistent function functions with the original function.
As a further improvement of the technical scheme of the invention, the simulation platform comprises a time-consuming evaluation module, and the time-consuming evaluation module is used for evaluating the performance requirements of the software.
As a further improvement of the technical scheme of the invention, the processing node class not only comprises hardware mark variables such as a core number or a core number, a DSP number or a DSP number, a module number or a module number, a unit number or a unit number, and the like, but also comprises hardware resources such as a memory, a control quantity pointer dynamic array, and the like and control variables.
As a further improvement of the technical scheme of the invention, the task program entry function is generated by copying the source code of the actual task program written in a high-level language.
The invention has the advantages that:
the technical scheme of the invention only concerns the behavior result of the task software and does not concern the specific implementation process in the software; only the approximate cost of transmission and calculation of each processing node is concerned, and the accurate time consumption of transmission and calculation of each processing node is not concerned; the method ensures that the function is consistent with the actual operation result after the function is operated on the simulation software, improves the simulation efficiency and reduces the simulation time consumption.
Drawings
FIG. 1 is a schematic diagram of a DSP function behavior level simulation structure in an embodiment of the invention;
FIG. 2 is a schematic diagram of processing node modeling of an embodiment of the present invention;
FIG. 3 is a schematic illustration of an instantiation of a processing node in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram of a multi-processing node simulation performed using multi-threading techniques in accordance with an embodiment of the present invention;
FIG. 5 is a schematic diagram of time counting according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described in the following in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The technical scheme of the invention is further described below with reference to the attached drawings and specific embodiments:
a real-time system behavior-level software simulation method suitable for a DSP (digital signal processor ), which concretely comprises the following steps:
1. and taking the function behavior result as a simulation check basis, and adopting a high-level language to complete the DSP function behavior level simulation.
And (3) aiming at each DSP function, the development of the corresponding simulation version is completed by using standard C and other high-level languages. The operation simulation function keeps consistent function name, consistent input/return parameters and consistent function with the original function, and the task program written in the high-level language can be directly operated on the simulation platform after recompilation and linking are not changed. Meanwhile, in consideration of the requirement of subsequent software performance evaluation, a time-consuming evaluation module is added to the simulation platform end function, as shown in fig. 1.
As can be seen from fig. 1, for the case of address operation, no matter whether the address is embodied in the input/return parameter or the functional implementation, the present invention uses the address mapping link to ensure the corresponding relationship between the DSP memory space and the simulation platform memory space. In practical implementation, the address mapping link adopts a similar way at the simulation platform end
int GetNewAddr(int OldAddr)
Is realized in a functional form, and is similar to that at the DSP end
#define GetNewAddr(N)(N)
Is realized in the form of a macro definition. Because the macro definition is directly unfolded in the compiling stage, the address mapping link does not influence the efficiency of the actual DSP processing program after the compiling operation of the DSP end.
In function implementation, the invention utilizes the function behavior result to check the simulation function, and ensures the consistency of the function. According to different function types, the function behavior result also has two expression forms of memory mapping change and flow control. For functions causing memory image change by calculation transmission class, the consistency of the memory image after function operation is utilized to ensure the correctness of function simulation; and for functions of the control operation flow such as synchronous mutual exclusion, the consistency of the flow execution after the function operation is utilized to ensure the function simulation correctness. As can be seen from fig. 1, if the memory in the DSP end function implementation changes, the memory in the simulation platform end function implementation changes similarly; if the DSP end function implementation has synchronous, mutually exclusive and other operation flow control, the simulation platform end function implementation can obtain the same control effect.
2. And the dynamic array of the memory and the control quantity pointer is used as a tie, and a processing node modeling instantiation+multithreading technology is adopted to complete the real-time system simulation of the DSP.
With the object-oriented programming approach, a model is first built for the minimum components of the independently running programs in a real-time system, referred to as processing nodes, and the model is referred to as a class of processing nodes. A processing node class contains hardware flag variables such as core number/core number, DSP number/DSP number, module number/module number, unit number/unit number, and the like, and also contains hardware resources such as memory, control quantity pointer dynamic array, and the like, and control variables. The processing node class can simulate the behavior results of the real-time system under various operations through the internal variables. The emulated version of the DSP function is encapsulated within the class of processing nodes as an internal function, along with the task program entry. The entry function is generated from a copy of the actual tasking program source code written in a high-level language. In consideration of the fact that each processing node in the task system can execute different task programs, the invention adopts a method of integrating different task program source codes together after being added with the constraints of a core number, a DSP number, a module number, a unit number and the like, so that each processing node can apply the same processing node model. The method has high automation degree, is simple and convenient to use and does not influence the actual simulation result. The processing node modeling flow is shown in fig. 2.
The hardware unit at the upper left corner of the figure 2 consists of K+1 hardware modules from the numbers 0 to K; each hardware module is provided with a number of 0-n and n+1 DSPs, and the DSPs possibly have certain shared memory resources, and are represented by 'on-board memory' in the figure; each DSP has m+1 operation cores with numbers of 0-m, each operation core comprises an exclusive operation/communication component and an intra-core memory resource, and each core of the DSP possibly has a certain shared memory resource and is represented by 'on-chip memory' in the figure. The processing nodes formed after modeling are shown in the upper right corner of fig. 2, and the internal variables and the internal functions of the processing node class are divided into virtual frames such as hardware units, hardware modules and the like according to different mapping hardware, and are in one-to-one correspondence with the actual hardware platforms. All the software and hardware elements such as control quantity, storage, serial number and the like are modeled and mapped into internal variables in the processing node, and the operation communication part only models the behavior of the internal variables and is mapped into internal functions of the processing node. The number from the unit to each processing level of the operation core in the processing node class assigns a unique ID to each processing node instance, so that the software can be distributed and communicated among the processing nodes. The lower part of fig. 2 illustrates how task program software borne by each physical operation core is mapped to each processing node in the simulation model by ID through a task program entry when the hardware unit is actually running.
After the simulation software is run, the program first needs to automatically create a corresponding number of processing node class objects according to the task system scale and perform instantiation operation on the processing node class objects. In the invention, the internal variables such as the memory, the control quantity and the like of the processing node class package are all in the form of pointer dynamic arrays. The array scale reflects the resource and control scale of the task system and can be automatically adjusted according to the actual task system scale. After the simulation system is initialized to complete memory allocation and control quantity creation, the object of each processing node class can bind the corresponding memory and control quantity by using a pointer in the instantiation operation, so that access and control of all resources of the real-time system are realized. By adopting the method, the invention can realize the function simulation of any system scale as long as the simulation platform resources are sufficient. The processing node instantiation flow is shown in figure 3. For simplicity, the hardware unit illustrated in fig. 3 is composed of only one hardware module with the operation core as the minimum component of the independent running program, and the result of instantiating the node class object to be processed by one core in the module is shown. For on-board storage on the module, on-chip storage of n+1 DSPs and in-core storage of (m+1) ×n+1 operation cores, a storage space corresponding to one is opened up on the simulation platform during initialization, so as to realize mapping of storage between the hardware unit and the simulation platform (for example, the storage space on the board is mapped to address A, DSP of the storage space of the simulation platform, and the storage space is mapped to address B). These memory spaces are used by the processing node instance to read and write (e.g., memory pointers in the processing node instance are assigned address a, memory pointers in the DSP chip numbered 0 are assigned address B, etc.) in the form of pointers. Each instance contains pointers to all resources, and the pointers in multiple instances can point to the same mapping address. The topological relation enables a plurality of instances to realize sharing of the same storage space through pointer operation, and also realize access to all storage spaces through pointer operation. To meet the parallel processing requirements of multiple independently running program components, we use multi-threading techniques to accomplish multi-processing node simulation. The minimum component of each independently running program in the actual hardware unit corresponds to an instance of a processing node in the simulation platform. When the simulation software is executed, each processing node instance in the simulation platform initiates a thread, runs a copy of an actual task program, and simulates a real and independent running minimum program component full parallel working state. The control quantity pointer array in the example is utilized among threads, and the control quantity such as mutex, semaphore, event and the like is adopted to realize the simulation of synchronization and mutex among multiple independent operation minimum program components. Multi-independent run min program component simulation is accomplished using multi-threading techniques as shown in fig. 4. The simulation platform in the figure simulates independently running minimum program components A and B (identified as processing nodes A and B in the figure) in an actual hardware unit using thread 1 and thread 2. As can be seen from FIG. 4, even if the simulation platform virtually realizes multithreading parallelism by adopting a time slice rotation method, the effects of operations such as synchronization and mutual exclusion among threads on the running flow of the threads are consistent with the actual running effects of the two processing nodes.
3. And taking the actual measurement time of the chip as a reference, and independently counting the transmission time and the calculation time to complete the software performance evaluation.
And packaging the actually measured transmission time and calculation time in a simulation platform version of the DSP function, wherein each task node class object comprises two time counters of the transmission time and the calculation time. In actual simulation operation, the DSP function at the simulation platform end selects the actual performance of the corresponding chip according to different transmission or operation conditions, calculates transmission or calculation time according to the transmission data quantity or operation quantity, and controls and adjusts the numerical values of the two time counters according to the transmission or calculation time. During a system task simulation, a user may evaluate actual software performance based on the two time counts. The time counting operation is shown in fig. 5. Two typical conditions of DMA access and open root are given in the figure. The former consumes mainly transmission time, and the latter consumes mainly calculation time. For data transmission, the transmission performance and the memory location relation involved in transmission are extremely large. In order to improve simulation timing precision, the simulation platform end establishes a DMA transmission time table according to the actually measured DMA transmission performance. The actual transmission bandwidth can be obtained by looking up the memory location involved in the transmission, that is, the unit time consumed txx (xx represents the combination of 00/01/02 etc. in the table) shown in the figure. If the current transmission data quantity is N, the actual time consumption of the current transmission is N x tx; the estimate of the computation time is similar to the transmission time. In order to improve simulation timing precision, the simulation platform end establishes a root opening number calculation time table according to the root opening number performance of different actually measured storage spaces. The actual computing performance, i.e. the unit time Txx (xx stands for 00/01/02 etc. combinations in the table) shown in the figure can be verified by computing the memory locations involved. If the number of the calculation elements is N, the actual time consumption is N×Txx. The transmission or calculation time increment obtained according to the algorithm is added with the count value of the corresponding time counter and then written back to the corresponding time counter for system performance evaluation.
Aiming at the requirements of the real-time system behavior-level simulation based on the DSP, the invention develops the behavior-level simulation which has high performance, expandability and certain performance evaluation capability, reduces the software development cost and improves the software development quality. The behavior simulates a 'heavy result, light process'; performance evaluation "major, light accuracy".
The invention takes the function behavior result as the simulation check basis, and adopts high-level language to complete the DSP function behavior level simulation. And constructing a corresponding simulation version by adopting a high-level language aiming at each DSP function. And ensuring the corresponding relation between the actual system storage space and the simulation platform storage space by using address mapping. The DSP end adopts a macro definition mode to realize address mapping, the actual address is unchanged after compiling, the software code is unchanged, and the program efficiency is unchanged; the simulation platform end adopts a function mode to realize address mapping, and the compiled actual address can be a system address or a virtual address such as a hard disk file position. In the aspect of checking basis, for functions of which the calculation transmission class causes the memory image to change, the consistency of the memory image after the functions are operated is utilized to ensure the correctness of function simulation; for functions of the control operation flow such as synchronous mutual exclusion, the consistency of the flow execution after the function operation is utilized to ensure the function simulation correctness.
The invention takes a dynamic array of memory and control quantity pointers as a tie, and adopts a processing node modeling instantiation+multi-thread technology to complete multi-processing node simulation. The processing nodes are defined as the smallest components of the independently running programs in the real-time system. For a single-core DSP, the processing node is the DSP; for a multi-core DSP, the processing nodes may be either DSPs or arithmetic cores. Processing nodes individually model and package into a class. The simulated version of the DSP function and the task program entry are encapsulated as internal functions within the class of processing nodes. And in the instantiation process of the processing node class, the dynamic adjustment of the dynamic array of the corresponding memory and the control quantity pointer is completed according to the actual system scale. The free expansion of the simulation scale is realized by using the instantiation of the processing node class in the simulation. Adopting control amounts such as mutex, semaphore, event and the like to realize the simulation of synchronization and mutex among the multiprocessing nodes; and the simulation of full parallel work of the multi-processing nodes is realized by adopting multithreading, and the processing nodes are in one-to-one correspondence with threads.
The invention takes the actual measurement time consumption of the chip as a benchmark, and adopts independent statistics of the transmission time and the calculation time to complete the software performance evaluation. Real-time systems generally employ a method of parallel transmission and computation to improve real-time performance. In the invention, two independent time counters for transmission and calculation are added in each processing node class. And controlling the numerical values of the two time counters according to different transmission or operation conditions in a cross-platform basic function library according to the actual performance of the chip. In a system task simulation process, a user can estimate actual system performance based on the actual system performance.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (5)
1. A real-time system behavior level software simulation method suitable for a DSP is characterized in that a function behavior result is taken as a simulation check basis, and a high-level language is adopted to complete the DSP function behavior level simulation; the method comprises the following steps: constructing a corresponding simulation function by adopting a high-level language aiming at each DSP original function; the corresponding relation between the actual system storage space and the simulation platform storage space is ensured by utilizing address mapping; for functions causing memory image change by calculation transmission class, the consistency of the memory image after function operation is utilized to ensure the correctness of function simulation; for the function of the synchronous mutual exclusion control operation flow, the consistency of the flow execution after the function operation is utilized to ensure the function simulation correctness;
taking a dynamic array of memory and control quantity pointers as a tie, and adopting a processing node modeling instantiation and multithreading technology to complete the real-time system simulation of the DSP; the method comprises the following steps: the processing nodes are individually modeled and packaged into a class, the simulation function of the DSP function and the task program entry function are packaged in the processing node class as internal functions, dynamic allocation of corresponding memory and control quantity pointer dynamic arrays is completed according to the actual system scale in the process of instantiation of the processing node class, free expansion of the simulation scale is realized by utilizing the instantiation of the processing node class in the simulation, and synchronous and mutually exclusive simulation among multiple processing nodes is realized by adopting mutex, semaphore and event control quantity; the simulation of the full parallel work of the multi-processing nodes is realized by adopting multithreading, and the processing nodes are in one-to-one correspondence with threads;
taking the actually measured time consumption of the chip as a reference, and independently counting the transmission time and the calculation time to complete the performance evaluation of the task software; the method comprises the following steps: calculating operation time according to the actual measurement transmission and calculation time consumption of the processing chip and the transmission quantity or calculation quantity conditions, packaging related calculation codes in all DSP functions of the processing nodes, adding two independent time counters for transmission and calculation in each processing node, and adjusting the counts of the two time counters according to the time calculation results by each operation function in the actual simulation operation, wherein a user evaluates the actual system performance and adjusts the task allocation strategy of each processing node in the simulation process.
2. The method for simulating real-time system behavior level software suitable for DSP according to claim 1, wherein said simulation function keeps consistent function name, consistent input or return parameters and consistent function with the original function.
3. The method for simulating real-time system behavior-level software for a DSP according to claim 2, wherein the simulation platform comprises a time-consuming evaluation module for evaluating performance requirements of the software.
4. The method of claim 1, wherein the processing node class includes a core number or number, a DSP number or number, a module number or number, a unit number or number of units, and hardware flag variables, and also includes a memory, a control pointer dynamic array of hardware resources, and control variables.
5. A method of real time system behavior level software simulation for a DSP according to claim 4 wherein the task program entry function is generated from a copy of the actual task program source code written in a high level language.
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