CN113705004A - Real-time system behavior level software simulation method suitable for DSP - Google Patents
Real-time system behavior level software simulation method suitable for DSP Download PDFInfo
- Publication number
- CN113705004A CN113705004A CN202111003047.XA CN202111003047A CN113705004A CN 113705004 A CN113705004 A CN 113705004A CN 202111003047 A CN202111003047 A CN 202111003047A CN 113705004 A CN113705004 A CN 113705004A
- Authority
- CN
- China
- Prior art keywords
- simulation
- function
- time
- dsp
- software
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
A real-time system behavior level software simulation method suitable for DSP belongs to the technical field of computer simulation, solves the problems that simulation of software development on a real-time system of DSP by adopting simulation software is long in time consumption and does not have large-scale task software simulation, and finishes DSP function behavior level simulation by adopting a high-level language by taking a function behavior result as a simulation assessment basis; taking a memory and a control quantity pointer dynamic array as links, and completing DSP real-time system simulation by adopting processing node modeling instantiation and a multithreading technology; taking the actual measurement time consumption of the chip as a reference, and independently counting the transmission time and the calculation time to complete the performance evaluation of the task software; only the behavior result of the task software is concerned, and the specific implementation process in the software is not concerned; only the rough overhead of transmission and calculation of each processing node is concerned, and the accurate time consumption of transmission and calculation of each processing node is not concerned; the method and the device not only ensure that the function is consistent with the actual operation result after the function is operated on the simulation software, but also improve the simulation efficiency and reduce the simulation time consumption.
Description
Technical Field
The invention belongs to the technical field of computer simulation, and relates to a real-time system behavior level software simulation method suitable for a DSP.
Background
Along with the diversification and complex development of real-time system functions, the difficulty of guaranteeing the real-time performance and stability of system implementation is also continuously improved. The single-core chip is restricted by multiple aspects such as processing capacity, power consumption, physical limit and the like, and the bottleneck is generated when the system performance is improved. In order to meet the performance requirements of real-time systems, digital signal processors have been developed from single cores and single processors to multi-processors or multi-core, the development workload of real-time system software is increasingly heavy, and the contradiction between software quality and development period is increasingly prominent.
Because the hardware design cost of the real system is high and the production period is long, the method of adopting simulation software to develop system software in advance is a popular way at present. The programming development environment provided by the DSP manufacturer can realize instruction level simulation of software. The simulation has high accuracy, can determine the state of each register in the chip at any time, but has the cost of overlong simulation time consumption and basically does not have the feasibility of task software simulation with larger scale.
To solve the time consuming problem of simulation, various solutions are presented in the industry. With the MATLAB real-time simulation toolkit (including SIMULINK, RTW, etc.) offered by Mathworks corporation being the most typical. The typical software development process adopting the MATLAB real-time simulation toolbox comprises the following steps: firstly, modeling is carried out in a SIMULINK environment, then simulation analysis is carried out in MATLAB, and finally, the SIMULINK model is converted into C or Ada codes by utilizing RTW and is converted into target codes through a target language compiler. During which the user may use the external mode of SIMULINK to monitor and adjust parameters in real time while the target code is running in the target environment. The disadvantages of this development process are that task allocation needs to be completed in a target environment, target code efficiency is limited by code conversion performance of RTW, and target code debugging is limited by the hardware range supported by Mathworks.
In the prior art, chinese patent application publication "real-time operating system simulation method based on cross-platform technology" published on 26 th of 8 th of 2015 and with publication number CN104866373A discloses that based on cross-platform technology, a micro sandbox is established in cross-platform middleware, when in simulation operation, a thread with real-time requirement is placed in the sandbox, and is uniformly scheduled by a sandbox management program, and a scheduling algorithm is adjusted according to an operating system of target simulation, so as to realize accurate simulation operation of real-time software on a host operating system, and the execution efficiency is high, but the publication does not solve the above problems.
Disclosure of Invention
The invention aims to design a real-time system behavior level software simulation method suitable for a DSP (digital signal processor), and solves the problems that the simulation in the prior art for carrying out software development on a real-time system of the DSP by adopting simulation software is long in time consumption and does not have large-scale task software simulation.
The invention solves the technical problems through the following technical scheme:
a real-time system behavior level software simulation method suitable for DSP takes a function behavior result as a simulation assessment basis, and adopts a high-level language to complete DSP function behavior level simulation; taking a memory and a control quantity pointer dynamic array as links, and completing DSP real-time system simulation by adopting processing node modeling instantiation and a multithreading technology; and (3) independently counting the transmission time and the calculation time by taking the actual measurement time of the chip as a reference to complete the performance evaluation of the task software.
According to the technical scheme, only the behavior result of the task software is concerned, and the specific implementation process inside the software is not concerned; only the rough overhead of transmission and calculation of each processing node is concerned, and the accurate time consumption of transmission and calculation of each processing node is not concerned; the method and the device not only ensure that the function is consistent with the actual operation result after the function is operated on the simulation software, but also improve the simulation efficiency and reduce the simulation time consumption.
As a further improvement of the technical scheme of the invention, the DSP function behavior level simulation is completed by adopting a high-level language by taking the function behavior result as a simulation assessment basis, and the method specifically comprises the following steps: constructing a corresponding simulation function by adopting a high-level language aiming at each DSP primitive function; ensuring the corresponding relation between the actual system storage space and the simulation platform storage space by using address mapping; for the function which calculates the memory mapping change caused by the transmission class, the function simulation correctness is ensured by using the consistency of the memory mapping after the function is operated; for the functions of controlling the operation flow such as synchronous mutual exclusion and the like, the simulation correctness of the functions is ensured by using the consistency of the flow execution after the functions are operated.
As a further improvement of the technical scheme of the invention, the method adopts a memory and a control quantity pointer dynamic array as links, adopts processing node modeling instantiation and a multithreading technology to complete DSP real-time system simulation, and specifically comprises the following steps: the processing nodes are independently modeled and packaged into a class, a simulation function of a DSP function and a task program entry function are packaged in the processing node class as internal functions, dynamic allocation of dynamic arrays of corresponding memories and control quantity pointers is completed according to the actual system scale in the instantiation process of the processing node class, free expansion of the simulation scale is realized by using instantiation of the processing node class in simulation, and synchronous and mutual-exclusive simulation among the multiple processing nodes is realized by adopting control quantities such as mutexes, semaphores and events; and multi-thread is adopted to realize the simulation of the full parallel work of the multi-processing nodes, and the processing nodes correspond to the threads one to one.
As a further improvement of the technical scheme of the invention, the task software performance evaluation is completed by taking the actual measurement time consumption of the chip as a reference and adopting independent statistics of transmission time and calculation time, and the method specifically comprises the following steps: calculating operation time according to conditions such as transmission quantity or operation quantity and the like according to actually measured transmission and calculation time consumption of a processing chip, packaging related calculation codes in all DSP functions of processing nodes, adding two independent time counters for transmission and calculation in each processing node, adjusting the counting of the two time counters according to time calculation results by each operation function during actual simulation operation, and accordingly evaluating the performance of an actual system and adjusting task allocation strategies of each processing node by a user in the simulation process.
As a further improvement of the technical scheme of the invention, the simulation function and the original function keep consistent function name, input or return parameters and function functions.
As a further improvement of the technical scheme of the invention, the simulation platform comprises a time-consuming evaluation module, and the time-consuming evaluation module is used for evaluating the performance requirement of the software.
As a further improvement of the technical solution of the present invention, the processing node type includes hardware flag variables such as a core number or a core number, a DSP number or a DSP number, a module number or a module number, a unit number or a unit number, and also includes hardware resources and control variables such as a memory, a controlled variable pointer dynamic array, and the like.
As a further improvement of the technical scheme of the invention, the task program entry function is generated by copying the source code of the actual task program written by adopting a high-level language.
The invention has the advantages that:
the technical scheme of the invention only concerns the behavior result of the task software and does not concern the specific implementation process inside the software; only the rough overhead of transmission and calculation of each processing node is concerned, and the accurate time consumption of transmission and calculation of each processing node is not concerned; the method and the device not only ensure that the function is consistent with the actual operation result after the function is operated on the simulation software, but also improve the simulation efficiency and reduce the simulation time consumption.
Drawings
FIG. 1 is a diagram illustrating a DSP function behavior level simulation structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of processing node modeling according to an embodiment of the present invention;
FIG. 3 is a schematic illustration of an instantiation of a processing node according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a multi-processing node simulation implemented by multithreading according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of time counting according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The technical scheme of the invention is further described by combining the drawings and the specific embodiments in the specification:
a real-time system behavior level software simulation method suitable for a DSP (Digital Signal Processor) specifically comprises the following steps:
1. and (4) taking the function behavior result as a simulation assessment basis, and finishing DSP function behavior level simulation by adopting a high-level language.
And aiming at each DSP function, the development of a corresponding simulation version is completed by using high-level languages such as standard C and the like. The operation simulation function and the original function keep the same function name, input/return parameters and function, and the task program written by the original high-level language can be directly operated on the simulation platform without changing, recompiling and linking. Meanwhile, in consideration of the requirement of subsequent software performance evaluation, a time-consuming evaluation module is added to the simulation platform end function, as shown in fig. 1.
As can be seen from fig. 1, for the occasion related to address operation, no matter whether the address is embodied in the input/return parameter or the address is embodied in the function implementation, the present invention utilizes the address mapping link to ensure the corresponding relationship between the DSP memory space and the emulation platform memory space. In practical implementation, address mapping links are similar at the simulation platform end
int GetNewAddr(int OldAddr)
Is implemented in the form of functions, and the like is adopted at the DSP end
#define GetNewAddr(N)(N)
Is implemented in a macro definition form. Because the macro definition is directly expanded in the compiling stage, the address mapping link does not influence the efficiency of the actual DSP processing program after the DSP end is compiled and run.
In terms of function realization, the simulation function is assessed by using the function behavior result, and the function consistency is ensured. According to different function types, the function behavior result also has two expression forms of memory mapping change and flow control. For the function which calculates the memory mapping change caused by the transmission class, the function simulation correctness is ensured by using the consistency of the memory mapping after the function is operated; for the functions of controlling the operation flow such as synchronous mutual exclusion and the like, the simulation correctness of the functions is ensured by using the consistency of the flow execution after the functions are operated. As can be seen from fig. 1, if the memory changes during the implementation of the DSP end function, the memory changes during the implementation of the simulation platform end function; if the operation flow control such as synchronization, mutual exclusion and the like occurs in the realization of the DSP end function, the realization of the simulation platform end function can obtain the same control effect.
2. And (3) taking the memory and the control quantity pointer dynamic array as links, and completing the simulation of the DSP real-time system by adopting a processing node modeling instantiation and multithreading technology.
With object-oriented programming, the smallest component of an independently running program in a real-time system, called a processing node, is modeled first, and the model is called a processing node class. One processing node class not only contains hardware flag variables such as core numbers/core numbers, DSP numbers/DSP numbers, module numbers/module numbers, unit numbers/unit numbers, but also contains hardware resources such as internal memories, control quantity pointer dynamic arrays and the like and control variables. The processing node class can simulate the behavior result of the real-time system under various operations through the internal variables. The simulation version of the DSP function is packaged in the processing node class as an internal function, and a task program inlet is also packaged together. The entry function is generated from a copy of the actual task program source code written in a high level language. Considering that each processing node in the actual task system may execute different task programs, the invention adopts a method of integrating different task program source codes with the constraints of core number, DSP number, module number, unit number and the like, so that each processing node can apply the same processing node type model. The method has high automation degree, is simple and convenient to use and does not influence the actual simulation result. The process node modeling flow is shown in fig. 2.
The hardware unit at the upper left corner of the figure 2 consists of K +1 hardware modules with the numbers of 0-K; each hardware module is provided with n +1 DSPs with numbers of 0-n, and the DSPs may have certain shared storage resources, which are represented by 'on-board storage' in the figure; each DSP has m +1 operation cores with numbers of 0-m, each operation core comprises an independent operation/communication component and an in-core storage resource, and each core in the DSP can have a certain shared storage resource, which is represented by 'on-chip storage' in the figure. The processing nodes formed after modeling are shown in the upper right corner of fig. 2, and the internal variables and the internal functions of the processing node classes are divided into virtual frames such as hardware units and hardware modules according to different mapping hardware, and are in one-to-one correspondence with the actual hardware platforms. All software and hardware elements such as control quantity, storage, serial numbers and the like are modeled and mapped into internal variables in the processing nodes, and the operation communication part only models the behaviors of the operation communication part and maps the behaviors into internal functions of the processing nodes. The serial numbers of the processing levels from the units to the operation cores in the processing node classes endow a unique ID to each processing node instance, so that software can be distributed and communicated among the processing nodes. The lower half of fig. 2 illustrates how the task program software assumed by each physical computing core is mapped to each processing node in the simulation model to run according to the ID through the task program entry when the hardware unit actually runs.
After the simulation software is run, the program first needs to automatically create a corresponding number of processing node class objects according to the scale of the task system and perform instantiation operation on the processing node class objects. In the invention, internal variables such as internal memories, control variables and the like of processing node class packaging all adopt a pointer dynamic array form. The array scale reflects the size of the task system resource and the control scale, and can be automatically adjusted according to the actual task system scale. After the simulation system initializes and finishes memory allocation and control quantity creation, the object of each processing node class can bind the corresponding memory and control quantity by using the pointer in the instantiation operation, and access and control of all resources of the real-time system are realized. By adopting the method, the invention can realize the function simulation of any system scale as long as the simulation platform resources are sufficient. The process node instantiation flow is shown in fig. 3. For the sake of simplicity, the hardware unit illustrated in fig. 3 is only composed of a hardware module with an arithmetic core as the minimum component of an independent operating program, and shows the instantiation result of the node class object to be processed by one core in the hardware module. For on-board storage on the module, on-chip storage of n +1 DSPs, and in-core storage of (m +1) × (n +1) arithmetic cores, a one-to-one corresponding storage space has been opened up on the simulation platform at initialization, and mapping of storage between the hardware unit and the simulation platform is realized (for example, storage space on the board is mapped to address A, DSP0 on-chip storage space of the simulation platform storage space and is mapped to address B, etc.). These memory spaces are read and written by the processing node instance in the form of pointers (for example, in the processing node instance in the figure, the on-board memory pointer is assigned as address a, the on-chip memory pointer of DSP with number 0 is assigned as address B, etc.). Each instance contains pointers to all resources, and the pointers in multiple instances can point to the same mapping address. The topological relation enables a plurality of instances to realize the sharing of the same storage space through pointer operation, and also realize the access to all the storage spaces through the pointer operation. In order to meet the parallel processing requirement of a plurality of independent operating program components, a multithreading technology is utilized to complete multiprocessing node simulation. The smallest component of each independently running program in the actual hardware unit corresponds to one processing node instance in the simulation platform. When the simulation software is executed, each processing node instance in the simulation platform initiates a thread, runs a copy of an actual task program, and simulates the full parallel working state of the minimum program components which are actually and independently run. The synchronous and mutual exclusion simulation among multiple independent operation minimum program components is realized by utilizing a control quantity pointer array in an example and adopting control quantities such as mutual exclusion elements, semaphores, events and the like among threads. The simulation of multiple independently running minimal program components is accomplished using multithreading as shown in figure 4. The simulation platform in the figure uses thread 1 and thread 2 to simulate independently running minimal program components a and B (identified as processing nodes a and B in the figure) in an actual hardware unit. As can be seen from fig. 4, even if the simulation platform virtually realizes the multithreading parallelism by adopting the time slice rotation method, the effect of the operation such as the synchronization and the mutual exclusion among the threads on the thread running process is still consistent with the actual running effect of the two processing nodes.
3. And (3) taking the actual measurement time consumption of the chip as a reference, and independently counting the transmission time and the calculation time to complete software performance evaluation.
And encapsulating the transmission time and the calculation time obtained by actual measurement in a simulation platform version of the DSP function, wherein each task node object comprises two time counters of the transmission time and the calculation time. In the actual simulation operation, the DSP function at the simulation platform end selects the actual performance of the corresponding chip according to different conditions of transmission or operation, calculates the transmission or calculation time according to the size of the transmission data volume or the operation volume, and controls and adjusts the numerical values of the two time counters according to the transmission or calculation time. During a system task simulation, the user can evaluate the actual software performance according to the two time counting values. The time counting operation is shown in fig. 5. Two typical conditions of DMA access and open root are given in the figure. The former mainly consumes transmission time, and the latter mainly consumes calculation time. For data transmission, the relation between the transmission performance and the memory location involved in the transmission is extremely large. In order to improve the simulation timing precision, the simulation platform end establishes a DMA transmission time table according to the actually measured DMA transmission performance. The actual transmission bandwidth can be obtained by looking up a table through the transmission related memory locations, namely the unit time consumption txx shown in the figure (xx represents a combination of 00\01\02 and the like in the table). If the data volume of the transmission is N, the actual time consumption of the transmission is N x txx; the estimate of the computation time is similar to the transmission time. In order to improve the simulation timing precision, the simulation platform end establishes a root number calculation time table according to the actually measured root number performance of different storage spaces. The actual computation performance, namely unit time consumption Txx (xx represents a combination of 00\01\02 and the like in a table) shown in the figure can be inversely checked through computing the related memory positions. If the number of the elements calculated at this time is N, the actual consumed time is N × Txx. And adding the transmission or calculation time increment obtained according to the algorithm and the count value of the corresponding time counter, and writing back the corresponding time counter for system performance evaluation.
Aiming at the real-time system behavior level simulation requirement based on the DSP, the invention develops a behavior level simulation which has high performance, is extensible and has certain performance evaluation capability, reduces the software development cost and improves the software development quality. Its behavior simulates a 'heavy result, light process'; the performance evaluation is 'heavy, rough, light precision'.
The invention takes the function behavior result as the simulation assessment basis and adopts the high-level language to complete the DSP function behavior level simulation. And constructing a corresponding simulation version by adopting a high-level language aiming at each DSP function. And ensuring the corresponding relation between the actual system storage space and the simulation platform storage space by using address mapping. The DSP end adopts a macro definition mode to realize address mapping, the actual address is unchanged after compiling, the software code is unchanged, and the program efficiency is unchanged; the simulation platform end adopts a function mode to realize address mapping, and the actual address after compiling can be a system address or a virtual address such as a hard disk file position. In the aspect of assessment basis, for the function of which the memory image changes caused by the calculation and transmission class, the function simulation correctness is ensured by using the consistency of the memory image after the function runs; for the functions for controlling the operation flow such as synchronous mutual exclusion and the like, the simulation correctness of the functions is ensured by using the consistency of the flow execution after the functions are operated.
The invention takes the dynamic arrays of the memory and the control quantity pointer as links, and adopts the modeling instantiation of the processing node and the multithreading technology to complete the simulation of the multiprocessing node. A processing node is defined as the smallest component of a program that runs independently in a real-time system. For a single-core DSP, the processing nodes are the DSPs; for a multi-core DSP, the processing nodes may be DSPs or arithmetic cores. The processing nodes are individually modeled and encapsulated as a class. The emulation version of the DSP function and the task program entry are encapsulated within the class of processing nodes as internal functions. And completing dynamic adjustment of the corresponding memory and control quantity pointer dynamic arrays according to the actual system scale in the instantiation process of the processing node class. And in the simulation, the instantiation of the processing node class is utilized to realize the free expansion of the simulation scale. Adopting control quantities such as mutex elements, semaphores and events to realize the synchronization and mutex simulation among the multiprocessing nodes; and multi-thread is adopted to realize the simulation of the full parallel work of the multi-processing nodes, and the processing nodes correspond to the threads one to one.
The invention takes the actual measurement time consumption of the chip as a reference, and completes the software performance evaluation by adopting independent statistics of transmission time and calculation time. Real-time systems generally employ a parallel transmission and computation method to improve real-time performance. In the invention, two independent time counters for transmission and calculation are added in each processing node class. And controlling the numerical values of the two time counters in a cross-platform basic function library according to the actual performance of the chip and different transmission or operation conditions. During a system task simulation, the user can estimate the actual system performance based on the estimated system performance.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (8)
1. A real-time system behavior level software simulation method suitable for DSP is characterized in that a function behavior result is taken as a simulation assessment basis, and DSP function behavior level simulation is completed by adopting a high-level language; taking a memory and a control quantity pointer dynamic array as links, and completing DSP real-time system simulation by adopting processing node modeling instantiation and a multithreading technology; and (3) independently counting the transmission time and the calculation time by taking the actual measurement time of the chip as a reference to complete the performance evaluation of the task software.
2. The method for simulating the real-time system behavior level software suitable for the DSP according to claim 1, wherein the function behavior result is used as a simulation assessment basis, and a high-level language is used for completing the DSP function behavior level simulation, specifically: constructing a corresponding simulation function by adopting a high-level language aiming at each DSP primitive function; ensuring the corresponding relation between the actual system storage space and the simulation platform storage space by using address mapping; for the function which calculates the memory mapping change caused by the transmission class, the function simulation correctness is ensured by using the consistency of the memory mapping after the function is operated; for the functions of controlling the operation flow such as synchronous mutual exclusion and the like, the simulation correctness of the functions is ensured by using the consistency of the flow execution after the functions are operated.
3. The method for simulating the real-time system behavior level software suitable for the DSP according to claim 1, wherein the DSP real-time system simulation is completed by using a memory and a control quantity pointer dynamic array as links and adopting a processing node modeling instantiation and a multithreading technology, and specifically comprises the following steps: the processing nodes are independently modeled and packaged into a class, a simulation function of a DSP function and a task program entry function are packaged in the processing node class as internal functions, dynamic allocation of dynamic arrays of corresponding memories and control quantity pointers is completed according to the actual system scale in the instantiation process of the processing node class, free expansion of the simulation scale is realized by using instantiation of the processing node class in simulation, and synchronous and mutual-exclusive simulation among the multiple processing nodes is realized by adopting control quantities such as mutexes, semaphores and events; and multi-thread is adopted to realize the simulation of the full parallel work of the multi-processing nodes, and the processing nodes correspond to the threads one to one.
4. The method for simulating the real-time system behavior level software suitable for the DSP according to claim 1, wherein the task software performance evaluation is completed by independently counting transmission time and calculation time based on actual measurement time of a chip, and specifically comprises the following steps: calculating operation time according to conditions such as transmission quantity or operation quantity and the like according to actually measured transmission and calculation time consumption of a processing chip, packaging related calculation codes in all DSP functions of processing nodes, adding two independent time counters for transmission and calculation in each processing node, adjusting the counting of the two time counters according to time calculation results by each operation function during actual simulation operation, and accordingly evaluating the performance of an actual system and adjusting task allocation strategies of each processing node by a user in the simulation process.
5. The method according to claim 2, wherein the simulation function and the original function have the same function name, the same input or return parameter and the same function.
6. The method according to claim 5, wherein the simulation platform comprises a time-consuming evaluation module for evaluating performance requirements of the software.
7. The method as claimed in claim 3, wherein the processing node class includes hardware flag variables such as core number or core number, DSP number or DSP number, module number or module number, unit number or unit number, and hardware resources and control variables such as memory and control quantity pointer dynamic array.
8. The method of claim 7, wherein the task program entry function is generated from a copy of the source code of the actual task program written in a high level language.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111003047.XA CN113705004B (en) | 2021-08-30 | 2021-08-30 | Real-time system behavior level software simulation method suitable for DSP |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111003047.XA CN113705004B (en) | 2021-08-30 | 2021-08-30 | Real-time system behavior level software simulation method suitable for DSP |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113705004A true CN113705004A (en) | 2021-11-26 |
| CN113705004B CN113705004B (en) | 2023-06-13 |
Family
ID=78656671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111003047.XA Active CN113705004B (en) | 2021-08-30 | 2021-08-30 | Real-time system behavior level software simulation method suitable for DSP |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113705004B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040233237A1 (en) * | 2003-01-24 | 2004-11-25 | Andreas Randow | Development environment for DSP |
| CN101281507A (en) * | 2008-05-07 | 2008-10-08 | 李明荣 | USB interface type DSP real-time simulation development system |
| CN102750143A (en) * | 2012-05-31 | 2012-10-24 | 武汉邮电科学研究院 | Digital signal processing (DSP) developing method based on matrix laboratory (MATLAB) component object model (COM) component calling |
| CN204270144U (en) * | 2014-12-22 | 2015-04-15 | 国家电网公司 | A kind of hydrogovernor simulation testing device based on dsp system |
| CN104750603A (en) * | 2013-12-30 | 2015-07-01 | 联芯科技有限公司 | Multi-core DSP (Digital Signal Processor) software emulator and physical layer software testing method thereof |
| CN110196720A (en) * | 2019-05-29 | 2019-09-03 | 北京灵思创奇科技有限公司 | A kind of Simulink generates the optimization method of dynamic link library |
| CN110674590A (en) * | 2019-10-07 | 2020-01-10 | 中国人民解放军陆军装甲兵学院 | Programming method of real-time simulation program of aircraft based on simulation software Simulink real-time extended RTX |
| CN111460635A (en) * | 2020-03-19 | 2020-07-28 | 南京南瑞继保电气有限公司 | Simulation test method, electronic device and storage medium |
-
2021
- 2021-08-30 CN CN202111003047.XA patent/CN113705004B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040233237A1 (en) * | 2003-01-24 | 2004-11-25 | Andreas Randow | Development environment for DSP |
| CN101281507A (en) * | 2008-05-07 | 2008-10-08 | 李明荣 | USB interface type DSP real-time simulation development system |
| CN102750143A (en) * | 2012-05-31 | 2012-10-24 | 武汉邮电科学研究院 | Digital signal processing (DSP) developing method based on matrix laboratory (MATLAB) component object model (COM) component calling |
| CN104750603A (en) * | 2013-12-30 | 2015-07-01 | 联芯科技有限公司 | Multi-core DSP (Digital Signal Processor) software emulator and physical layer software testing method thereof |
| CN204270144U (en) * | 2014-12-22 | 2015-04-15 | 国家电网公司 | A kind of hydrogovernor simulation testing device based on dsp system |
| CN110196720A (en) * | 2019-05-29 | 2019-09-03 | 北京灵思创奇科技有限公司 | A kind of Simulink generates the optimization method of dynamic link library |
| CN110674590A (en) * | 2019-10-07 | 2020-01-10 | 中国人民解放军陆军装甲兵学院 | Programming method of real-time simulation program of aircraft based on simulation software Simulink real-time extended RTX |
| CN111460635A (en) * | 2020-03-19 | 2020-07-28 | 南京南瑞继保电气有限公司 | Simulation test method, electronic device and storage medium |
Non-Patent Citations (3)
| Title |
|---|
| WANG CHONGWEN ET AL.: "Design of DSP Virtual Machine Oriented All-Digital Simulation and Testing", 《2011 INTERNATIONAL CONFERENCE ON FUTURE COMPUTER SCIENCE AND EDUCATION》, pages 571 - 574 * |
| WELBERT A. RODRIGUES ET AL.: "Voltage and Power Balance Strategy without Communication for a Modular Solid State Transformer Based on Adaptive Droop Control", 《ENERGIES》, vol. 11, no. 7, pages 5 - 13 * |
| 胡波等: "基于时间仿真模型的DSP软件仿真系统", 《计算机仿真》, vol. 26, no. 11, pages 313 - 315 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113705004B (en) | 2023-06-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Nugteren et al. | A detailed GPU cache model based on reuse distance theory | |
| US7987075B2 (en) | Apparatus and method to develop multi-core microcomputer-based systems | |
| Lai et al. | Fast profiling framework and race detection for heterogeneous system | |
| US8041551B1 (en) | Algorithm and architecture for multi-argument associative operations that minimizes the number of components using a latency of the components | |
| CN113705004B (en) | Real-time system behavior level software simulation method suitable for DSP | |
| Syrowik et al. | Use of CPU performance counters for accelerator selection in HLS-generated CPU-accelerator systems | |
| US20220066824A1 (en) | Adaptive scheduling with dynamic partition-load balancing for fast partition compilation | |
| Posadas et al. | Single source design environment for embedded systems based on SystemC | |
| Schorr et al. | Integrated time-and event-triggered scheduling-An overhead analysis on the ARM architecture | |
| Panwar et al. | Online performance projection for clusters with heterogeneous GPUs | |
| CN106020982A (en) | Method for simulating resource consumption of software component | |
| Hammond et al. | Predictive simulation of HPC applications | |
| Bronevetsky et al. | Clomp: Accurately characterizing openmp application overheads | |
| Garanina et al. | Model Checking Meets Auto-Tuning of High-Performance Programs | |
| Pimentel et al. | An architecture workbench for multicomputers | |
| Cornelis et al. | The pipeline performance model: a generic executable performance model for GPUs | |
| Kim et al. | Software platform for hybrid resource management of a many-core accelerator for multimedia applications | |
| Sjöström | Parallelizing the Edge application for GPU-based systems using the SkePU skeleton programming library | |
| Kelm et al. | CIGAR: Application partitioning for a CPU/coprocessor architecture | |
| Fryer et al. | Strategies for heterogeneous multi-core processing based on graph programming | |
| George et al. | Distributed simulation of parallel DSP architectures on workstation clusters | |
| ne Zeller et al. | Performance analysis of MPI-based FEniCS/PETSc models in pyMOR | |
| Trabes | Efficient DEVS Simulations Design on Heterogeneous Platforms | |
| Rubini et al. | Modeling shared-memory multiprocessor systems with AADL | |
| Terrosi et al. | Modeling of GPGPU architectures for performance analysis of CUDA programs |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |