CN113703799A

CN113703799A - Computing device and BIOS updating method and medium thereof

Info

Publication number: CN113703799A
Application number: CN202010436449.8A
Authority: CN
Inventors: 杨林; 马秋涛; 董德远
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-05-21
Filing date: 2020-05-21
Publication date: 2021-11-26
Anticipated expiration: 2040-05-21
Also published as: WO2021233363A1; CN113703799B

Abstract

The application relates to the field of computers, and discloses a computing device and a BIOS system updating method and medium thereof. The updating method of the BIOS system comprises the following steps: an operating system of the computing device enters a sleep state; restarting the basic input and output system after the operating system enters a dormant state; the basic input and output system acquires an update file of the basic input and output system, and executes the update of the basic input and output system based on the acquired update file; and after the basic input and output system is updated, the operating system is awakened from the dormant state. The updating of the BIOS system can be completed after the operating system of the computing equipment enters the dormant state, the computing equipment does not need to be restarted, and the working state of the operating system can be maintained before and after the updating of the BIOS system.

Description

Computing device and BIOS updating method and medium thereof

Technical Field

The application relates to the field of computers, and particularly discloses a computing device and a BIOS updating method and medium thereof.

Background

A Basic Input Output System (BIOS) is generally a set of programs stored in a nonvolatile memory on a computer motherboard, and includes the most important Basic Input Output programs of a terminal, a self-test program after power-on, a System self-boot program, and the like, which are one of the root bases of a terminal System. With the rapid development of computers, the BIOS is updated more and more frequently as the most important bottom firmware of the PC. The iteration and the updating of the BIOS can better solve product problems, such as security loopholes of hardware such as a Central Processing Unit (CPU) and the like and product design problems, so that the user experience is improved.

However, because the BIOS update requires the system restart, the current operation of the system cannot be saved, and thus the update will of the user is not strong, and in addition, the current BIOS cannot force the update to be pushed.

Disclosure of Invention

An object of the present application is to provide a computing device, a BIOS updating method and medium thereof, which enable updating of a BIOS without restarting an operating system, thereby saving a current operation of the operating system.

In a first aspect, an embodiment of the present application provides an update method for a basic input output system of a computing device, including: an operating system of the computing device enters a sleep state; restarting the basic input and output system after the operating system enters a dormant state; the basic input and output system acquires an update file of the basic input and output system, and executes the update of the basic input and output system based on the acquired update file; and after the BIOS finishes updating, the operating system wakes up from the sleep state.

In this method, the OS is put into a sleep state, and the BIOS is turned off. Then, the BIOS is restarted, so that the BIOS starts to be updated, and the OS is awakened after the BIOS is updated. Thereby saving the current operation of the OS while completing the BIOS update.

In one implementation of the first aspect, the entering of the operating system of the computing device into the sleep state includes: and the updating program of the basic input and output system sends a sleep instruction to the operating system, and the operating system enters a sleep state. Specifically, the update program of the BIOS may send a hibernation instruction to the CPU of the computing device through the BIOS, the CPU turns off the power, and the OS enters a hibernation state.

In an implementation of the first aspect, after the operating system enters the sleep state, restarting the bios includes: and after the operating system enters a dormant state, the embedded controller of the computing equipment resets the central processing unit of the computing equipment so as to restart the basic input and output system.

After the OS enters the sleep state, the EC decoupled from the OS is still in a working state, so the EC decoupled from the OS can be used to reset the CPU, thereby restarting the BIOS for updating.

In an implementation of the first aspect, the method further includes: before the operating system enters a dormant state, the basic input and output system sets a wakeup flag bit for the embedded controller, wherein the embedded controller resets the central processing unit after acquiring the wakeup flag bit.

In an implementation of the first aspect, the method further includes: and the embedded controller deletes the awakening zone bit after resetting the central processing unit.

In one implementation of the first aspect, the bios performs the updating of the bios by: the basic input and output system writes the update file into a basic input and output system chip of the computing equipment; the BIOS resets a central processing unit of the computing device to load the update file in the BIOS chip into a memory of the computing device.

After writing the update file of the BIOS into the BIOS chip, the BIOS needs to reset the CPU, so as to load the update file of the BIOS into the memory to complete the update of the BIOS.

In an implementation of the first aspect, after the bios completes the update, the waking up the operating system from the sleep state includes: reading relevant data before the operating system enters a sleep state from a hard disk of the computing equipment; and based on the acquired related data, returning the operating system to a working state before entering the dormant state.

In a second aspect, an embodiment of the present application discloses an updating method of a basic input output system of a computing device, including: the basic input and output system sends a sleep instruction acquired from an updating program of the basic input and output system to an operating system of the computing device, wherein the sleep instruction is used for instructing the operating system to enter a sleep state; the basic input and output system is restarted; the basic input and output system acquires an update file of the basic input and output system; and the basic input and output system executes the updating of the basic input and output system based on the acquired updating file.

In an implementation of the second aspect, the completing, by the bios, the update of the bios based on the obtained update file includes: the basic input and output system writes the update file into a basic input and output system chip of the computing equipment; and the basic input and output system restarts a central processing unit of the computing device so as to load the update file in the basic input and output system chip into a memory of the computing device.

In a third aspect, an embodiment of the present application discloses an updating method for a basic input output system of a computing device, including: the embedded controller of the computing equipment detects that the power state of a central processing unit of the computing equipment is a dormant state; and the embedded controller resets the central processing unit so as to restart the basic input and output system of the computing equipment to update the basic input and output system.

In one implementation of the third aspect, the resetting the central processor by the embedded controller includes:

and the embedded controller resets the central processing unit under the condition of acquiring the awakening flag bit.

In an implementation of the third aspect, the method further includes:

the embedded controller detects that the basic input and output system writes the update file of the basic input and output system into a basic input and output system chip of the computing equipment; and the embedded controller resets a central processing unit of the computing equipment so as to write the update file into a memory of the computing equipment.

In a fourth aspect, embodiments of the present application disclose a readable medium of a computing device, the readable medium having stored thereon instructions that, when executed on the computing device, cause the computing device to perform the method of the first or second aspect.

In a fifth aspect, embodiments of the present application disclose a computing device, comprising: a memory and a controller;

wherein the memory is to store instructions for execution by one or more controllers of a computing device;

the controller comprises a central processing unit and an embedded controller, and is used for executing the method of the first or second aspect.

Drawings

Fig. 1 is a schematic structural diagram of a computer 100 according to an embodiment of the present application.

FIG. 2 is a BIOS update control system 200 according to an embodiment of the present application.

FIG. 3 is a flow chart of a BIOS update method according to an embodiment of the present application.

FIG. 4(a) is a diagram of an operating system display interface prior to a BIOS update, according to an embodiment of the present application.

FIG. 4(b) is a diagram of an operating system display interface after a BIOS update according to an embodiment of the present application.

FIG. 5 is a schematic diagram of an example computing device, according to an embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. It will be apparent, however, to one skilled in the art that some alternative embodiments may be practiced using the features described in part. For purposes of explanation, specific numbers and configurations are set forth in order to provide a more thorough understanding of the illustrative embodiments. It will be apparent, however, to one skilled in the art that alternative embodiments may be practiced without the specific details. In some other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments of the present application. It should be noted that in this specification, like reference numerals and letters refer to like items in the following drawings.

In various electronic devices such as computers, the BIOS is a very important underlying firmware, and iteration and updating of the BIOS can better solve product problems, such as security holes of hardware such as CPUs and product design problems, thereby improving user experience. But updates to the BIOS typically require a system reboot, resulting in the current operation of the system not being preserved. Based on the situation, the embodiment of the application provides a scheme capable of saving the current operation while updating the BIOS.

Illustrative embodiments of the present application include, but are not limited to, BIOS update methods, apparatus, media, devices, systems, and the like.

Embodiments of the present application may be applied to various electronic devices with Embedded Controllers (ECs), such as personal computers, notebook computers, desktop computers, handheld or laptop computers, tablet computers, portable game machines, servers, and the like.

Next, taking the computer 100 as an example, a schematic structural diagram of an electronic device according to an embodiment of the present application is described with reference to fig. 1.

As shown in fig. 1, the computer 100 may include a main processor 110, a memory 120, an input device 130, an embedded controller 140, a display card 150, a display screen 151, a power supply 160, a sensor 170, an audio module 180, and the like.

It is to be understood that the illustrated structure of the embodiment of the invention is not intended to limit the computer 100. In other embodiments of the present application, computer 100 may include more or fewer components than shown, or some components may be combined, or some components may be split, or a different arrangement of components and/or a different architecture. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The main processor 110 is a control center of the computer 100, connects various parts of the entire computer 100 using various interfaces and lines, and performs various functions and data processing of the computer 100 by running or executing software programs and/or data stored in the memory 120, thereby performing overall control of the computer 100. For example, the main processor 110 may perform related operations performed by the CPU222 and the like described below in conjunction with fig. 2 and 3, so as to implement the functions provided by the embodiments of the present application.

The main processor 110 may include one or more processing units, wherein the different processing units may be separate devices or may be integrated into one or more processors. A memory may also be provided in the main processor 110 for storing instructions and data. In some embodiments, the memory in the main processor 110 is a cache memory. The memory may hold instructions or data that the main processor 110 has just used or cycled through. If the host processor 110 needs to use the instruction or data again, it can be called directly from the memory. Avoiding repeated accesses reduces the latency of the host processor 110, thereby increasing the efficiency of the system.

The memory 120 may include any suitable non-volatile memory and/or any suitable non-volatile storage device, such as flash memory, Hard Disk Drive (HDD), solid-state drive (SSD), Compact Disk (CD) drive, and/or Digital Versatile Disk (DVD) drive, among others. The memory 120 may be used to store computer-executable program code, which includes instructions. According to some embodiments of the present application, the memory 120 may include a program storage area and a data storage area. The storage program area may store an operating system, an application program required for at least one function (e.g., a function of controlling the computer 100 to enter a sleep state, a function of waking up the computer 100, etc.), and the like. The storage data area may store data (e.g., audio data, image data, etc.) created during use of the computer 100, etc. The main processor 110 executes various functional applications of the computer 100 and data processing by executing instructions stored in the memory 120 and/or instructions stored in a memory provided in the processor.

The input device 130 may be used to receive input digital information, character information, or contact touch operation/non-contact gesture, and to generate signal input related to user setting and function control of the computer 100, etc.

Specifically, according to some embodiments of the present application, the input device 130 may include a touch panel 131, a keyboard 132, and a mouse 133. The touch panel 131 can be used to collect touch operations of a user (for example, operations of the user on the touch panel 131 by using a finger, a stylus pen, or any other suitable object or accessory) on or near the touch panel 131, and drive the corresponding connection device according to a preset program. Characters, numbers, punctuation marks, etc. may be input into the computer 100 through the keyboard 132, or commands may be issued to the computer 100 through function keys on the keyboard 132. The mouse 133 can position the cursor on the current display screen 151 and operate the screen element at the position where the cursor passes through by means of the button and wheel device, so as to trigger the computer 100 to execute the corresponding command.

According to some embodiments of the present application, computer 100 may also include other input devices, which may include, but are not limited to, any one or more of function keys (e.g., volume control keys, switch keys, etc.), a trackball, a light pen, a joystick, and the like.

Embedded Controller (EC) 140 is a control system for performing specified independent control functions and having complex data processing capabilities. EC 140 controls the timing of most important signals during system startup. For example, in embodiments of the present application below, EC 140 wakes up the BIOS by booting CPU222 to perform a BIOS update.

The display screen 151 may be used to display information input by a user or information provided to the user, for example, various menu interfaces of the computer 100, and the like. The display screen 151 includes a display panel. The display panel may adopt a Liquid Crystal Display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (active-matrix organic light-emitting diode, AMOLED), a flexible light-emitting diode (FLED), a miniature, a Micro-oeld, a quantum dot light-emitting diode (QLED), and the like. Alternatively, the display screen 151 may be configured in the form of a Liquid Crystal Display (LCD) or an organic light-emitting diode (OLED). In some embodiments, a portion of the touch panel 131 may be integrated with the display screen 151, forming a touch display screen.

The graphic card 150 may include a Graphic Processing Unit (GPU) or a Video Processing Unit (VPU) for converting a digital signal input to the computer 100 into an analog signal and displaying the converted analog signal on the display screen 151, and the graphic card 150 also has an image Processing capability, and the processed image is displayed on the display screen 151. The display card 150 may be integrated on the motherboard of the computer 100, or may be independent from the motherboard of the computer 100.

The power supply 160 is used for supplying power to other modules, and the power supply 160 may include a charging management module and a power management module. The charging management module is configured to receive a charging input from a charger. The charger may be a wireless charger or a wired charger. The charging management module can charge the battery and supply power to the electronic equipment through the power management module. The power management module is configured to receive input from a battery and/or a charging management module and to provide power to the modules in the computer 100. The power management module may also be used to monitor parameters such as battery capacity, battery cycle number, battery state of health (leakage, impedance), etc.

The computer 100 may include one or more sensors 170 for sensing various information and converting the sensed information into an electrical signal or other desired form of information output according to a certain rule. In embodiments of the present application, the sensor 170 may include various types of sensors, such as an image sensor, a brightness sensor, a light sensor, a GPS sensor, an infrared sensor, and the like.

The computer 100 may implement audio functions through the audio module 180, the speaker 181, the microphone 182, the headphone interface 183, the main processor 110, and the like. Such as music playing, recording, etc.

The audio module 180 is used to convert digital audio information into an analog audio signal output and also used to convert an analog audio input into a digital audio signal. The audio module 180 may also be used to encode and decode audio signals. In some embodiments, the audio module 180 may be disposed in the main processor 110, or some functional modules of the audio module 180 may be disposed in the main processor 110.

The speaker 181 converts an audio electric signal into a sound signal. The computer 100 may output sound through the speaker 181.

The microphone 182 is used to pick up sound signals and convert the sound signals into electrical signals. The computer 100 may be provided with at least one microphone 182. In other embodiments, the computer 100 may be provided with two microphones 182 to achieve noise reduction functions in addition to collecting sound signals. In other embodiments, three, four or more microphones 182 may be provided for the computer 100 to collect sound signals, reduce noise, identify sound sources, perform directional recording, and so on.

The earphone interface 183 is used to connect a wired earphone. The headset interface 183 may be a USB interface, an open mobile electronic device platform (OMTP) standard interface of 3.5mm, a cellular telecommunications industry association (cellular telecommunications industry association of the USA, CTIA) standard interface, or the like.

In addition, the computer 100 may further include a Radio Frequency (RF) circuit 191 for performing network communication with a wireless network device, and may further include a WIFI module 192 for performing WIFI communication with other devices, acquiring data transmitted by other devices, and the like.

A BIOS update control system 200 according to an embodiment of the present application is described below in conjunction with figure 2. The update control system 200 may be implemented in a computer 100 as shown in FIG. 1.

The update control System 200 may include a Software (SW) portion 210 and a Hardware (Hardware) portion 220, the Software 210 portion includes a Basic Input Output System (BIOS) 211 and an Operating System (OS) 212, and the Hardware 220 portion may include a hard disk 221, a Central Processing Unit (CPU) 222, a BIOS chip 223, and an Embedded Controller (EC) 224.

The OS 212 is a computer program for managing hardware and software resources in a computer, and is mainly used to process basic transactions such as managing and configuring memory, determining priorities of supply and demand of system resources, controlling input devices and output devices, operating a network, and managing a file system. OS 212 may schedule various resources of the computer system, including hardware and software devices and data, information, etc., while also providing an interface for users to interact with computer 100. Common operating systems include, but are not limited to: windows, Android, IOS, etc. It is understood that in the embodiment of the present application, the OS 212 is decoupled from the EC 224, and after the OS 212 is hibernated, the EC 224 continues to operate, and performs the functions of waking up the CPU222, and the like.

The BIOS211 is a set of programs solidified in a BIOS chip 223 on a computer motherboard, and includes a program of the most important basic input and output of the computer, a power-on self-test program, and a system self-start program, and is used to directly perform hardware-level control on input and output devices in the computer system, and provide a basis for establishing connections between other software programs and hardware devices. The BIOS211 is a program executed first after the computer is powered on, and completes functions of initializing, setting, testing, and the like of each hardware device of the system, so as to ensure that the system can operate normally. After the BIOS211 initializes the hardware resources, the OS 212 operates to perform various services through the initialized hardware resources.

Specifically, from the power-on of the host of the computer 100 to the loading of the bootloader (boot loader), that is, the BIOS211 completes the boot task and enters the idle state, the BIOS211 mainly goes through three stages: pown On (inactive Power phase), POST (Power On self tests), and load bootloader. Wherein:

1) the main tasks of the Pown On phase are to verify the correct content in CMOS (Complementary Metal Oxide Semiconductor), check the status of some hardware On the host to determine the next self-test.

2) The post (power on self test) stage checks whether some key devices such as memory and display card can work normally, and provides simple memory test, and as long as the test is not problematic, the basic information of the hardware is displayed on the screen. In general, the basic process of BIOS211 during the POST phase is as follows: the BIOS211 searches the BIOS code of the display card, then calls the initialization code of the display card, the BIOS of the display card completes the initialization of the display card, and then the screen can display information; subsequently, the BIOS211 calls the BIOS code of the found other device to complete the initialization of the corresponding device, and so on. After checking other devices, the BIOS211 displays its own start-up screen, and then checks the type and operating frequency of the CPU222, the memory capacity of the computer, and the like; the BIOS211 then begins testing and configuring some of the standard hardware devices installed in the system, such as hard disks, optical drives, interfaces, etc., and the BIOS211 then checks and configures the plug-and-play devices in the computer system. Generally, all devices that need to be used at and after power-on are activated during the POST phase.

3) In the bootloader loading stage, the method after the BIOS quits from the background is to give the Master control right of the loaded OS to the MBR (Master Boot Record) of the hard disk, i.e., the content of the physical sector 0, column 0, and face 1 of the hard disk, and let the Boot manager (bootloader) hidden here bring the pointer to the system core.

Further, it is understood that in some embodiments of the present application, the BIOS211 exits after the OS 212 enters the sleep state, and the BIOS211 can be restarted after the CPU222 is reset. As will be described in detail below.

The hard disk 221 is one of the most important memories in a computer. Most of the application programs and data required for the computer to normally operate are stored on the hard disk 221. The hard disk 221 may include, but is not limited to: solid State Drive (SSD), Hard Disk Drive (HDD), and the like. When updating the BIOS211, the BIOS update utility may initially store a binary (bin) file of the BIOS to the hard disk 221. It should be appreciated that in embodiments of the present application, the storage location of the bin file of the BIOS is not limited to the hard disk 221, and in some embodiments, the bin file of the BIOS (i.e., the update file of the BIOS) may be stored in various internal memories or accessible external storage devices, for example, a removable storage device such as a usb disk.

The CPU222 is a core hardware unit that performs control and allocation of all hardware resources of the computer 100 and executes general-purpose operations. The CPU222, as the operation and control core of the computer 100, is the final execution unit for information processing and program operation, and the operations of all software layers 210 in the computer system will be mapped into the operations of the CPU222 through the instruction set. In some embodiments of the present application, the BIOS update program sends a hibernate command to the CPU222 via the BIOS211, and the OS 212 enters a hibernate state.

The BIOS chip 223 is a nonvolatile memory provided on a computer main board and stores the aforementioned BIOS211, and it can keep data from being lost without supplying power. The BIOS chip 223 may be a Read-Only Memory (ROM) chip or a Flash Memory (Flash) chip, etc. The BIOS chip is typically a flash rom (flash read only memory) chip. At present, the capacity of a flash rom chip is generally 1M or 2M to 8M, and is roughly divided into two series 28 and 29. The 28-series flash rom chip is a dual voltage design that can be read at 5V, while writing must provide 12V. The mainboard of the chip needs to be opened and the jumper setting needs to be changed when the mainboard is upgraded. The 29 series FlashROM chip is relatively simple, and because the single-voltage design is adopted, 5V voltage is adopted for reading and writing, so that the Firmware reading and writing operation can be completed only by software.

Embedded Controller (EC) 224 is a control system for performing specified independent control functions and having complex data processing capabilities. The EC 224 is used as a single processor and can be realized by adopting a single chip microcomputer, and plays a role in overall management on the whole system before and during the startup process. The EC 224 performs the control function by using a logic program (i.e., EC code) stored in the Flash, in some embodiments, the EC 224 itself may integrate Flash with a certain capacity, or the like, to store the EC code, and in some embodiments, the EC 224 may not integrate Flash, but store the EC code in the BIOS chip 223.

The EC 224 controls the timing of most important signals during system startup. In a computer, the EC 224 will always be on whenever power is applied, whether the computer is in a power-on state or a power-off state, unless the battery and adapter are completely removed. In the off state, the EC 224 remains running and waits for user power-on information. After the device is turned on, the EC 224 performs control or support of the functions of the keyboard, the fan, charging and discharging, the indicator light, etc., and is responsible for the tasks of the keyboard, the mouse, the battery power supply and the temperature control detection. In some embodiments, the EC 224 is also used to control the standby, sleep, etc. states of the system.

The process of performing a BIOS update using the BIOS update control system 200 shown in fig. 2 is described below with reference to fig. 3.

First, S301: in the operating state of the OS 212, the BIOS update tool is used to store a new BIOS bin file in a designated location of a hard disk of the computer, where the designated location is determined by a storage path of the BIOS bin file, and the file storage path may be set by default by the BIOS update tool or may be defined by a user. For example, the new BIOS bin file may be stored in an EFI System Partition (ESP) of the hard disk 221 so that the BIOS211 may be accessed directly without a driver. It is understood that the new BIOS bin file may also be stored in other partitions of the hard disk 221 or other storage devices of the computer 100.

S302: an update flag (update flag) is set by the BIOS211 update tool, and the update flag can be used in the POST process of the BIOS211 to enable the BIOS211 to self-check whether update is needed.

S303-S304: the BIOS211 update utility notifies the BIOS to send a hibernate instruction to the CPU222 to put the computer into a hibernate state. Wherein, when the OS 212 enters the sleep state, the BIOS211 also exits.

For example, as shown in fig. 4a, when the computer system enters the hibernation state, the user may be prompted through the display interface of the computer 100 that the computer system is about to enter the hibernation state for BIOS update, and after the user clicks to confirm, the computer system enters the hibernation state. If the user chooses to update later, the user may be alerted to the update after a predetermined time. Or the user may also be given an option to update the time, such as selecting a 4 hour later update, selecting a night update, etc.

According to some embodiments of the present application, the sleep instruction sent by the BIOS211 to the CPU222 may be an S4 sleep instruction to control the computer system to enter an S4 state, also referred to as a Suspend To Disk (STD) state. In the S4 state, the CPU222 is powered off, the system main power is off, but the hard disk is still powered and can be woken up, the relevant data in operation is saved to the hard disk, and then all components stop working. In the STD state, the current operation of the user is not lost, and then the system can be waken up again by pressing a power key and other operations, and after the system is waken up, the relevant data can be read from the hard disk and recovered to the working state before STD.

According to other embodiments of the present application, the sleep command sent by the BIOS211 to the CPU222 may also be an S3 sleep command to control the computer system to enter an S3 state, which is also referred to as a Suspend To RAM (STR) state. In the STR state, the power of the CPU222 is also turned off, and the operating state data of the system before entering STR is stored in the memory. In the STR state, the power supply still continues to supply power to the most necessary components, such as the memory, to ensure that data is not lost, while other components are all in the off state. Similarly, the system can be re-awakened by pressing a power key and the like, and the data can be read from the memory and restored to the working state before the STR immediately after the system is awakened. Because the memory has a very fast read and write speed, the time to enter and leave the STR state is shorter than the time to enter and leave the STD state. The system entering S3 or S4 sleep may be implemented via an Advanced Configuration and Power Interface (ACPI).

Further, it is understood that in other embodiments, the BIOS211 may send the hibernate instruction to the CPU222 through other systems that coexist on the computer 100, for example, the BIOS211 may send the hibernate instruction to the CPU through the OS 212.

S305: according to some embodiments of the present disclosure, the operation of configuring the wake flag by the BIOS211 may be performed while the BIOS211 sends the sleep instruction to the CPU222, or may be performed before or after the operation of sending the sleep instruction by the BIOS211 to the CPU222, but it is to be ensured that the operation of configuring the wake flag by the BIOS211 for the EC 224 is completed when the BIOS211 has an operation right, that is, is completed before the CPU222 sleeps. The wake-up flag is set before the CPU222 is hibernated, so that after the computer system enters the hibernation state, the EC 224 can start the CPU222 according to the obtained wake-up flag, thereby waking up the BIOS211 to update the BIOS.

Under normal conditions, after the BIOS211 sends a sleep instruction to the CPU222, the OS 212 and the BIOS211 enter a sleep state together, and in order to enable the BIOS to be woken up and updated, the embodiment of the present application configures a wake-up flag for the EC 224 while sending the sleep instruction to the CPU 222. The wake flag is set in a location accessible by the EC 224 so that the BIOS211 may be woken up after the EC 224 reads the wake flag.

S306: BIOS211 is woken up using EC 224 and the wake flag is cleared.

Since the EC 224 will always be on at power-on, the EC 224 will remain on even if the computer goes to sleep and can access the previously set wake-up flag. In an embodiment of the present application, the EC 224 is configured to perform the operation of resetting the CPU222 after reading the wake-up flag, the BIOS211 is turned on after the CPU222 is reset, and the wake-up flag is cleared after the BIOS211 is turned on. This clearing operation may be performed by the EC after accessing the wake-up flag; or may be performed by the BIOS211, for example, the BIOS211 may set the wake-up flag to be cleared when the wake-up flag is accessed during configuration.

S307-S308: after the BIOS211 is turned on, a boot task is performed, and a BIOS update operation is performed in a case where an update flag is detected (for example, the update flag is detected as 1) in the POST stage. As described above, the BIOS211 enters the POST stage when executing the boot task, and in the POST stage, when detecting that the update flag is 1, the BIOS211 executes the BIOS update operation, writes the BIOS bin file originally stored in the hard disk 221 into the BIOS chip 223, and clears the update flag.

Specifically, after the BIOS211 detects that the update flag is 1 in the POST stage, the BIOS211 may read a new BIOS file from a specified location of the hard disk 221, for example, read the new BIOS file from the ESP mentioned above, then perform verification and authentication on the new BIOS file (for example, verify whether the new BIOS file carries a virus, detect the integrity of the new BIOS file, and the like), confirm that the new BIOS file stored in the ESP needs to be updated, and check whether the update condition is currently met. According to some embodiments of the present application, the upgrade condition may include whether the current electric quantity of the computer device meets the upgrade requirement, and the upgrade condition may be set by a user, which is not limited herein.

After the BIOS211 confirms that the new BIOS file to be updated is stored in the ESP, and the current computer device has the update condition, the preparation for updating the BIOS is started, and the new BIOS file is written into the BIOS chip 223. After completing the writing action of the new BIOS file, the read-write check can be carried out, the successful check indicates that the BIOS is successfully written, and if the check fails, the BIOS can be rewritten.

After the BIOS211 writes the new BIOS file into the BIOS chip 223, the BIOS211 sends a message that the update file is successfully written into the BIOS chip 223 to the EC 224, and the BIOS211 enables the CPU222 to restart, and after the CPU222 restarts, the new BIOS file in the BIOS chip 223 is loaded into the memory of the computer 100, so that the BIOS211 finishes updating.

In addition, it may be understood that, in other embodiments, the EC 224 may instruct the CPU to restart, that is, after the BIOS211 writes the new BIOS file into the BIOS chip 223, the BIOS211 sends a message that the update file is successfully written into the BIOS chip 223 to the EC 224, the EC 224 restarts the CPU222, and after the CPU222 restarts, the new BIOS file in the BIOS chip 223 is loaded into the memory of the computer 100, so that the BIOS211 finishes updating.

S309: after the BIOS211 is updated and successfully started, the OS 212 wakes up from the hibernation state, enters the S0 state, reads the operation-related data from the memory or the hard disk, and restores to the working state before hibernation, so that the operation related to the system before BIOS update is saved. For example, as shown in FIG. 4b, after the BIOS211 is updated, the OS 212 enters the S0 state to save the related operations before the update. The S0 state of the OS 212 is a normal operating state of the OS 212, and the hardware devices of the computer 100 are basically turned on.

Embodiments of the present application enable the updating of the BIOS211 through the interactive design of the OS 212, BIOS211, and EC 224. During the BIOS update process, the BIOS211 is decoupled from the OS 212, such that the OS 212 remains in a hibernate state and the BIOS211 initiates the update. In the update process of the BIOS211, the OS 212 is in the S3 or S4 hibernation state, so that the current operation state, files, and the like of the OS system can be saved, and the current system operation is not lost while the BIOS update is realized, thereby satisfying the requirements of automatic update and forced update of the BIOS211 in an idle state.

An example computing device 500 in accordance with some embodiments of the present application is described below in conjunction with FIG. 5. In embodiments of the present application, the computing device 500 may be or include the update control system 200 shown in FIG. 2, and in various embodiments, the computing device 500 may have more or fewer components and/or different architectures.

In one embodiment, computing device 500 may include one or more processors 504, system control logic 508 coupled to at least one of processors 504, system memory 512 coupled to system control logic 508, storage 516 (e.g., non-volatile memory (NVM)) coupled to system control logic 508, and a network interface 520 coupled to system control logic 508.

Processor 504 may include one or more single-core or multi-core processors. Processor 504 may include any combination of general-purpose processors and special-purpose processors (e.g., graphics processors, application processors, baseband processors, etc.). In some cases, the processor 504 may be configured to perform various operations described above in connection with fig. 2-3 as being performed by the CPU222 or the EC 224.

System control logic 508 for certain embodiments may include any suitable interface controllers to provide any suitable interface to at least one of processors 504 and/or any suitable device or component in communication with system control logic 508. System control logic 508 for one embodiment may include one or more memory controllers to provide an interface to system memory 512. System memory 512 may be used to load and store data and/or instructions, for example, for computing device 500, system memory 512 for an embodiment may comprise any suitable volatile memory, such as suitable random-access memory (RAM) or Dynamic Random Access Memory (DRAM).

Memory 516 may include one or more tangible, non-transitory computer-readable media for storing data and/or instructions. For example, the memory 516 may include any suitable non-volatile memory and/or any suitable non-volatile storage device, such as flash memory, a Hard Disk Drive (HDD), a solid-state drive (SSD), a Compact Disk (CD) drive, a Digital Versatile Disk (DVD) drive, and/or the like.

Memory 516 may comprise a portion of a storage resource on the apparatus on which computing device 500 is installed, or it may be accessible by, but not necessarily a part of, the device. For example, the memory 516 may be accessed over a network via the network interface 520.

In particular, system memory 512 and storage 516 may each include: temporary and permanent copies of instructions 524. The instructions 524 may include: instructions that, when executed by at least one of the processors 504, cause the computing device 500 to implement the methods described above. In various embodiments, the instructions 524 or hardware, firmware, and/or software components thereof may additionally/alternatively be disposed in the system control logic 508, the network interface 520, and/or the processor 504.

Network interface 520 may include a transceiver to provide a radio interface for computing device 500 to communicate with any other suitable device (e.g., front end module, antenna, etc.) over one or more networks. In various embodiments, network interface 520 may be integrated with other components of computing device 500. For example, the network interface may include processors of the processors 504, memory of the system memory 512, storage of the storage 516, and/or a firmware device (not shown) having instructions that, when executed by at least one of the processors 504, cause the computing device 500 to implement the method as described in fig. 3.

The network interface 520 may further include any suitable hardware and/or firmware to provide a multiple-input multiple-output radio interface. For example, network interface 520 for one embodiment may be a network adapter, a wireless network adapter, a telephone modem, and/or a wireless modem.

For one embodiment, at least one of the processors 504 may be packaged together with logic for one or more controllers of system control logic 508. For one embodiment, at least one of the processors 504 may be packaged together with logic for one or more controllers of system control logic 508 to form a System In Package (SiP). For one embodiment, at least one of the processors 504 may be integrated with logic for one or more controllers of system control logic 508. For one embodiment, at least one of the processors 504 may be integrated with logic for one or more controllers of system control logic 508 to form a system on a chip (SoC).

The computing device 500 may further include: input/output (I/O) devices 532. The I/O devices 532 may include a user interface designed to enable a user to interact with the computing device 500; a peripheral component interface designed to enable peripheral components to also interact with computing device 500; and/or sensors designed to determine environmental conditions and/or location information associated with computing device 500, etc.

The embodiments disclosed herein may be implemented in hardware, software, firmware, or a combination of these implementations. Embodiments of the application may be implemented as computer programs or program code executing on programmable systems that may include at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Program code may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices in a known manner.

The program code in the present application may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The program code can also be implemented in assembly or machine language, if desired. Indeed, the mechanisms described in this application are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.

In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented in the form of instructions or programs carried on or stored on one or more transitory or non-transitory machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors or the like. When the instructions or program are executed by a machine, the machine may perform the various methods described previously. For example, the instructions may be distributed via a network or other computer readable medium. Thus, a machine-readable medium may include, but is not limited to, any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), such as floppy diskettes, optical disks, compact disc read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), Random Access Memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or flash memory or tangible machine-readable memory for transmitting network information via electrical, optical, acoustical or other forms of signals (e.g., carrier waves, infrared signals, digital signals, etc.). Thus, a machine-readable medium includes any form of machine-readable medium suitable for storing or transmitting electronic instructions or machine (e.g., a computer) readable information.

Accordingly, embodiments of the present application also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, devices, processors, and/or system features described herein. These embodiments are also referred to as program products.

It will be understood that, although the terms "first", "second", etc. may be used herein to describe various features, these features should not be limited by these terms. These terms are used merely for distinguishing and are not intended to indicate or imply relative importance. For example, a first feature may be termed a second feature, and, similarly, a second feature may be termed a first feature, without departing from the scope of example embodiments.

Moreover, various operations will be described as multiple operations separate from one another in a manner that is most helpful in understanding the illustrative embodiments; however, the order of description should not be construed as to imply that these operations are necessarily order dependent, and that many of the operations can be performed in parallel, concurrently, or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when the described operations are completed, but may have additional operations not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.

References in the specification to "one embodiment," "an illustrative embodiment," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature is described in connection with a particular embodiment, the knowledge of one skilled in the art can affect such feature in combination with other embodiments, whether or not such embodiments are explicitly described.

The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise. The phrase "A/B" means "A or B". The phrase "A and/or B" means "(A), (B) or (A and B)".

As used herein, the term "module" may refer to, be a part of, or include: memory (shared, dedicated, or group) for executing one or more software or firmware programs, an Application Specific Integrated Circuit (ASIC), an electronic circuit and/or processor (shared, dedicated, or group), a combinational logic circuit, and/or other suitable components that provide the described functionality.

In the drawings, some features of the structures or methods may be shown in a particular arrangement and/or order. However, it should be understood that such specific arrangement and/or ordering is not required. Rather, in some embodiments, these features may be described in a manner and/or order different from that shown in the illustrative figures. Additionally, the inclusion of a structural or methodical feature in a particular figure does not imply that all embodiments need to include such feature, and in some embodiments may not include such feature, or may be combined with other features.

While the embodiments of the present application have been described in detail with reference to the accompanying drawings, the application of the present application is not limited to the various applications mentioned in the embodiments of the present application, and various structures and modifications can be easily implemented with reference to the present application to achieve various advantageous effects mentioned herein. Variations that do not depart from the gist of the disclosure are intended to be within the scope of the disclosure.

Claims

1. A method for updating a bios of a computing device, comprising:

an operating system of the computing device enters a sleep state;

restarting the basic input and output system after the operating system enters a dormant state;

the basic input and output system acquires an update file of the basic input and output system, and executes the update of the basic input and output system based on the acquired update file;

and after the BIOS finishes updating, the operating system wakes up from the sleep state.

2. The update method of claim 1, wherein entering the sleep state by the operating system of the computing device comprises:

and the updating program of the basic input and output system sends a sleep instruction to the operating system, and the operating system enters a sleep state.

3. The updating method of claim 2, wherein restarting the bios after the os enters the sleep state comprises:

and after the operating system enters a dormant state, the embedded controller of the computing equipment resets the central processing unit of the computing equipment so as to restart the basic input and output system.

4. The updating method according to claim 3, further comprising:

before the operating system enters a dormant state, the basic input and output system sets a wakeup flag bit for the embedded controller, wherein the embedded controller resets the central processing unit after acquiring the wakeup flag bit.

5. The updating method according to claim 1, further comprising:

and the embedded controller deletes the awakening zone bit after resetting the central processing unit.

6. The update method according to claim 1, wherein the bios performs the update of the bios by:

the basic input and output system writes the update file into a basic input and output system chip of the computing equipment;

the BIOS resets a central processing unit of the computing device to load the update file in the BIOS chip into a memory of the computing device.

7. The updating method of claim 1, wherein waking up the operating system from the sleep state after the bios completes updating comprises:

reading relevant data before the operating system enters a sleep state from a hard disk of the computing equipment;

and based on the acquired related data, returning the operating system to a working state before entering the dormant state.

8. A method for updating a bios of a computing device, comprising:

the basic input and output system sends a sleep instruction acquired from an updating program of the basic input and output system to an operating system of the computing device, wherein the sleep instruction is used for instructing the operating system to enter a sleep state;

the basic input and output system is restarted;

the basic input and output system acquires an update file of the basic input and output system;

and the basic input and output system executes the updating of the basic input and output system based on the acquired updating file.

9. The updating method according to claim 8, wherein the updating of the bios based on the obtained update file comprises:

and the basic input and output system restarts a central processing unit of the computing device so as to load the update file in the basic input and output system chip into a memory of the computing device.

10. A method for updating a bios of a computing device, comprising:

the embedded controller of the computing equipment detects that the power state of a central processing unit of the computing equipment is a dormant state;

and the embedded controller resets the central processing unit so as to restart the basic input and output system of the computing equipment to update the basic input and output system.

11. The method of claim 10, wherein the embedded controller resetting the central processor comprises:

12. The method of claim 10 or 11, further comprising:

the embedded controller detects that the basic input and output system writes the update file of the basic input and output system into a basic input and output system chip of the computing equipment;

and the embedded controller resets a central processing unit of the computing equipment so as to write the update file into a memory of the computing equipment.

13. A readable medium of a computing device having instructions stored thereon that, when executed on the computing device, cause the computing device to perform the method of any of claims 1 to 12.

14. A computing device, comprising: a memory and a controller;

the controller comprises a central processor and an embedded controller for performing the method of any one of claims 1 to 12.