CN113690306B - Array substrate and display panel - Google Patents
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- CN113690306B CN113690306B CN202110899686.2A CN202110899686A CN113690306B CN 113690306 B CN113690306 B CN 113690306B CN 202110899686 A CN202110899686 A CN 202110899686A CN 113690306 B CN113690306 B CN 113690306B
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- 239000000758 substrate Substances 0.000 title claims abstract description 93
- 229910052751 metal Inorganic materials 0.000 claims abstract description 92
- 239000002184 metal Substances 0.000 claims abstract description 92
- 239000004065 semiconductor Substances 0.000 claims abstract description 50
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 239000003990 capacitor Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 8
- 238000005538 encapsulation Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 167
- 238000010586 diagram Methods 0.000 description 23
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 18
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 18
- 239000010409 thin film Substances 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 101150031602 CST11 gene Proteins 0.000 description 1
- 101150092285 Cst12 gene Proteins 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Theoretical Computer Science (AREA)
- Geometry (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Control Of El Displays (AREA)
Abstract
The embodiment of the application discloses an array substrate and a display panel, wherein the array substrate comprises a substrate, a first semiconductor layer, a first metal layer, a second semiconductor layer and a third metal layer which are arranged in a stacked manner from bottom to top, the first semiconductor layer comprises active layers of transistors of various first types, and the second semiconductor layer comprises active layers of transistors of various second types; the first metal layer comprises top grids of all first transistors, the second metal layer comprises a first main scanning line and a second main scanning line, the third metal layer comprises a first sub-scanning line and a second sub-scanning line, the first main scanning line comprises a bottom grid of a reset transistor, the first sub-scanning line comprises a top grid of the reset transistor, the second main scanning line comprises a bottom grid of a compensation transistor, and the second sub-scanning line comprises a top grid of the compensation transistor. The pixel circuit of the polysilicon transistor can reduce the leakage current to the greatest extent, so that the current of the light-emitting element is more stable, and the flicker phenomenon of the display panel is avoided.
Description
Technical Field
The application relates to the field of display, in particular to an array substrate and a display panel.
Background
With the development of multimedia, display devices are becoming more and more important. Accordingly, there is an increasing demand for various types of display devices, particularly in the field of smart phones, ultra-high frequency driving display, low power consumption driving display, and low frequency driving display, which are all current and future development demands.
Since low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) has high mobility and strong driving capability, LTPS thin film transistors are widely used in pixel circuits in OLED display panels (organic light emitting display panels), but LTPS thin film transistors have large leakage currents, and particularly in low frequency display, gate voltages are easily unstable due to the large leakage currents, so that potential differences between gates and sources are unstable, current of OLED light emitting elements is unstable, and a flicker phenomenon occurs in the display panel.
Disclosure of Invention
The embodiment of the application provides an array substrate and a display panel, which can solve the problem that a pixel circuit adopting a polysilicon thin film transistor causes unstable current of an OLED light-emitting element due to larger leakage current of the transistor, and the display panel has a flicker phenomenon.
The embodiment of the application provides an array substrate, which comprises a plurality of pixels arranged in an array, wherein each pixel comprises a driving transistor, a data writing transistor, a reset transistor, a compensation transistor and a light-emitting element, the driving transistor and the data writing transistor are first-class transistors, and the reset transistor and the compensation transistor are second-class transistors;
the array substrate comprises a base, a first semiconductor layer, a first metal layer, a second semiconductor layer and a third metal layer which are arranged in a stacked manner from bottom to top, wherein the first semiconductor layer comprises an active layer of each first type transistor, and the second semiconductor layer comprises an active layer of each second type transistor;
the first metal layer comprises top gates of all first transistors, the second metal layer comprises a first main scanning line and a second main scanning line, the third metal layer comprises a first sub-scanning line and a second sub-scanning line, the first main scanning line comprises a bottom gate of the reset transistor, the first sub-scanning line comprises a top gate of the reset transistor, the second main scanning line comprises a bottom gate of the compensation transistor, and the second sub-scanning line comprises a top gate of the compensation transistor.
Optionally, in some embodiments of the present application, the first type of transistor is a polysilicon transistor and the second type of transistor is an oxide transistor.
Optionally, in some embodiments of the present application, the orthographic projection of the first main scan line on the substrate and the orthographic projection of the first sub scan line on the substrate at least partially overlap;
the orthographic projection of the second main scanning line on the substrate and the orthographic projection of the second sub scanning line on the substrate are at least partially overlapped.
Optionally, in some embodiments of the present application, the active layer of the compensation transistor and the active layer of the reset transistor are an integral structure connected to each other, and a material of the second semiconductor layer between the compensation transistor and the reset transistor is conductive.
Optionally, in some embodiments of the present application, a storage capacitor is further included, and the storage capacitor is electrically connected to the driving transistor;
the first metal layer includes a first capacitance electrode of a storage capacitance, and the second metal layer includes a second capacitance electrode of the storage capacitance.
Optionally, in some embodiments of the present application, a fourth metal layer is further included on a side of the third metal layer away from the substrate,
the fourth metal layer includes a data line and a first power line.
Optionally, in some embodiments of the present application, a fifth metal layer disposed on a side of the fourth metal layer away from the substrate is further included, where the fifth metal layer includes a second power line, the second power line is electrically connected to the first power line, an extension direction of the second power line is the same as an extension direction of the first power line, and an orthographic projection of the second power line on the substrate and an orthographic projection of the first power line on the substrate at least partially overlap.
Optionally, in some embodiments of the present application, the second power line further includes a protrusion, and an orthographic projection of the protrusion on the substrate covers orthographic projections of the driving transistor, the compensation transistor, and the reset transistor on the substrate.
Optionally, in some embodiments of the application, the pixel further includes:
the light emitting diode comprises a reset transistor, a first light emitting control transistor and a second light emitting control transistor, wherein the reset transistor, the first light emitting control transistor and the second light emitting control transistor are of a first type.
Correspondingly, the embodiment of the application provides a display panel, which comprises the array substrate, a pixel definition layer, a light-emitting element and a packaging layer, wherein the array substrate is any one of the above, the pixel definition layer is arranged in an opening of the pixel definition layer, and the packaging layer is arranged on the light-emitting element.
In the embodiment of the application, the array substrate and the display panel are provided, and the double-grid-structure oxide transistor is used as the reset transistor and the compensation transistor, so that the leakage current of the pixel circuit of the polysilicon transistor can be reduced to the greatest extent, the current of the OLED light-emitting element is more stable, and the flicker phenomenon of the display panel is avoided.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an equivalent circuit of a pixel on an array substrate according to an embodiment of the present application;
FIG. 2 is a timing diagram of an equivalent circuit of a pixel on an array substrate according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a cross-sectional film structure of a pixel on an array substrate according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a layout of pixels on an array substrate according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a pattern of a first semiconductor layer in a pixel layout according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a pattern of a first metal layer in a pixel layout according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a pattern of a second metal layer in a pixel layout according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a pattern of a second semiconductor layer in a pixel layout according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a third metal layer in a pixel layout according to an embodiment of the present application;
FIG. 10 is a schematic diagram of a fourth metal layer in a pixel layout according to an embodiment of the present application;
FIG. 11 is a schematic diagram of a fifth metal layer in a pixel layout according to an embodiment of the present application;
fig. 12 is a schematic diagram of a stacked structure of a first semiconductor layer to a first metal layer in a pixel layout according to an embodiment of the application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and description only, and is not intended to limit the application. In the present application, unless otherwise indicated, terms of orientation such as "upper" and "lower" are used to generally refer to the upper and lower positions of the device in actual use or operation, and specifically the orientation of the drawing figures; while "inner" and "outer" are for the outline of the device.
The embodiment of the application provides an array substrate, which comprises a plurality of pixels arranged in an array, wherein each pixel comprises a driving transistor, a data writing transistor, a reset transistor, a compensation transistor and a light-emitting element, the driving transistor and the data writing transistor are first-class transistors, and the reset transistor and the compensation transistor are second-class transistors;
the array substrate comprises a substrate, a first semiconductor layer, a first metal layer, a second semiconductor layer and a third metal layer which are arranged in a stacked manner from bottom to top, wherein the first semiconductor layer comprises an active layer of each first type transistor, and the second semiconductor layer comprises an active layer of each second type transistor;
the first metal layer comprises top grids of all first transistors, the second metal layer comprises a first main scanning line and a second main scanning line, the third metal layer comprises a first sub-scanning line and a second sub-scanning line, the first main scanning line comprises a bottom grid of a reset transistor, the first sub-scanning line comprises a top grid of the reset transistor, the second main scanning line comprises a bottom grid of a compensation transistor, and the second sub-scanning line comprises a top grid of the compensation transistor.
The embodiment of the application provides an array substrate and a display panel. The following will describe in detail. The following description of the embodiments is not intended to limit the preferred embodiments.
Embodiment 1,
Referring to fig. 1, fig. 2, fig. 3 and fig. 4, fig. 1 is a schematic diagram of an equivalent circuit of a pixel on an array substrate according to an embodiment of the present application, fig. 2 is a timing chart of an equivalent circuit of a pixel on an array substrate according to an embodiment of the present application, fig. 3 is a schematic diagram of a cross-sectional film structure of a pixel on an array substrate according to an embodiment of the present application, and fig. 4 is a schematic diagram of a layout of a pixel on an array substrate according to an embodiment of the present application.
The embodiment of the application provides an array substrate 100, which comprises a plurality of pixels 200 arranged in an array, wherein each pixel 200 comprises a driving transistor T1, a data writing transistor T2, a reset transistor T4, a compensation transistor T3 and a light emitting element OL, the driving transistor T1 and the data writing transistor T2 are of a first type, and the reset transistor T4 and the compensation transistor T3 are of a second type;
the array substrate 100 includes a base 11, a first semiconductor layer 13, a first metal layer 15, a second metal layer 17, a second semiconductor layer 19, and a third metal layer 21 stacked from bottom to top, the first semiconductor layer 13 including active layers of transistors of the first type, and the second semiconductor layer 19 including active layers of transistors of the second type;
wherein the first metal layer 15 includes top gates of the first type transistors, the second metal layer 17 includes a first main scanning line Sn (11) and a second main scanning line Sn (vt 1), the third metal layer 21 includes a first sub scanning line Sn (12) and a second sub scanning line Sn (vt 2), the first main scanning line Sn (11) includes a bottom gate of the reset transistor T4, the first sub scanning line Sn (12) includes a top gate of the reset transistor T4, the second main scanning line Sn (vt 1) includes a bottom gate of the compensation transistor T3, and the second sub scanning line Sn (vt 2) includes a top gate of the compensation transistor T3.
Further, in the array substrate 100 of some embodiments, the first type of transistors are polysilicon transistors and the second type of transistors are oxide transistors.
Further, in the array substrate 100 of some embodiments, the orthographic projection of the first main scan line Sn (11) on the base 11 and the orthographic projection of the first sub scan line Sn (12) on the base 11 at least partially overlap;
the orthographic projection of the second main scanning line Sn (vt 1) on the substrate 11 and the orthographic projection of the second sub scanning line Sn (vt 2) on the substrate 11 at least partially overlap.
Further, in the array substrate 100 of some embodiments, the active layer of the compensation transistor T3 and the active layer of the reset transistor T4 are of an integral structure connected to each other, and the material of the second semiconductor layer between the compensation transistor T3 and the reset transistor T4 is conductive.
Further, in the array substrate 100 of some embodiments, the array substrate further includes a storage capacitor Cst electrically connected to the driving transistor T1;
the first metal layer 15 includes a first capacitance electrode Cst11 of the storage capacitance Cst, and the second metal layer 17 includes a second capacitance electrode Cst12 of the storage capacitance Cst.
Further, in the array substrate 100 of some embodiments, a fourth metal layer 23 disposed on a side of the third metal layer 21 away from the substrate 11 is further included, and the fourth metal layer 23 includes a Data line Data and a first power line VDD1.
Further, in some embodiments of the array substrate 100, the fifth metal layer 25 is further included on a side of the fourth metal layer 23 away from the substrate 11, the fifth metal layer 25 includes a second power line VDD2, the second power line VDD2 is electrically connected to the first power line VDD1, the extending direction of the second power line VDD2 is the same as the extending direction of the first power line VDD1, and the orthographic projection of the second power line VDD2 on the substrate 11 at least partially overlaps with the orthographic projection of the first power line VDD1 on the substrate 11.
Further, in the array substrate 100 of some embodiments, the second power line VDD2 further includes a protrusion 301, and the front projection of the protrusion 301 on the substrate 11 covers the front projections of the driving transistor T1, the compensating transistor T3 and the reset transistor T4 on the substrate 11.
Further, in the array substrate 100 of some embodiments, the pixel further includes: the reset transistor T7, the first light emission control transistor T5, and the second light emission control transistor T6 are first-type transistors.
The structure and connection relation of the above-described embodiments are further described below.
Referring to fig. 3 and 4, the pixels 200 are disposed on the array substrate 100, and the layer structure of the array substrate 100 may include, but is not limited to, the following number and sequence of layers: a substrate 11; a buffer layer 12 provided on the substrate 11, a first semiconductor layer 13 provided on the buffer layer 12; a first gate insulating layer 14 provided on the first semiconductor layer 13; a first metal layer 15 provided on the first gate insulating layer 14; a capacitance insulating layer 16 provided on the first metal layer 15; a second metal layer 17 provided on the capacitance insulating layer 16; a second gate insulating layer 18 provided on the second metal layer 17; a second semiconductor layer 19 provided on the second gate insulating layer 18; a third gate insulating layer 20 provided on the second semiconductor layer 19; a third metal layer 21 provided on the third gate insulating layer 20; an interlayer insulating layer 22 provided on the third metal layer 21; a fourth metal layer 23 provided on the interlayer insulating layer 22; a first planarization layer 24 disposed on the fourth metal layer 23; a fifth metal layer 25 provided on the first planarization layer 24; a second planarization layer 26 disposed on the fifth metal layer 25; an anode 27 provided on the second flat layer; a pixel defining layer 28 provided on the anode 27.
Referring to fig. 3, fig. 4, fig. 5, fig. 6, fig. 7, fig. 8, fig. 9, fig. 10, fig. 11, fig. 12, fig. 5 is a schematic diagram of a first metal layer in a pixel layout provided by an embodiment of the present application, fig. 6 is a schematic diagram of a first metal layer in a pixel layout provided by an embodiment of the present application, fig. 7 is a schematic diagram of a second metal layer in a pixel layout provided by an embodiment of the present application, fig. 8 is a schematic diagram of a second metal layer in a pixel layout provided by an embodiment of the present application, fig. 9 is a schematic diagram of a third metal layer in a pixel layout provided by an embodiment of the present application, fig. 10 is a schematic diagram of a fourth metal layer in a pixel layout provided by an embodiment of the present application, fig. 11 is a schematic diagram of a fifth metal layer in a pixel layout provided by an embodiment of the present application, and fig. 12 is a schematic diagram of a stack structure of the first semiconductor layer to the first metal layer in a pixel layout provided by an embodiment of the present application.
Referring to fig. 3, 4, 5, and 12, the first semiconductor layer 13 includes an active layer T1B, a source T1S, and a drain T1D of the driving transistor T1, the first semiconductor layer 13 includes an active layer T2B, a source T2S, and a drain T2D of the data writing transistor T2, the first semiconductor layer 13 includes an active layer T5B, a source T5S, and a drain T5D of the first light emitting control transistor T5, the first semiconductor layer 13 includes an active layer T6B, a source T6S, and a drain T6D of the second light emitting control transistor T6, the first semiconductor layer 13 includes an active layer T7B, a source T7S, and a drain T7D of the reset transistor T7, the active layers of the respective transistors are connected to each other, and a material of the first semiconductor layer between the different transistors is electrically connected to serve as a track or electrode of the source or the drain. That is, the first semiconductor layer 13 includes an active layer of each first-type transistor.
Specifically, the first type of transistor is a polysilicon transistor, and a polysilicon material is used as a semiconductor layer, such as Low Temperature Polysilicon (LTPS).
Specifically, the reset signal sources may include a first reset signal source VI1 and a second reset signal source VI2, the first semiconductor layer 13 includes a second reset signal source VI12, and the first semiconductor layer 13 includes a second reset signal source VI12 formed by being conductive.
Referring to fig. 3, 4, 6 and 12, the first metal layer 15 includes a third scan line Sn (d), a fourth scan line Sn (x), a light emission control signal line EM, and a gate T1G of the driving transistor T1, wherein a gate T2G of the data writing transistor T2 is a portion of the third scan line Sn (d), a gate T7G of the reset transistor T7 is a portion of the fourth scan line Sn (x), a gate T5G of the first light emission control transistor T5 and a gate T6G of the second light emission control transistor T6 are portions of the light emission control signal line EM, and the gate T1G of the driving transistor T1 is multiplexed as the first capacitor electrode C11 of the storage capacitor Cst. That is, the first metal layer 15 is patterned to form the top gate of the first type transistor.
Referring to fig. 3, 4 and 7, the second metal layer 17 includes a trace of the reset signal source VI, a first main scanning line Sn (11), a second main scanning line Sn (vt 1), a second capacitor electrode C12 of the storage capacitor Cst, a bottom gate T4G1 of the reset transistor T4 is a portion of the first main scanning line Sn (11), and a bottom gate T3G1 of the compensation transistor T3 is a portion of the second main scanning line Sn (vt 1). That is, the second metal layer 17 is patterned to form the bottom gates of the second type of transistor.
Specifically, the reset signal source VI may include a first reset signal source VI1 and a second reset signal source VI2, the second metal layer 17 includes a first reset signal source VI11, the first semiconductor layer 13 includes a second reset signal source VI12, and by setting the second reset signal source VI12, the impedance of the reset signal source VI may be reduced, so that the potential uniformity of the reset signal source VI in each pixel may be improved.
Referring to fig. 3, 4 and 8, the second semiconductor layer 19 includes an active layer T3B, a source T3S and a drain T3D of the compensation transistor T3, and the second semiconductor layer 19 includes an active layer T4B, a source T4S and a drain T4D of the reset transistor T4. That is, the second semiconductor layer 19 is patterned to form the active layers of the respective second type transistors.
Specifically, the second type of transistor is an oxide transistor, and a metal oxide is used as a semiconductor material, for example, IGZO (indium gallium zinc oxide) material.
Specifically, the active layer of the compensation transistor T3 and the active layer of the reset transistor T4 are of an integrated structure in which the active layers are connected to each other, the material of the second semiconductor layer between the compensation transistor T3 and the reset transistor T4 is made conductive, the portion of the second semiconductor layer that is made conductive serves as the source T3S and the drain T3D of the compensation transistor T3, and the source T4S and the drain T4D of the reset transistor T4, and no additional metal layer is required to be manufactured to serve as the source and the drain of the second transistor, so that the complexity of the layer structure of the array substrate 100 can be reduced and the manufacturing process can be simplified.
Referring to fig. 3, 4 and 9, the third metal layer 21 includes a first scan line Sn (12) and a second scan line Sn (vt 2), the top gate T4G2 of the reset transistor T4 is a portion of the first scan line Sn (12), and the top gate T3G2 of the compensation transistor T3 is a portion of the second scan line Sn (vt 2). That is, the third metal layer 21 is patterned to form the top gate of the second type transistor.
Specifically, in the pixel of polysilicon, the leakage current of the polysilicon thin film transistor is larger, especially, the gate voltage is unstable due to the larger leakage current during low-frequency display, so that the potential difference between the gate and the source is unstable, the current of the OLED light emitting element is unstable, and the display panel has a flicker phenomenon.
Specifically, the front projection of the first main scan line Sn (11) on the substrate 11 and the front projection of the first scan line Sn (12) on the substrate 11 at least partially overlap, that is, the bottom gate T3G1 and the top gate T3G2 of the compensation transistor T3 at least partially overlap, and the double-gate overlapping portions of the compensation transistor T3 jointly play a role in simultaneously turning on and off the compensation transistor T3, so that mobility of the compensation transistor T3 in the on state can be improved, and leakage current of the compensation transistor T3 in the off state can be reduced. The front projection of the second main scan line Sn (vt 1) on the substrate 11 and the front projection of the second sub scan line Sn (vt 2) on the substrate 11 are at least partially overlapped, that is, the bottom gate T4G1 and the top gate T4G2 of the reset transistor T4 are at least partially overlapped, and the double-gate overlapped portions of the reset transistor T4 jointly play a role of simultaneously turning on and off the reset transistor T4, so that mobility of the reset transistor T4 in an on state can be improved, and leakage current of the reset transistor T4 in an off state can be reduced.
Referring to fig. 3, 4 and 10, the fourth metal layer 23 includes a Data line Data, a first power line VDD1, a first connection electrode 201, a second connection electrode 202, a third connection electrode 203 and a fourth connection electrode 204, where the first connection electrode 201, the second connection electrode 202, the third connection electrode 203 and the fourth connection electrode 204 serve as bridging electrodes for transferring signals, and are specifically connected to other layers through various vias described later.
Referring to fig. 3, 4, and 11, the fifth metal layer 25 includes a second power line VDD2, where the second power line VDD2 is electrically connected to the first power line VDD1 and supplies the same signal, so that the voltage drop (IRDrop) on the first power line VDD1 can be reduced to the maximum, and the uniformity and stability of the voltage on the first power line VDD1 on the whole array substrate 100 can be improved, thereby improving the display quality.
Specifically, the second power line VDD2 further includes a protrusion 301, where the front projection of the protrusion 301 on the substrate 11 covers the front projection of the driving transistor T1, the compensating transistor T3, and the reset transistor T4 on the substrate 11, that is, the protrusion 301 of the second power line VDD2 plays a role in shielding the driving transistor T1, the compensating transistor T3, and the reset transistor T4, so as to avoid that the working stability of the driving transistor T1, the compensating transistor T3, and the reset transistor T4 is affected by the electrodes of the light emitting element OL above the protrusion 301 through the capacitive coupling, and the protrusion 301 can also play a role in shielding the storage capacitor Cst, so that the voltage stability of the storage capacitor Cst is prevented from being affected by the electrodes of the light emitting element OL above the protrusion 301 through the capacitive coupling, and the voltage stability of the storage capacitor Cst is prevented from being improved by the protrusion 301, so as to avoid the flicker phenomenon of the display panel.
Specifically, the second power line VDD2 is electrically connected to the first power line VDD1, the extending direction of the second power line VDD2 is the same as the extending direction of the first power line VDD1, the front projection of the second power line VDD2 on the substrate 11 and the front projection of the first power line VDD1 on the substrate 11 are at least partially overlapped, and since the second power line VDD2 is electrically connected to the first power line VDD1 and supplies the same electrical signal, after the front projection of the second power line VDD2 on the substrate 11 and the front projection of the first power line VDD1 on the substrate 11 are overlapped, the space occupied by the second power line VDD2 and the first power line VDD1 on the layout (layout) can be reduced, and the pixel resolution of the array substrate 100 can be improved.
The connection relation of the transistors is described in detail below.
The array substrate 100 provided in the embodiment of the application includes pixels 200 arranged in an array, the pixels 200 include a pixel circuit and a light emitting element OL, a first electrode of the light emitting element OL is electrically connected to a first power line VDD1, a second electrode of the light emitting element OL is electrically connected to a third power line VSS, the pixel circuit is coupled between the first power line VDD1 and the first electrode of the light emitting element OL, and the pixel circuit includes a driving transistor T1, a data writing transistor T2, a storage capacitor Cst, a compensation transistor T3, a reset transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, and a reset transistor T7.
The grid electrode T1G of the driving transistor T1 is electrically connected with the first node A, the source electrode T1S of the driving transistor T1 is electrically connected with the second node B, and the drain electrode T1D of the driving transistor T1 is electrically connected with the third node C;
the grid electrode T2G of the Data writing transistor T2 is electrically connected with the third scanning line Sn (D), the source electrode T2S of the Data writing transistor T2 is electrically connected with the Data line Data, and the drain electrode T2D of the Data writing transistor T2 is electrically connected with the second node B;
the storage capacitor Cst includes a first capacitor electrode C11 and a second capacitor electrode C12, the second capacitor electrode C12 is electrically connected to the first power line VDD1, and the first capacitor electrode C11 is electrically connected to the first node a;
a reset transistor T4, a gate T4G of the reset transistor T4 is electrically connected to a first scan line Sn, a source T4S of the reset transistor T4 is electrically connected to a first node a, a drain T4D of the reset transistor T4 is electrically connected to a reset signal source VI, and the first scan line Sn includes a first main scan line Sn (11) and a first sub scan line Sn (12);
a compensation transistor T3, a gate T3G of the compensation transistor T3 is electrically connected to the second scan line Sn (vt), a source T3S of the compensation transistor T3 is electrically connected to the third node C, a drain T3D of the compensation transistor T3 is electrically connected to the first node a, the second scan line Sn (vt) includes a second main scan line Sn (vt 1) and a second sub scan line Sn (vt 2), the second main scan line Sn (vt 1) and the second sub scan line Sn (vt 2) are electrically connected within the pixel 200 or outside the pixel 200, and the second main scan line Sn (vt 1) and the second sub scan line Sn (vt 2) may be electrically connected outside the pixel 200 in a non-display area of the array substrate 100;
a reset transistor T7, a gate T7G of the reset transistor T7 is electrically connected to the fourth scan line Sn (x), a source T7S of the reset transistor T7 is electrically connected to the reset signal source VI, a drain T7D of the reset transistor T7 is electrically connected to a first electrode of the light emitting element OL, the first electrode of the light emitting element OL may be an anode of the light emitting element, a second electrode of the light emitting element OL may be a cathode, and the reset signal source VI may include one or both of the first reset signal source VI1 and the second reset signal source VI 2;
a first light emitting control transistor T5, a gate T5G of the first light emitting control transistor T5 is electrically connected to the light emitting control signal line EM, a source T5S of the first light emitting control transistor T5 is electrically connected to the first power line VDD1, and a drain T5D of the first light emitting control transistor T5 is electrically connected to the second node B;
the second light-emitting control transistor T6, the gate T6G of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal line EM, the source T6S of the second light-emitting control transistor T6 is electrically connected to the third node C, and the drain T6D of the second light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting element OL.
The second electrode of the light emitting element OL is electrically connected to the third power source VSS.
Referring to fig. 1, 2 and 3, the operation of the pixel 200 of the above embodiment is further described below.
In the reset phase T1, the signals of the first scan line Sn and the third scan line Sn (d) are at high potential, the signals of the second scan line Sn (vt), the fourth scan line Sn (x), and the light emission control signal line EM are at low potential, the driving transistor T1, the data writing transistor T2, the compensation transistor T3, the reset transistor T7, the first light emission control transistor T5, the second light emission control transistor T6 are turned off, the reset transistor T4, the reset transistor T7 are turned on, and the reset signal source VI supplies the first node a and the first electrode of the light emitting element OL with reset signals.
In the Data writing stage T2, the signals of the first scan line Sn, the third scan line Sn (D), and the emission control signal line EM are low, the signals of the second scan line Sn (vt) and the fourth scan line Sn (x) are high, the compensation transistor T3 is turned on, the gate T1G and the drain T1D of the driving transistor T1 are turned on, a voltage difference is generated between the gate T1G and the source T1S of the driving transistor T1 by the threshold voltage of the driving transistor T1, at this time, the driving transistor T1 is turned on, the Data writing transistor T2 is turned on, the Data signal of the Data line Data is input to the second node B, and the Data signal of the Data line Data includes the compensated threshold voltage and is input to the gate T1G of the driving transistor T1, thereby compensating for the threshold voltage deviation of the driving transistor T1. The Data signal of the written Data line Data charges the first node a through the driving transistor T1 until the voltage of the first node a becomes Vdata-Vth, and the driving transistor T1 is turned off.
In the light emission stage T3, the signal of the first scanning line Sn and the signal of the second scanning line Sn (vt) are at low potential, the signal of the third scanning line Sn (d) and the signal of the fourth scanning line Sn (x) are at high potential, the signal of the light emission control signal line EM is at high potential, the data writing transistor T2, the compensation transistor T3, the reset transistor T4, and the reset transistor T7 are turned off, the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, the driving transistor T1 is kept in an on state, the signal of the first power supply VDD flows to the light emitting element OL, and at this time, the light emitting element OL emits light.
The structure and connection relation of the above-described embodiments are further described below.
Fig. 1, 2 and 4 are combined. The array substrate 100 includes a first Via hole Via1, a second Via hole Via2, a third Via hole Via3, a fourth Via hole Via4, and a fifth Via hole Via5. The second metal layer 17 is connected to the fourth metal layer 23 Via the first Via1, the fourth metal layer 23 is connected to the first semiconductor layer 13 Via the second Via2, the fourth metal layer 23 is connected to the second semiconductor layer 19 Via the third Via3, the fourth metal layer 23 is connected to the first metal layer 15 through a fourth Via4, and the fifth metal layer 25 is connected to the fourth metal layer 23 through a fifth Via5. The first connection electrode 201, the second connection electrode 202, the third connection electrode 203, and the fourth connection electrode 204 are connected to corresponding wirings or electrodes of other layers through corresponding vias.
In the embodiment of the application, the leakage current of the polysilicon thin film transistor is larger, especially, the gate voltage is unstable due to the larger leakage current in low-frequency display, so that the potential difference between the gate and the source is unstable, the current of the OLED light-emitting element is unstable, and the display panel has a flicker phenomenon.
Embodiment II,
The embodiment of the present application further provides a display panel, including the array substrate 100 according to any one of the above embodiments, where the array substrate 100 further includes a pixel defining layer 28, the light emitting element OL is disposed in an opening of the pixel defining layer 28, and the display panel further includes an encapsulation layer disposed on the light emitting element OL.
The above describes in detail an array substrate and a display panel provided by the embodiments of the present application, and specific examples are applied to describe the principles and embodiments of the present application, and the description of the above embodiments is only for helping to understand the method and core ideas of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application.
Claims (9)
1. The array substrate is characterized by comprising a plurality of pixels arranged in an array, wherein each pixel comprises a driving transistor, a data writing transistor, a reset transistor, a compensation transistor and a light emitting element, the driving transistor and the data writing transistor are of a first type, and the reset transistor and the compensation transistor are of a second type;
the array substrate comprises a base, a first semiconductor layer, a first metal layer, a second semiconductor layer and a third metal layer which are arranged in a stacked manner from bottom to top, wherein the first semiconductor layer comprises an active layer of each first type transistor, and the second semiconductor layer comprises an active layer of each second type transistor;
the first metal layer comprises top gates of the first transistors, the second metal layer comprises a first main scanning line and a second main scanning line, the third metal layer comprises a first sub-scanning line and a second sub-scanning line, the first main scanning line comprises a bottom gate of the reset transistor, the first sub-scanning line comprises a top gate of the reset transistor, the second main scanning line comprises a bottom gate of the compensation transistor, and the second sub-scanning line comprises a top gate of the compensation transistor;
the first type transistor is a polysilicon transistor, and the second type transistor is an oxide transistor.
2. The array substrate of claim 1, wherein the orthographic projection of the first main scan line on the base and the orthographic projection of the first sub scan line on the base at least partially overlap;
the orthographic projection of the second main scanning line on the substrate and the orthographic projection of the second sub scanning line on the substrate are at least partially overlapped.
3. The array substrate of claim 2, wherein an active layer of the compensation transistor and an active layer of the reset transistor are of an integrated structure connected to each other, and a material of the second semiconductor layer between the compensation transistor and the reset transistor is conductive.
4. The array substrate of claim 3, further comprising a storage capacitor electrically connected to the drive transistor;
the first metal layer includes a first capacitance electrode of a storage capacitance, and the second metal layer includes a second capacitance electrode of the storage capacitance.
5. The array substrate of claim 4, further comprising a fourth metal layer disposed on a side of the third metal layer away from the base, the fourth metal layer including a data line and a first power line.
6. The array substrate of claim 5, further comprising a fifth metal layer disposed on a side of the fourth metal layer away from the substrate, the fifth metal layer including a second power line, the second power line being electrically connected to the first power line, the second power line extending in a same direction as the first power line, an orthographic projection of the second power line on the substrate at least partially overlapping an orthographic projection of the first power line on the substrate.
7. The array substrate of claim 6, wherein the second power line further comprises a protrusion, and an orthographic projection of the protrusion on the substrate covers orthographic projections of the driving transistor, the compensation transistor, and the reset transistor on the substrate.
8. The array substrate of claim 7, wherein the pixel further comprises:
the light emitting diode comprises a reset transistor, a first light emitting control transistor and a second light emitting control transistor, wherein the reset transistor, the first light emitting control transistor and the second light emitting control transistor are of a first type.
9. A display panel comprising the array substrate according to any one of claims 1 to 8, further comprising a pixel defining layer, wherein the light emitting element is disposed in an opening of the pixel defining layer, and further comprising an encapsulation layer disposed on the light emitting element.
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