CN113690300B - Transistor with local bottom gate and manufacturing method thereof - Google Patents

Transistor with local bottom gate and manufacturing method thereof Download PDF

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CN113690300B
CN113690300B CN202110793111.2A CN202110793111A CN113690300B CN 113690300 B CN113690300 B CN 113690300B CN 202110793111 A CN202110793111 A CN 202110793111A CN 113690300 B CN113690300 B CN 113690300B
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gate dielectric
oxide
substrate
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CN113690300A (en
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许海涛
高宁飞
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Beijing Hua Tan Yuan Xin Electronics Technology Co Ltd
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Beijing Hua Tan Yuan Xin Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02192—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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Abstract

The invention relates to a transistor of local bottom gate and its preparation method, this transistor includes the substrate, low-dimensional semiconductor layer, source electrode, drain electrode and local bottom gate, the local bottom gate locates on above-mentioned substrate, there is a gate dielectric layer on the local bottom gate, the low-dimensional semiconductor layer locates on above-mentioned gate dielectric layer as the channel of the transistor device, source electrode and drain electrode locate at the opposite sides of the low-dimensional semiconductor channel, and contact with one or more parts of the above-mentioned low-dimensional semiconductor layer separately; the source electrode, the drain electrode and the channel layer are provided with a transition layer and an electrostatic doping layer, and fixed charges are arranged in the electrostatic doping layer, so that the corresponding low-dimensional semiconductor channel layer is subjected to electrostatic doping to form an NMOS device, and meanwhile, the manufacturing method of the transistor is also provided. The transistor has the advantages of good thermal stability, accurate and controllable threshold voltage, and compatibility in process, and can meet the requirements of large-scale carbon-based integrated circuit production.

Description

Transistor with local bottom gate and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor devices, in particular to a transistor with a local bottom gate and a preparation method thereof.
Background
Low-dimensional semiconductor materials, such as carbon nanotubes, graphene, black phosphorus, or two-dimensional materials, have been widely used as channel materials in transistors because of their excellent properties such as thin thickness, high mobility, high physical and chemical stability, and high thermal conductivity. Similar to the conventional semiconductor process, the transistor with the low-dimensional material as the channel can also change the electric property of the semiconductor channel material by doping the low-dimensional material to change the distribution of carriers in the semiconductor channel material, and respectively form a p-type region and an n-type region, thereby forming semiconductor devices with various structural functions, such as diodes, field effect transistors and the like. However, the low-dimensional semiconductor forbidden band width is generally smaller than that of silicon, wherein the typical band gap of the carbon nano tube is about 0.5eV, and the corresponding band gap of the silicon is about 1.12eV. Because the band gap is narrower, the width of the tunneling barrier between the drain end bands in the off state is greatly compressed, larger tunneling current is generated, and the static energy consumption is influenced. The off-state tunneling effect of the corresponding transistor is more remarkable than that of a silicon-based transistor, and in the existing undoped MOS structure, the electric field at the drain end is too concentrated and too strong to cause the schottky barrier near the biased drain end of the channel to be too thin, so that the schottky tunneling is serious.
Due to the specificity of low-dimensional semiconductor materials, doping channel materials by conventional thermal diffusion and ion implantation tends to cause various problems. For example, low-dimensional materials are more susceptible to the environment, so thermal diffusion or ion implantation is difficult to form uniform and reliable doping, and damage to the low-dimensional material is easily caused during doping. Meanwhile, the channel thickness of the low-dimensional material is extremely thin, generally a single atomic layer or a plurality of atomic layers, effective doping in the channel is difficult to achieve through a traditional impurity ion doping method, and impurity ions are more likely to be distributed in an insulating substrate. And partial low-dimensional materials such as carbon nanotubes and graphene have stable chemical properties, strong interatomic chemical bond energy and no dangling bond on the surface, and doped impurity ions are difficult to form a stable structure by bonding with carbon atoms, but tend to exist in an unstable weak interaction mode (such as surface adsorption) so as to cause unstable doping effect. In addition, the traditional doping mode generally needs to be annealed at a high temperature of more than 1000 ℃ to repair lattice damage caused by the doping process. Most low dimensional materials cannot withstand the above temperatures, and the high temperature annealing process also limits the compatibility of the device fabrication process. Therefore, the low-dimensional semiconductor material transistor cannot realize the light doped source drain (LDD) of the silicon-based transistor to finely regulate the distribution of the drain doping concentration in space, thereby reducing the negative effects such as short channel effect, junction leakage current, parasitic current and the like. However, the low-dimensional semiconductor material is easier to realize electrostatic regulation than bulk semiconductor materials due to the ultra-thin channel characteristics and limited carrier concentration (compared with bulk semiconductor materials), and the contact characteristics of the low-dimensional semiconductor material and the metal semiconductor are different from those of the traditional semiconductor, for example, the contact of the carbon nano tube and certain metals does not observe obvious Fermi pinning effect.
The PMOS or NMOS can be realized by selecting a metal material matching the work function of the channel material as a source/drain instead of doping the channel material, or a device structure with a bottom gate is adopted, and the above problems are solved by depositing a material layer with fixed charges on the surface of the channel and performing electrostatic doping on the channel. The source and drain electrodes are formed by selecting a metal material matched with the work function of the channel material, effective injection of electrons (NMOS) or holes (PMOS) can be performed in an on state, the on and off of the transistor is controlled by regulating and controlling the band bending in the channel through the grid electrode, the whole channel can be subjected to electrostatic doping by depositing a material layer with fixed charges on the surface of the channel, and further, the band bending between the source and drain electrodes and the grid electrode is regulated, so that barrier-free injection or tunneling injection of carriers is realized. However, the low-dimensional material transistor prepared by the two modes still has more problems, taking a carbon nanotube transistor as an example, and adopting a metal material with matched metal work functions to form a high-k dielectric transistor prepared by a source and a drain, the threshold voltage can not be effectively regulated and controlled, reverse tunneling is easy to occur at the drain end in the off state, and the switching ratio is reduced. The transistor prepared by combining the local bottom gate with the channel surface electrostatic doping or adopting the gate dielectric oxide electrostatic doping mode is adopted, the electrostatic doping is usually realized by using metal oxides with incomplete proportion (namely more oxygen vacancies or dangling bonds and the like), the interface is unstable, a plurality of defect states and interface states exist, the channel mobility is reduced, the gate control is not facilitated, the uniformity of the device is affected, and the process repeatability is poor.
Therefore, there is a need to develop an effective doping technology based on a low-dimensional semiconductor material, so that the critical index of a transistor based on the low-dimensional material can simultaneously meet requirements, such as on-state and off-state current, threshold voltage, gate control capability, device reliability, thermal stability and the like, and meanwhile, the process has certain compatibility, so that the requirement of large-scale carbon-based integrated circuit production can be met.
Disclosure of Invention
The present invention is directed to the above problems in the prior art, and proposes a transistor with a local bottom gate and a method for manufacturing the same by using a dielectric material capable of directly forming a fixed charge therein as an electrostatic doped layer, where the technical solution of the embodiment of the first aspect of the present invention is as follows:
A transistor comprises a substrate, a local bottom gate, a gate dielectric layer, a low-dimensional semiconductor layer, a source electrode and a drain electrode, and comprises the following schemes: the local bottom gate is embedded in the substrate and is in the same plane with the substrate or is positioned on the substrate;
A gate dielectric layer is arranged on the local bottom gate, and a low-dimensional semiconductor layer is arranged on the gate dielectric layer and is used as a channel of the transistor device;
the source electrode and the drain electrode are positioned on two opposite sides of the channel and respectively form one or more partial contacts with the low-dimensional semiconductor layer;
the channel has a transition layer and an electrostatic doped layer, and a fixed charge is formed in the electrostatic doped layer.
In an embodiment of the first aspect of the present invention, the substrate includes at least one of a SiO 2/Si substrate, a quartz substrate, an Al 2O3 substrate, a glass substrate, or a polymer substrate.
In an embodiment of the first aspect of the present invention, the low-dimensional semiconductor layer includes at least one of a carbon nanotube, a silicon nanowire, a group II-VI element nanowire, a group III-V element nanowire, or a two-dimensional layered semiconductor material, and the carbon nanotube is further preferably a single-walled carbon nanotube, a multi-walled carbon nanotube, a network-like carbon nanotube, or a carbon nanotube array, and the two-dimensional layered semiconductor material is further preferably black phosphorus or molybdenum disulfide.
In an embodiment of the first aspect of the present invention, the local bottom gate is at least one selected from tantalum nitride (TaN), titanium nitride (TiN), polysilicon, gold (Au), palladium (Pd), platinum (Pt), titanium/gold stack (Ti/Au), titanium/palladium stack (Ti/Pd), or titanium/platinum stack (Ti/Pt).
In an embodiment of the first aspect of the present invention, the source electrode and the drain electrode are at least one selected from platinum (Pt), titanium (Ti) or palladium (Pd), and preferably palladium (Pd).
In an embodiment of the first aspect of the present invention, a first gate dielectric sub-layer is provided between the local bottom gate and the gate dielectric layer, and a second gate dielectric sub-layer is provided between the gate dielectric layer and the low-dimensional semiconductor layer, where the first gate dielectric sub-layer and the second gate dielectric sub-layer are made of the same or different materials. The first gate dielectric sub-layer, the gate dielectric layer and the second gate dielectric sub-layer together function as a gate dielectric.
Further, the first gate dielectric sub-layer and the second gate dielectric sub-layer include at least one of aluminum oxide (Al 2O3), aluminum nitride (AlN), hafnium oxide (HfO 2), zirconium oxide (ZrO 2), titanium oxide (TiO 2), hafnium oxynitride (HfO xNy), lanthanum oxynitride (LaO xNy), yttrium oxide (Y 2O3), or lanthanum oxide (La 2O3).
In an embodiment of the first aspect of the present invention, the electrostatic doped layer is a metal oxide or nitride, preferably aluminum oxide, hafnium oxide, aluminum nitride, and further preferably aluminum nitride.
In an embodiment of the first aspect of the present invention, a protective layer is provided on the electrostatically doped layer.
In an embodiment of the first aspect of the present invention, a transition layer is provided between the electrostatic doped layer and the low-dimensional semiconductor layer.
An embodiment of the first aspect of the present invention provides a method for manufacturing the transistor, which specifically includes the following steps:
S1, providing a substrate, and forming a local bottom gate on the substrate;
S2, forming a gate dielectric layer on the local bottom gate;
s3, forming a low-dimensional semiconductor layer on the gate dielectric layer;
S4, forming a source electrode and a drain electrode on two opposite sides of the low-dimensional semiconductor layer, and exposing part of the low-dimensional semiconductor layer to serve as a channel layer of the transistor;
And S5, further forming a transition layer and an electrostatic doping layer on the channel layer, wherein the electrostatic doping layer is provided with fixed charges.
In an embodiment of the second aspect of the present invention, the substrate is selected from the group consisting of a SiO 2/Si substrate, a quartz substrate, an Al 2O3 substrate, a glass substrate, and a polymer substrate, and the operation of performing a pretreatment on the surface of the substrate, the pretreatment including at least one of a plasma treatment, an annealing treatment, a wet chemical cleaning, and a surface molecular modification, is further included before the formation of the low-dimensional material layer.
In an embodiment of the second aspect of the present invention, the low-dimensional semiconductor layer includes at least one of a carbon nanotube, a silicon nanowire, a group II-VI element nanowire, a group III-V element nanowire, or a two-dimensional layered semiconductor material, and the carbon nanotube is further preferably a single-walled carbon nanotube, a multi-walled carbon nanotube, a network-like carbon nanotube, or a carbon nanotube array, and the two-dimensional layered semiconductor material is further preferably black phosphorus or molybdenum disulfide.
In an embodiment of the second aspect of the present invention, the local bottom gate includes at least one of tantalum nitride (TaN), titanium nitride (TiN), polysilicon, gold (Au), palladium (Pd), platinum (Pt), titanium/gold stack (Ti/Au), titanium/palladium stack (Ti/Pd), or titanium/platinum stack (Ti/Pt).
In an embodiment of the second aspect of the present invention, the source electrode and the drain electrode include at least one of platinum (Pt), titanium (Ti) or palladium (Pd), and preferably palladium (Pd).
In an embodiment of the second aspect of the present invention, a first gate dielectric sub-layer is formed after the local bottom gate is formed, the gate dielectric layer is formed on the first gate dielectric sub-layer, and a second gate dielectric sub-layer is further formed on the gate dielectric layer, where materials of the first gate dielectric sub-layer and the second gate dielectric sub-layer are the same or different.
In an embodiment of the second aspect of the present invention, the first gate dielectric sublayer and the second gate dielectric sublayer comprise at least one of aluminum oxide (Al 2O3), aluminum nitride (AlN), hafnium oxide (HfO 2), zirconium oxide (ZrO 2), titanium oxide (TiO 2), hafnium oxynitride (HfO xNy), lanthanum oxynitride (LaO xNy), yttrium oxide (Y 2O3), or lanthanum oxide (La 2O3), and further preferably yttrium oxide.
In an embodiment of the second aspect of the present invention, the electrostatic doped layer is a metal oxide or nitride, including at least one of aluminum oxide, hafnium oxide, or aluminum nitride, and further preferably is aluminum nitride.
In an embodiment of the second aspect of the present invention, a transition layer is provided between the electrostatic doped layer and the low-dimensional semiconductor layer.
In an embodiment of the second aspect of the present invention, a protection layer is further formed on the electrostatic doped layer, and the protection layer may be selected from aluminum oxide or silicon nitride.
In an embodiment of the second aspect of the present invention, a transition layer is provided between the electrostatically doped layer and the low-dimensional semiconductor layer, and the transition layer is deposited in a non-plasma manner, for example, thermal atomic layer deposition or physical vapor deposition, and the transition layer includes at least one of aluminum oxide, yttrium oxide or hafnium oxide, and preferably yttrium oxide.
The embodiment of the third aspect of the invention also provides a manufacturing method of the complementary field effect transistor, which specifically comprises the following steps:
S1, providing a substrate, and forming a first local bottom gate and a second local bottom gate on the substrate, wherein the first local bottom gate and the second local bottom gate are respectively used as PMOS (P-channel metal oxide semiconductor) corresponding gates and NMOS (N-channel metal oxide semiconductor) corresponding gates;
s2, forming a gate dielectric layer on the first partial bottom gate and the second partial bottom gate;
s3, forming a low-dimensional semiconductor layer on the gate dielectric layer;
S4, forming a source electrode and a drain electrode on two opposite sides of the low-dimensional semiconductor layer corresponding to the first local bottom gate and the second local bottom gate respectively, and exposing part of the low-dimensional semiconductor layer to serve as channel layers of the PMOS and the NMOS respectively;
S5, further depositing a transition layer and an electrostatic doping layer on the structure formed in the step, wherein the electrostatic doping layer is provided with fixed charges;
S6, forming a first protection layer on the structure, filling the groove between the source electrode and the drain electrode with the dielectric medium, and flattening the groove;
s7, defining a window pattern of the semiconductor channel layer corresponding to the first local bottom gate on the surface of the dielectric formed after planarization, and carrying out dry etching on the first protective layer and the electrostatic doping layer by taking the transition layer as an etching stop layer;
and S8, further depositing a second protective layer in the groove formed after the etching, so as to form a PMOS corresponding to the first partial bottom gate and an NMOS corresponding to the second partial bottom gate, and further forming the nano complementary field effect transistor through an interconnection process.
In an embodiment of the third aspect of the present invention, a first gate dielectric sub-layer is formed after the first local bottom gate and the second local bottom gate are formed, the gate dielectric layer is formed on the first gate dielectric sub-layer, and a second gate dielectric sub-layer is further formed on the gate dielectric layer, where materials of the first gate dielectric sub-layer and the second gate dielectric sub-layer are the same or different.
In an embodiment of the third aspect of the present invention, the first gate dielectric sublayer and the second gate dielectric sublayer comprise at least one of aluminum oxide (Al 2O3), aluminum nitride (AlN), hafnium oxide (HfO 2), zirconium oxide (ZrO 2), titanium oxide (TiO 2), hafnium oxynitride (HfO xNy), lanthanum oxynitride (LaO xNy), yttrium oxide (Y 2O3), or lanthanum oxide (La 2O3), and further preferably yttrium oxide.
In an embodiment of the third aspect of the present invention, the electrostatic doped layer is a metal oxide or nitride, preferably at least one of aluminum oxide, hafnium oxide, or aluminum nitride, and further preferably aluminum nitride.
In an embodiment of the third aspect of the present invention, when the electrostatically doped layer is aluminum nitride, the NMOS threshold voltage is controlled by adjusting a process temperature of atomic layer deposition of aluminum nitride, where the process temperature is 200-400 ℃, preferably 220-300 ℃.
In an embodiment of the third aspect of the present invention, the first protective layer is preferably aluminum oxide or silicon nitride, and the second protective layer is preferably yttrium oxide.
The embodiment of the invention has the following beneficial effects:
According to the invention, a material capable of directly forming fixed charges is adopted as an electrostatic doping layer, and a high-k dielectric layer is adopted as a transition layer between the electrostatic doping layer and a channel layer, so that the high-k dielectric layer has better thermal stability, when the transition layer (107) and a second gate dielectric sub-layer (103') in a gate dielectric are made of the same material, for example, yttrium oxide, the device has better interface characteristics, and in addition, the transition layer can protect the channel layer, can be used as an etching stop layer in a subsequent process, has strong process compatibility, and can meet the requirements of large-scale carbon-based integrated circuit production.
Drawings
FIG. 1 is a schematic diagram of an embodiment of a gate-less dielectric transition layer transistor according to the present invention;
FIG. 2 is a schematic diagram of an embodiment of a transistor with a symmetric gate dielectric transition layer according to the present invention;
FIG. 3 is a schematic diagram of one embodiment of a transistor with raised local bottom gate of the present invention;
FIG. 4 is a schematic diagram of forming an embedded local bottom gate in one embodiment of the invention;
FIG. 5 is a schematic diagram of forming a gate dielectric layer according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of forming a low-dimensional semiconductor material layer and source/drain electrodes in accordance with one embodiment of the present invention;
FIG. 7 is a schematic diagram of forming a dielectric layer according to an embodiment of the present invention;
FIG. 8 is a schematic illustration of forming an electrostatically doped layer in one embodiment of the present invention;
FIG. 9 is a schematic diagram illustrating formation of a first passivation layer according to an embodiment of the present invention;
FIG. 10 is a schematic illustration of forming a mask pattern in one embodiment of the invention;
FIG. 11 is a schematic diagram of etching a first protective layer according to an embodiment of the invention;
FIG. 12 is a schematic diagram of etching an electrostatic doped layer in accordance with an embodiment of the present invention;
FIG. 13 is a schematic illustration of depositing a second protective layer in accordance with an embodiment of the invention;
FIG. 14 is a CV characterization of a transistor in one embodiment of the present invention;
FIG. 15 is an I-V representation of a transistor in an embodiment of the invention in which one dielectric layer is HfO 2;
FIG. 16 is an I-V representation of a transistor in an embodiment of the invention in which the dielectric layer is Y 2O3/HfO2;
FIG. 17 is an I-V representation of a transistor in an embodiment of the invention in which the dielectric layer is Y 2O3/HfO2/Y2O3;
FIG. 18 is an I-V characterization of a transistor in an embodiment of the invention in which the electrostatically doped layer is a Y 2O3/AlN stack;
FIG. 19 is a characterization of transistors I-V formed at different ALD growth temperatures for AlN.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the drawings, like elements are denoted by like reference numerals, and various parts thereof are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
The structure of the transistor with local bottom gate of this embodiment is shown in fig. 1, and the transistor includes a substrate 101 in which a local bottom gate 102 is embedded. In this embodiment, the substrate 101 is a silicon oxide substrate, and in other embodiments, the substrate 101 may be made of a hard insulating material such as quartz, glass, or alumina, or a high temperature resistant flexible insulating material such as PET (polyethylene terephthalate), PEN (polyethylene naphthalate), polyimide, or the like. In this embodiment, the local bottom gate is made of a titanium/gold (Ti/Au) laminated material, and in other embodiments, the local bottom gate may be selected from one or more alloys of titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), aluminum (A l), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), palladium (Pd), platinum (Pt), scandium (Sc), yttrium (Y), or erbium (Er).
The substrate with the local bottom gate 102 has the gate dielectric layer 103, in this embodiment, the gate dielectric layer 103 is hafnium oxide (HfO 2), and in other embodiments, the gate dielectric layer 103 may be a high-k dielectric such as aluminum oxide (Al 2O3), aluminum nitride (Al N), zirconium oxide (ZrO 2), titanium oxide (TiO 2), hafnium oxynitride (HfO xNy), lanthanum oxynitride (LaO xNy), yttrium oxide (Y 2O3), or lanthanum oxide (La 2O3).
Further, the gate dielectric layer 103 has a low-dimensional semiconductor material layer 104, and in this embodiment, the low-dimensional semiconductor material is a single-walled carbon nanotube material, and in other embodiments, the low-dimensional semiconductor material may be a multi-walled carbon nanotube, a network-like carbon nanotube or a carbon nanotube array. In addition, other low-dimensional semiconductor materials such as silicon nanowires, II-VI element nanowires, III-V element nanowires, two-dimensional layered semiconductor materials and the like can be adopted, wherein the two-dimensional layered semiconductor materials can be molybdenum disulfide, tungsten disulfide or black phosphorus.
In other embodiments, as shown in fig. 2, a first gate dielectric sub-layer 103 'may be provided between the gate dielectric 103 and the local bottom gate 102, and a second gate dielectric sub-layer 103″ may be provided between the gate dielectric 103 and the low-dimensional semiconductor material layer 104, where the first gate dielectric sub-layer 103' or the second gate dielectric sub-layer 103″ may be configured to improve the quality of the interface between the local bottom gate 102 and the gate dielectric 103 and between the gate dielectric 103 and the low-dimensional semiconductor material layer 104. The adoption of the first gate dielectric sublayer 103 '/gate dielectric 103/second gate dielectric sublayer 103' stack as a gate dielectric is advantageous in improving the on-off ratio of the device under the working condition compared with the adoption of the gate dielectric 103 alone as a gate dielectric, and the adoption of the stack gate dielectric layer is higher in quality and smaller in hysteresis. The materials of the first gate dielectric sublayer 103' and the second gate dielectric sublayer 103″ may be the same or different, and may include at least one of aluminum oxide (Al 2O3), aluminum nitride (AlN), hafnium oxide (HfO 2), zirconium oxide (ZrO 2), titanium oxide (TiO 2), hafnium oxynitride (HfO xNy), lanthanum oxynitride (LaO xNy), yttrium oxide (Y 2O3) or lanthanum oxide (La 2O3), and in the embodiment shown in fig. 2, both are yttrium oxide (Y 2O3) dielectric layers, so that the influence of electrostatic doping on the gate dielectric interface can be reduced by symmetrically disposing two yttrium oxide (Y 2O3) dielectric layers on both sides of the gate dielectric 103, and meanwhile, more precise control over the threshold voltage can be realized.
Further, the source 105 and the drain 106 are disposed on opposite sides of the low-dimensional semiconductor material layer 104, a channel region of the transistor is defined between the source 105 and the drain 106, a transition layer 107 and an electrostatic doped layer 108 are disposed on the channel region, and yttrium oxide (Y 2O3) is selected as the transition layer in this embodiment, so that on one hand, the transition layer 107 and the low-dimensional semiconductor layer 104 have better interface quality, which is beneficial to improving the performance and reliability of the device, and on the other hand, the layer can also be used as an etching barrier layer in the etching process when the electrostatic doped layer 108 is deposited, for example, the electrostatic doped layer is deposited by adopting a plasma process, so as to damage the low-dimensional semiconductor channel layer, and on the other hand, when other dielectric layers above yttrium oxide (Y 2O3) are removed in the subsequent process. The electrostatic doped layer 108 has a fixed charge, so that the low-dimensional semiconductor channel layer is doped, and the threshold voltage and the switching state are regulated. In this embodiment, the electrostatically doped layer 108 is an aluminum nitride (AlN) material. In other embodiments, the electrostatically doped layer 108 may also be aluminum oxide, organic molecules, or silicon nitride. By adopting the double-layer structure of the electrostatic doping layer and the transition layer with the protection function, the more stable electrostatic doping effect can be realized at the same time and the advantages in the preparation process are brought.
In another embodiment, as shown in fig. 3, a local bottom gate pattern is defined on a substrate 201 by a photolithography process, and instead of embedding the local bottom gate into the substrate in the previous embodiment, the local bottom gate 202 is directly formed on the local bottom gate pattern of the substrate 201, then a transition layer 203 and a gate dielectric layer 204 are formed on the local bottom gate 202, then a low-dimensional semiconductor material layer 205 is formed on the gate dielectric layer 204, and a source electrode 206 and a drain electrode 207 are formed on opposite sides thereof, respectively. And further a transition layer 208 and an electrostatically doped layer 209 are formed on the low-dimensional semiconductor material layer 205.
Fig. 14-18 are comparative experimental results of examples of the present invention. In fig. 14, the CV characteristics of different gate dielectrics according to the invention show that yttrium oxide/hafnium oxide/yttrium oxide is used as the gate dielectric, the gate dielectric has higher quality, smaller hysteresis, and better uniformity of the device. Figures 15-17 are respectively representative of embodiments I-V of the present invention employing different gate dielectrics, and by comparison, it can be seen that the devices have higher on-off ratios and better uniformity using the combination of Y 2O3/HfO2/Y2O3 dielectrics. FIG. 18 is an I-V characterization of an embodiment of the invention employing different electrostatically doped layers. It can be seen that the yttrium oxide and aluminum nitride laminated layer is adopted as the electrostatic doping layer, so that the electrostatic doping layer has more effective electrostatic doping, better interface characteristics with the channel layer and the gate dielectric layer, higher on-state current and better consistency are achieved. When aluminum nitride grows by adopting a plasma deposition process, such as a plasma enhanced atomic layer deposition Process (PEALD) or a radio frequency sputtering (RF-router) process, the transition layer yttrium oxide also plays a role of a protective layer, and prevents the carbon nanotubes from being damaged by the plasma process. FIG. 19 is a representation of transistors I-V formed by ALD depositing AlN at different temperatures to achieve threshold voltage regulation by adjusting the AlN growth temperature.
In another embodiment of the present invention, a method for fabricating a transistor with a local bottom gate is provided, and the method is described in detail below with reference to the accompanying drawings.
Step S1, as shown in FIG. 4, providing a silicon oxide substrate 101, defining a local bottom gate 102 pattern on the substrate 101 through a photolithography process, etching the silicon oxide substrate with the local bottom gate pattern to form a groove, depositing a titanium/gold (Ti/Au) metal stack in the groove to form a local bottom gate 102, and enabling the surface of the local bottom gate 102 to be in the same plane with the substrate 101. In other embodiments, the substrate may be made of a hard insulating material such as quartz, glass, or alumina, or a high temperature resistant flexible insulating material selected from PET (polyethylene terephthalate), PEN (polyethylene naphthalate), polyimide, or the like.
In another embodiment, after defining the local bottom gate pattern on the silicon oxide substrate, the local bottom gate 102 may also be formed directly by Atomic Layer Deposition (ALD) or Physical Vapor Deposition (PVD), where a step is formed between the local bottom gate and the substrate, and when a gate dielectric layer is grown subsequently, the deposition is preferably performed by Atomic Layer Deposition (ALD), so as to enhance the cladding of the step.
In step S2, as shown in FIG. 5, a layer of dielectric is deposited on the local bottom gate 102 as a gate dielectric layer 103, which may be obtained by Atomic Layer Deposition (ALD), physical Vapor Deposition (PVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD), and the thickness of the gate dielectric layer 103 may be controlled to be 1-50nm, and in this embodiment, 8nm. The material of the gate dielectric layer may be selected from a general high-k dielectric material, such as aluminum oxide (Al 2O3), aluminum nitride (AlN), zirconium oxide (ZrO 2), titanium oxide (TiO 2), hafnium oxide (HfO 2), hafnium oxynitride (HfO xNy), lanthanum oxynitride (LaO xNy), yttrium oxide (Y 2O3), lanthanum oxide (La 2O3), or the like.
In another embodiment, a first gate dielectric sub-layer is formed before the gate dielectric layer is formed, and then a second gate dielectric sub-layer is formed after the gate dielectric layer is formed, wherein the material of the first gate dielectric sub-layer and the material of the second gate dielectric sub-layer can be the same or different, and the first gate dielectric sub-layer can be used as a transition layer for depositing the gate dielectric layer, so that the growth quality of the gate dielectric layer is improved; the second gate dielectric sub-layer is used as the transition between the gate dielectric layer and the low-dimensional semiconductor layer, is favorable for the deposition of the low-dimensional semiconductor layer, and forms a better interface with the transition layer above the low-dimensional semiconductor layer. Preferably, the material of the first gate dielectric sub-layer is the same as that of the second gate dielectric sub-layer, so that symmetry is achieved at two sides of the gate dielectric layer, and hysteresis of the device is reduced. By using the stacked combination of the first gate dielectric sub-layer/the gate dielectric layer/the second gate dielectric sub-layer as the gate dielectric of the device, more accurate control of the threshold voltage and higher on-off ratio can be realized. Specifically, the first gate dielectric sublayer may be yttria (Y 2O3), forming a metal yttrium film on the local bottom gate by electron beam evaporation, then performing thermal oxidation to form an yttria transition layer, further depositing a hafnium oxide (HfO 2) gate dielectric layer by Atomic Layer Deposition (ALD) thereon, and then forming a second yttria (Y 2O3) transition layer according to the thermal oxidation process.
S3, forming a low-dimensional semiconductor layer 104 on the gate dielectric, wherein the low-dimensional semiconductor layer is a single-walled carbon nanotube film in the embodiment, and the low-dimensional semiconductor layer can be obtained by inserting a substrate into a carbon nanotube solution for pulling, wherein the carbon nanotube solution is formed by dissolving carbon nanotubes in one or more halogenated hydrocarbon, and the halogenated hydrocarbon can be selected from organic solvents such as chloroform, dichloroethane, trichloroethane, chlorobenzene, dichlorobenzene, bromobenzene and the like. In other embodiments, the low-dimensional semiconductor material may be multi-walled carbon nanotubes, network-like carbon nanotubes or carbon nanotube arrays. In addition, other low-dimensional semiconductor materials such as silicon nanowires, II-VI element nanowires, III-V element nanowires, two-dimensional layered semiconductor materials and the like can be adopted, wherein the two-dimensional layered semiconductor materials can be molybdenum disulfide, tungsten disulfide or black phosphorus.
Source and drain electrodes 106 are then formed on opposite sides of the low-dimensional semiconductor layer 104 as shown in fig. 6. Next, a metal yttrium thin film 107 is formed on the low-dimensional semiconductor layer 104 and the source and drain electrodes by electron beam evaporation, and then thermal oxidation is performed thereon to form an yttrium oxide transition layer, as shown in fig. 6 and 7. In other embodiments, the transition layer may be deposited in a non-plasma manner, such as thermal atomic layer deposition or physical vapor deposition, and the transition layer comprises at least one of aluminum oxide, yttrium oxide, or hafnium oxide, and preferably yttrium oxide. Next, the electrostatic doped layer 108 is formed using this layer as a transition layer, and in this embodiment, the electrostatic doped layer 108 is formed directly by plasma enhanced atomic energy deposition (PEALD), in which a fixed charge is formed, by selecting an aluminum nitride layer (AlN).
When the electrostatic doped layer 108 is aluminum nitride, the NMOS threshold voltage may be controlled by adjusting the process temperature of atomic layer deposition of aluminum nitride, which is 200-400 c, and in another embodiment, 220-300 c. An alumina layer 109 is then deposited over the electrostatically doped layer 108, an opening pattern is formed over the p-type channel region by a photolithographic process, and the alumina layer 109 and the electrostatically doped layer 108 of aluminum nitride are dry etched according to the pattern and stopped on the yttria layer, as shown in fig. 9-12. A filled yttria (Y 2O3) layer 110 can then be further deposited in the grooves, as shown in fig. 13. In another embodiment, the aluminum oxide layer 109 may be first dry etched, and then the aluminum nitride layer 110 may be wet etched, so as to reduce etching damage such as charge doping caused by the dry etching process. And then flattening the surface of the formed structure to form a PMOS with a yttrium oxide dielectric layer above the p-type channel region and an NMOS with a silicon nitride electrostatic doping layer and an aluminum oxide protective layer in the n-type channel region, thereby forming a CMOS device.
It should be noted that the foregoing detailed description is exemplary and is intended to provide further explanation of the application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the exemplary embodiments described above in accordance with the present application. As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise. Furthermore, it will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, devices, components, and/or groups thereof.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or otherwise described herein.
Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Spatially relative terms, such as "above … …," "above … …," "upper surface on … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations "above … …" and "below … …". The device may also be positioned in other different ways, such as rotated 90 degrees or at other orientations, and the spatially relative descriptors used herein interpreted accordingly.
In the above detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, like numerals typically identify like components unless context indicates otherwise. The illustrated embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (24)

1. A transistor comprising a substrate (101), a local bottom gate (102), a gate dielectric layer (103), a low-dimensional semiconductor layer (104), a source and a drain, characterized in that:
the local bottom gate (102) is embedded in the substrate (101) and is in the same plane with the substrate or is positioned on the substrate (101);
A gate dielectric layer (103) is arranged on the local bottom gate (102), and the low-dimensional semiconductor layer (104) is positioned on the gate dielectric layer (103) and is used as a channel of the transistor device;
The source and drain electrodes are located on opposite sides of the channel and are in contact with one or more portions of the low-dimensional semiconductor layer (104), respectively;
-having a transition layer (107) on the channel and an electrostatic doped layer (108), the electrostatic doped layer (108) having a fixed charge formed therein;
A first gate dielectric sub-layer (103 ') is arranged between the local bottom gate (102) and the gate dielectric layer (103), a second gate dielectric sub-layer (103 ") is arranged between the gate dielectric layer (103) and the electrostatic doping layer (108) or the transition layer (107), and yttrium oxide/hafnium oxide/yttrium oxide is adopted as the first gate dielectric sub-layer (103')/the gate dielectric layer (103)/the second gate dielectric sub-layer (103").
2. The transistor according to claim 1, wherein the substrate (101) comprises at least one of a SiO 2/Si substrate, a quartz substrate, an Al 2O3 substrate, a glass substrate, or a polymer substrate.
3. The transistor according to claim 1, wherein the low-dimensional semiconductor layer (104) is selected from carbon nanotubes, silicon nanowires and group II-VI element nanowires, group III-V element nanowires, and two-dimensional layered semiconductor materials, the carbon nanotubes being single-walled carbon nanotubes, multi-walled carbon nanotubes, network-like carbon nanotubes, or arrays of carbon nanotubes, the two-dimensional layered semiconductor materials being black phosphorus or molybdenum disulfide.
4. The transistor of claim 1, wherein the partial bottom gate (102) comprises at least one of tantalum nitride (TaN), titanium nitride (TiN), polysilicon, gold (Au), palladium (Pd), platinum (Pt), titanium/gold stack (Ti/Au), titanium/palladium stack (Ti/Pd), or titanium/platinum stack (Ti/Pt).
5. The transistor of claim 1, wherein the source and drain electrodes comprise at least one of platinum (Pt), titanium (Ti), or palladium (Pd).
6. The transistor of claim 1, wherein the first gate dielectric sublayer (103') and the second gate dielectric sublayer (103 ") comprise at least one of aluminum oxide (Al 2O3), aluminum nitride (AlN), hafnium oxide (HfO 2), zirconium oxide (ZrO 2), titanium oxide (TiO 2), hafnium oxynitride (HfO xNy), lanthanum oxynitride (LaO xNy), yttrium oxide (Y 2O3), or lanthanum oxide (La 2O3).
7. The transistor according to claim 1, characterized in that the electrostatically doped layer (108) is aluminum nitride.
8. A transistor according to claim 1, characterized in that a protective layer (109) is provided on the electrostatically doped layer (108).
9. A transistor according to claim 1, characterized in that there is a transition layer (107) between the electrostatically doped layer (108) and the low-dimensional semiconductor layer (104).
10. A method of fabricating a transistor according to any one of claims 1 to 9, comprising the steps of:
providing a substrate (101), and forming a local bottom gate (102) on the substrate (101);
Forming a gate dielectric layer (103) on the local bottom gate (102);
Forming a low-dimensional semiconductor layer (104) on the gate dielectric layer (103);
forming a source electrode and a drain electrode on opposite sides of the low-dimensional semiconductor layer (104), and exposing a part of the low-dimensional semiconductor layer (104) as a channel layer of the transistor;
A transition layer (107) and an electrostatic doped layer (108) are further formed on the channel layer, the electrostatic doped layer (108) having a fixed charge therein.
11. The method of manufacturing a transistor according to claim 10, wherein the substrate (101) is at least one selected from a SiO 2/Si substrate, a quartz substrate, an Al 2O3 substrate, a glass substrate, and a polymer substrate, and further comprising an operation of performing pretreatment on a surface of the substrate, before forming the low-dimensional semiconductor layer, the pretreatment including at least one of plasma treatment, annealing treatment, wet chemical cleaning, and surface molecular modification.
12. The method of claim 10, wherein the low-dimensional semiconductor layer is at least one of a carbon nanotube, a silicon nanowire, a group II-VI element nanowire, a group III-V element nanowire, and a two-dimensional layered semiconductor material, the carbon nanotube being a single-walled carbon nanotube, a multi-walled carbon nanotube, a network-like carbon nanotube, or an array of carbon nanotubes, and the two-dimensional layered semiconductor material being black phosphorus or molybdenum disulfide.
13. The method of claim 10, wherein the local bottom gate is at least one selected from the group consisting of tantalum nitride (TaN), titanium nitride (TiN), polysilicon, gold (Au), palladium (Pd), platinum (Pt), titanium/gold stack (Ti/Au), titanium/palladium stack (Ti/Pd), and titanium/platinum stack (Ti/Pt).
14. The method of claim 10, wherein the source and drain electrodes are at least one selected from the group consisting of platinum (Pt), titanium (Ti), and palladium (Pd).
15. The method according to claim 10, wherein a first gate dielectric sub-layer (103') is formed after the local bottom gate (102) is formed, the gate dielectric layer (103) is formed on the first gate dielectric sub-layer, and further a second gate dielectric sub-layer (103 ") is formed on the gate dielectric layer (103), wherein the materials of the first gate dielectric sub-layer and the second gate dielectric sub-layer are the same or different.
16. The method of claim 15, wherein the first gate dielectric sub-layer and the second gate dielectric sub-layer comprise at least one of aluminum oxide (Al 2O3), aluminum nitride (AlN), hafnium oxide (HfO 2), zirconium oxide (ZrO 2), titanium oxide (TiO 2), hafnium oxynitride (HfO xNy), lanthanum oxynitride (LaO xNy), yttrium oxide (Y 2O3), or lanthanum oxide (La 2O3).
17. The method of manufacturing a transistor according to claim 10, wherein the electrostatically doped layer (108) is aluminum nitride.
18. The method of manufacturing a transistor according to claim 10, wherein a protective layer (109) is further formed on the electrostatically doped layer (108), the protective layer (109) comprising at least one of aluminum oxide or silicon nitride.
19. The method of manufacturing a transistor according to claim 10, wherein a transition layer (107) is provided between the electrostatically doped layer (108) and the low dimensional semiconductor layer (104), the transition layer (107) being deposited in a non-plasma manner, the transition layer (107) comprising at least one of aluminum oxide, yttrium oxide or hafnium oxide.
20. The manufacturing method of the complementary field effect transistor is characterized by comprising the following steps:
Providing a substrate (101), and forming a first local bottom gate and a second local bottom gate on the substrate (101) to serve as PMOS (P-channel metal oxide semiconductor) corresponding gates and NMOS (N-channel metal oxide semiconductor) corresponding gates respectively;
Forming a gate dielectric layer (103) on the first partial bottom gate and the second partial bottom gate;
Forming a low-dimensional semiconductor layer (104) on the gate dielectric layer (103);
Forming a source electrode and a drain electrode on two opposite sides of the low-dimensional semiconductor layer (104) corresponding to the first partial bottom gate and the second partial bottom gate respectively, and exposing part of the low-dimensional semiconductor layer (104) to serve as channel layers of the PMOS and the NMOS respectively;
Further depositing a transition layer (107) and an electrostatic doped layer (108) on the structure formed in the step, wherein the electrostatic doped layer (108) has fixed charges therein;
forming a first protection layer on the structure, wherein the first protection layer fills the groove between the source electrode and the drain electrode, and further flattening the groove;
defining a window pattern of a semiconductor channel layer corresponding to the first local bottom gate on the surface of the first protective layer formed after planarization, and performing dry etching on the first protective layer and the electrostatic doping layer by taking the transition layer as an etching stop layer to form a groove;
Further depositing a second protective layer in the groove formed after the etching, so as to form a PMOS corresponding to the first partial bottom gate and an NMOS corresponding to the second partial bottom gate, and finally further forming the complementary field effect transistor through an interconnection process;
Forming a first gate dielectric sub-layer after forming the first partial bottom gate and the second partial bottom gate, forming the gate dielectric layer on the first gate dielectric sub-layer, and further forming a second gate dielectric sub-layer on the gate dielectric layer, wherein yttrium oxide/hafnium oxide/yttrium oxide is adopted as the first gate dielectric sub-layer/gate dielectric layer/second gate dielectric sub-layer.
21. The method of claim 20, wherein the first gate dielectric sub-layer and the second gate dielectric sub-layer comprise at least one of aluminum oxide (Al 2O3), aluminum nitride (AlN), hafnium oxide (HfO 2), zirconium oxide (ZrO 2), titanium oxide (TiO 2), hafnium oxynitride (HfO xNy), lanthanum oxynitride (LaO xNy), yttrium oxide (Y 2O3), or lanthanum oxide (La 2O3).
22. The method of claim 20, wherein the electrostatically doped layer is aluminum nitride.
23. The method of claim 20, wherein when the electrostatic doped layer is aluminum nitride, the NMOS threshold voltage is controlled by adjusting a process temperature of atomic layer deposition of aluminum nitride, the process temperature being 200-400 ℃.
24. The method of claim 20, wherein the first protective layer is aluminum oxide or silicon nitride and the second protective layer is yttrium oxide.
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CN105810748A (en) * 2014-12-31 2016-07-27 清华大学 N-type thin film transistor
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CN103858344A (en) * 2011-06-23 2014-06-11 国际商业机器公司 Graphene or carbon nanotube devices with localized bottom gates and gate dielectric
CN105810748A (en) * 2014-12-31 2016-07-27 清华大学 N-type thin film transistor
WO2020244541A1 (en) * 2019-06-05 2020-12-10 京东方科技集团股份有限公司 Thin film transistor, manufacturing method for same, and electronic device

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