CN113690219B - Semiconductor device, manufacturing method thereof and electronic equipment - Google Patents
Semiconductor device, manufacturing method thereof and electronic equipment Download PDFInfo
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- CN113690219B CN113690219B CN202010421260.1A CN202010421260A CN113690219B CN 113690219 B CN113690219 B CN 113690219B CN 202010421260 A CN202010421260 A CN 202010421260A CN 113690219 B CN113690219 B CN 113690219B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
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- 238000001312 dry etching Methods 0.000 claims abstract description 15
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- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
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Abstract
The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment, which relate to the technical field of semiconductors and ensure that corresponding contact structures adjacent to the side wall or the bottom of the air side wall do not generate electrochemical corrosion phenomenon when the air side wall is formed in a dry etching mode, so that the corresponding contact structures have good conductivity, and the working performance of the semiconductor device is improved. The semiconductor device includes: the device comprises a substrate, a bit line structure and a side wall structure. A substrate having an active region. A bit line structure is formed over the active region. The sidewall structure is formed on the substrate. The sidewall structure surrounds the sidewall of the bit line structure. The side wall structure comprises an air side wall and a medium side wall surrounding the air side wall, wherein the part of the medium side wall positioned at the top of the air side wall is made of a breathable material. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device provided by the technical scheme. The semiconductor device provided by the invention is applied to electronic equipment.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a manufacturing method thereof, and an electronic apparatus.
Background
In order to reduce parasitic capacitance between adjacent bit lines, air side walls with lower dielectric constants are respectively arranged on two sides of a bit line structure in a semiconductor device. In order to form the air sidewall, it is necessary to form sacrificial layers on both sides of the bit line structure in advance when manufacturing the semiconductor device. After the storage contact part and the landing pad are formed, removing the sacrificial layer in a wet etching mode, wherein the space where the sacrificial layer is located is correspondingly formed into an air side wall.
However, in the process of removing the sacrificial layer by adopting a wet etching mode, the wet etching solution can cause electrochemical corrosion of the storage contact part, so that the conductivity of the storage contact part is affected, and the working performance of the semiconductor device is reduced.
Disclosure of Invention
The invention aims to provide a semiconductor device, a manufacturing method thereof and electronic equipment, and the air side wall is formed in a dry etching mode, so that the corresponding contact structure adjacent to the side wall or the bottom of the air side wall can not generate electrochemical corrosion phenomenon when the air side wall is formed, and the corresponding contact structure has good conductivity, thereby improving the working performance of the semiconductor device.
In order to achieve the above object, the present invention provides a semiconductor device including:
a substrate having an active region;
a bit line structure formed on the active region;
And the side wall structure is formed on the substrate, surrounds the side wall of the bit line structure, and comprises an air side wall and a medium side wall surrounding the air side wall, wherein the part of the medium side wall positioned at the top of the air side wall is made of a breathable material.
Compared with the prior art, in the semiconductor device provided by the invention, the side wall structure surrounding the side wall of the bit line structure is formed on the substrate. The side wall structure comprises an air side wall and a medium side wall surrounding the air side wall. And the part of the medium side wall positioned at the top of the air side wall is made of breathable materials. On the basis, in the process of manufacturing the semiconductor device, after the sacrificial layer and the dielectric side wall surrounding the periphery of the sacrificial layer are formed, a dry etching mode, such as an ashing mode, can be adopted, at least the part of the dielectric side wall, which is positioned at the top of the sacrificial layer, is used for removing gas formed after the sacrificial layer is processed, and the air side wall can be obtained at the position where the original sacrificial layer is positioned. Compared with the air side wall formed by wet etching in the conventional semiconductor device, the air side wall in the semiconductor device provided by the invention can be formed by dry etching. When the air side wall in the semiconductor device is formed, etching solution in a wet etching mode is not used. The phenomenon of electrochemical corrosion of the related contact structure included in the semiconductor device caused by contact of the etching solution with the related contact structure adjacent to the air side wall through the gap of the air side wall is avoided, and the conductivity of the related contact structure is ensured, so that the performance of the semiconductor device is improved.
The invention also provides a manufacturing method of the semiconductor device, which comprises the following steps:
Providing a substrate with an active region;
Forming a bit line structure on the active region;
and forming a side wall structure on the substrate, wherein the side wall structure surrounds the side wall of the bit line structure, the side wall structure comprises an air side wall and a medium side wall surrounding the air side wall, and the part of the medium side wall positioned at the top of the air side wall is made of a breathable material.
Compared with the prior art, the beneficial effects of the manufacturing method of the semiconductor device provided by the invention are the same as those of the semiconductor device provided by the technical scheme, and the detailed description is omitted here.
The invention also provides electronic equipment comprising the semiconductor device provided by the technical scheme.
Compared with the prior art, the beneficial effects of the electronic equipment provided by the invention are the same as those of the semiconductor device provided by the technical scheme, and the description is omitted here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
FIG. 1 is a schematic view of a portion of a prior art semiconductor device;
fig. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a structure after forming a pre-sidewall structure and a contact material layer according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a structure after back etching of a pre-sidewall structure and a contact material layer in an embodiment of the present invention;
FIG. 5 is a schematic view of a structure after removing the remaining third pre-side wall according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a structure after forming a sacrificial layer according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a structure of a third dielectric material layer according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a structure after forming a dielectric sidewall in an embodiment of the present invention;
FIG. 9 is a schematic diagram of a structure after forming an air sidewall in an embodiment of the present invention;
FIG. 10 is a schematic diagram of a structure after forming a metal material layer according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a structure after forming landing pads in an embodiment of the present invention;
fig. 12 is a schematic view of a part of a structure of a semiconductor device according to an embodiment of the present invention;
fig. 13 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Reference numerals:
1 is a substrate, 11 is an active region, 2 is a bit line structure, 21 is a bit line, 22 is an isolation layer, 3 is an air sidewall, 4 is a dielectric sidewall, 41 is a first dielectric sidewall, 42 is a second dielectric sidewall, 43 is a third dielectric sidewall, 5 is Liu Hanpan, 6 is a storage contact portion, 7 is a pre-sidewall structure, 71 is a first pre-sidewall, 72 is a second pre-sidewall, 73 is a third pre-sidewall, 8 is a groove, 9 is a sacrificial layer, 10 is a contact material layer, and 20 is a metal material layer.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned. In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. The meaning of "a number" is one or more than one unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
As shown in fig. 1, in the fabrication of a semiconductor device, a transistor is formed on a substrate, and a bit line structure, a memory contact, a landing pad, and the like are formed on the transistor. Wherein the bit line structure is electrically connected to a source (or drain) of an active region included in the transistor, and the memory contact is electrically connected to a drain (or source) of the active region included in the transistor. And, an air sidewall surrounding the sidewall of the bit line structure can be formed on the bit line structure to reduce parasitic capacitance between adjacent bit line structures. However, in the process of forming the air sidewall, a sacrificial layer is required to be formed on the sidewall of the bit line structure in advance, and the dielectric sidewall is required to cover the periphery of the sacrificial layer. After the storage contact part and the landing pad are formed subsequently, removing the exposed sacrificial layer by adopting a wet etching mode through an opening structure formed on the dielectric side wall, and forming an air side wall at the position where the original sacrificial layer is located. In the process of forming the air side wall by reacting the etching solution with the sacrificial layer, the wet etching solution can contact with the formed storage contact part through a gap of the air side wall, so that the storage contact part generates electrochemical corrosion phenomenon, the conductivity of the storage contact part is affected, and the working performance of the semiconductor device is reduced.
In addition, landing pads are formed between adjacent bit line structures, and the landing pad fabrication steps follow the sacrificial layer and dielectric sidewall formation and precede the air sidewall formation. At this time, the gap between the adjacent bit line structures is reduced due to the existence of the sacrificial layer and the dielectric sidewall, so that the width L of the landing pad is smaller, and further the resistance of the landing pad is increased, thereby affecting the conductivity of the landing pad.
The method aims to solve the technical problems that the air side wall in the existing semiconductor device is formed in a wet etching mode, so that electrochemical corrosion phenomenon is generated at the storage contact part, the conductivity of the storage contact part is affected, and the working performance of the semiconductor device is reduced. The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and electronic equipment. The medium side wall in the semiconductor device is made of a gas-permeable material at the top of the air side wall. On the basis, the air side wall can be formed in a dry etching mode, so that the phenomenon of electrochemical corrosion of the related contact structure can not occur when the air side wall is formed, the related contact structure has good conductivity, and the performance of the semiconductor device is improved.
In view of the above technical problems, embodiments of the present invention provide a semiconductor device that can be applied to electronic devices such as DRAM (dynamic random access memory), PRAM (phase change memory), or MRAM (magnetic random access memory). As shown in fig. 2, the semiconductor device includes a substrate 1, a bit line structure 2, and a sidewall structure.
The substrate 1 may be a single semiconductor material such as monocrystalline silicon, polycrystalline silicon, or the like. Of course, the substrate 1 may also be a laminate of already formed semiconductor structures. For example: in DRAM fabrication, the surface of the dielectric layer formed over the transistor may be used as the surface of the substrate 1. The substrate 1 has an active region 11. The active region 11 may have a source and a drain formed therein. As for the number of active regions 11, it is possible to set according to the actual application scenario, and is not particularly limited herein. In some cases, the above substrate 1 also has a gate stack structure. The gate stack structure may include a gate dielectric layer and a gate electrode. The gate dielectric layer may be a silicon oxide layer, a thermal oxide layer, or an insulating material layer such as a high-k dielectric layer. The gate electrode may be made of doped polysilicon, metal or metal silicide.
The bit line structure 2 is formed on the active region 11. It should be appreciated that the bit line structures 2 described above are electrically connected to the source (or drain) of the corresponding active region 11. The bit line structure 2 is a single layer or a plurality of layers, and the specific types of the contained materials can be set according to the actual application scene. The number of the bit line structures 2 is not limited herein, and the invention can be applied to the semiconductor device provided in the embodiment of the present invention. Illustratively, the bit line structure 2 includes bit lines 21 and spacers 22 on the respective bit lines 21. The material contained in the bit line 21 may be a conductive material such as doped polysilicon, tungsten, or aluminum. The material contained in the isolation layer 22 may be an insulating material such as SiCN, siOCN, or SiN. Of course, in some cases, the bit line contact structure may be considered as part of the bit line structure 2. The bit line contact structure may be made of doped polysilicon or boron doped silicon germanium.
The sidewall structure is formed on the substrate 1. The sidewall structures surround the sidewalls of the bit line structure 2. The side wall structure comprises an air side wall 3 and a medium side wall 4 surrounding the air side wall 3, wherein the part of the medium side wall 4 positioned at the top of the air side wall 3 is made of a breathable material. It should be understood that, when the height direction of the air sidewall 3 is the same as the height direction of the bit line structure 2, the top height of the air sidewall 3 is less than or equal to the top height of the bit line structure 2. Specifically, the top height of the air sidewall 3 may be designed according to the practical application scenario, so long as parasitic capacitance between adjacent bit line structures 2 can be eliminated. For example, when the bit line structure 2 includes the bit lines 21 and the spacers 22 on the corresponding bit lines 21 as described above, the top height of the air sidewall 3 may be greater than or equal to the top height of the bit lines 21 and less than the top height of the spacers 22.
The portion of the dielectric sidewall 4 located at the top of the air sidewall 3 may be a dielectric sidewall with a relatively loose structure. For example: porous dielectric side walls. The porous medium side wall is made of porous insulating material. The plasma or gas and the like can pass through the hole structure of the porous medium side wall and enter the inside (or the outside) of the porous medium side wall from the outside (or the inside) of the porous medium side wall, so that the part of the medium side wall 4 positioned at the top of the air side wall 3 has ventilation property. Of course, the material contained in the dielectric sidewall 4 may be selected according to the actual application scenario, so long as the portion of the dielectric sidewall 4 formed by the manufacturing process, which is located at the top of the air sidewall 3, has air permeability.
For example, the structure of the dielectric sidewall 4 may be designed according to the practical application scenario, and is not specifically limited herein. Specifically, each region in the dielectric sidewall 4 may be a porous dielectric sidewall, or only a portion of the dielectric sidewall 4 located at the top of the air sidewall 3 may be a porous dielectric sidewall, so long as it is ensured that the gas formed by the conversion of the sacrificial layer 9 can be discharged through the dielectric sidewall 4.
It is noted that there are dielectric spacers 4 formed on the outer periphery of the air spacers 3 in addition to the air spacers 3 between adjacent bit line structures 2, or between the bit line structures 2 and the associated contact structures adjacent to the bit line structures 2. The presence of the dielectric sidewall 4 may further isolate adjacent bit line structures 2 or bit line structures 2 and associated contact structures adjacent to the bit line structures 2. In addition, the part of the medium side wall 4 positioned at the top of the air side wall 3 is made of air-permeable material. Of course, the portion of the dielectric sidewall 4 located on the sidewall of the air sidewall 3 may also be made of an air permeable material. On the basis, in the process of manufacturing the semiconductor device, a dry etching mode (such as an ashing treatment mode) is adopted to convert the sacrificial layer 9 preformed at the position of the air side wall 3 into gas. The gas can be discharged through the part of the medium side wall 4 made of the gas-permeable material, thereby realizing the formation of the air side wall 3.
In the semiconductor device provided by the embodiment of the invention, a side wall structure surrounding the side wall of the bit line structure 2 is formed on the substrate 1. The side wall structure comprises an air side wall 3 and a medium side wall 4 surrounding the air side wall 3. And, the part of the medium side wall 4 positioned at the top of the air side wall 3 is made of air-permeable material. On the basis, in the process of manufacturing the semiconductor device, after the sacrificial layer 9 and the dielectric side wall 4 surrounding the periphery of the sacrificial layer 9 are formed, a dry etching mode, such as an ashing mode, can be adopted, at least through the part of the dielectric side wall 4 positioned at the top of the sacrificial layer 9, the gas formed after the treatment of the sacrificial layer 9 is removed, and the air side wall 3 can be obtained at the position where the original sacrificial layer 9 is positioned. Compared with the air side wall 3 formed by wet etching in the existing semiconductor device, the air side wall 3 in the semiconductor device provided by the embodiment of the invention can be formed by dry etching. In forming the air sidewall 3 in the semiconductor device, the etching solution in the wet etching mode is not used. The phenomenon of electrochemical corrosion of the relevant contact structure included in the semiconductor device caused by the contact of the etching solution with the relevant contact structure adjacent to the air side wall 3 through the gap of the air side wall 3 is avoided, the conductivity of the relevant contact structure is ensured, and the performance of the semiconductor device is improved.
In an alternative manner, as shown in fig. 2, the dielectric spacers 4 include a first dielectric spacer 41, a second dielectric spacer 42, and a third dielectric spacer 43. The first dielectric sidewall 41, the second dielectric sidewall 42, and the third dielectric sidewall 43 enclose an air sidewall 3.
Specifically, the first dielectric sidewall 41 and the second dielectric sidewall 42 are formed on the substrate 1. The first dielectric sidewall 41 covers the sidewall of the bit line structure 2. When the height direction of the first dielectric sidewall 41 is the same as the height direction of the bit line structure 2, the top height of the first dielectric sidewall 41 may be equal to the top height of the bit line structure 2.
The second dielectric sidewall 42 is formed on the periphery of the first dielectric sidewall 41, and the second dielectric sidewall 42 surrounds the first dielectric sidewall 41. The top height of the second dielectric sidewall 42 may be less than or equal to the top height of the first dielectric sidewall 41. It will be appreciated that the spacing of the second dielectric sidewall 42 from the first dielectric sidewall 41 determines the width of the third dielectric sidewall 43 and the air sidewall 3. In addition, the top height of the second dielectric sidewall 42 determines the top height of the third dielectric sidewall 43, and the top height of the third dielectric sidewall 43 and the thickness of the third dielectric sidewall 43 determine the top height of the air sidewall 3, so the distance between the second dielectric sidewall 42 and the first dielectric sidewall 41 and the top height of the second dielectric sidewall 42 can be set according to the related parameters of the third dielectric sidewall 43 and the air sidewall 3.
The third dielectric sidewall 43 is formed between the first dielectric sidewall 41 and the second dielectric sidewall 42. The top height of the third dielectric sidewall 43 is greater than or equal to the top height of the bit line 21 and less than the top height of the isolation layer 22. It will be appreciated that the top height of the third dielectric sidewall 43, as described above, and the layer thickness of the third dielectric sidewall 43 determine the top height of the air sidewall 3. The height of the third dielectric sidewall 43 may be set according to the height of the air sidewall 3. The thickness of the third dielectric sidewall 43 may be set according to the actual application scenario.
As for the first dielectric sidewall 41, the second dielectric sidewall 42, and the third dielectric sidewall 43, the materials contained in the three may be breathable materials. Or only the third dielectric sidewall 43 may comprise a breathable material. So long as it is ensured that the gases formed by the conversion of the sacrificial layer 9 can be discharged through the dielectric sidewall 4. Illustratively, the third dielectric sidewall 43 comprises a material that is breathable. At this time, when the ashing treatment is performed on the sacrificial layer 9, the gas formed by the conversion of the sacrificial layer 9 may be discharged through the third dielectric sidewall 43 on top of the sacrificial layer 9. It should be understood that the material of the porous dielectric sidewall may be a porous insulating material. A common porous insulating material may be porous SiO 2 formed by atomic layer deposition.
As a possible implementation, the above-mentioned semiconductor device further comprises a storage contact 6 and a landing pad 5 formed on the substrate 1, as shown in fig. 2 and 12. Landing pads 5 are formed on the storage contacts 6. The amount of width variation of the landing pad 5 in the height direction of the landing pad 5 is less than or equal to a preset threshold. It should be appreciated that in the process of fabricating the semiconductor device described above, after the air sidewall 3 is formed by ashing, the landing pads 5 need to be formed between adjacent bit line structures 2. If the height of the air sidewall 3 surrounding the sidewall of the bit line structure 2 is smaller than the top height of the bit line structure 2, there is a wider space between the relevant regions (where the air sidewall 3 is not formed) in the adjacent bit line structures 2. And the landing pad 5 formed after the formation of the air sidewall 3 may be formed in the above-described wider space such that the width L of the landing pad 5 in this space is larger. On this basis, the width of each portion of the landing pad 5 varies less along the height direction of the landing pad 5, and the variation amount thereof may be less than or equal to a preset threshold. Further, the larger width L of the landing pad 5 in the space may cause the cross-sectional area of the landing pad 5 in the space to increase. Since the resistance is inversely proportional to the area, the cross-sectional area of the landing pad 5 is larger, so that the resistance of the landing pad 5 is smaller, thereby improving the conductive performance of the landing pad 5.
The magnitude of the preset threshold is affected by factors such as the size of the semiconductor device, the size of the bit line structure 2, the width of the sidewall structure, and the size of the memory contact 6. Specifically, the magnitude of the preset threshold needs to be set according to the actual application scenario, which is not specifically limited herein. For example, when the semiconductor device is applied to a 30 nm-class DRAM, the above-mentioned preset threshold ranges are: 20 angstroms to 60 angstroms. The landing pad 5 is made of a conductive material, and a common conductive material is tungsten or titanium nitride. For the memory contact 6, the memory contact 6 may be made of a conductive material such as doped polysilicon or boron doped silicon germanium.
In practical use, as shown in fig. 2 and 10, when the semiconductor device is applied to a DRAM, the substrate 1 has an active region 11. The bit line structure 2 is electrically connected to a source (or drain) provided in the corresponding active region 11 through a bit line contact structure. The landing pads 5 are electrically connected with the drains (or sources) that the respective active regions 11 have through the respective memory contacts 6. The air side walls 3 on the two sides of the storage contact part 6 are the air side walls 3 formed by dry etching. In the process of forming the air side wall 3, etching solution used in wet etching is not introduced, so that the storage contact part 6 can be ensured not to generate electrochemical corrosion phenomenon when the air side wall 3 is formed, and the storage contact part 6 has good conductivity. And, the height of the air sidewall 3 is smaller than the height of the bit line structure 2. The volume occupied by the air side wall 3 between the adjacent bit line structures 2 is reduced, so that the sectional area of the landing pad 5 between the adjacent bit line structures 2 is enlarged, the resistance of the landing pad 5 is reduced, and the conductivity of the landing pad 5 is improved.
The embodiment of the invention also provides a manufacturing method of the semiconductor device, as shown in fig. 13, the manufacturing method of the semiconductor device comprises the following steps:
Step S101: a substrate 1 is provided, the substrate 1 having an active region 11. In some cases, the above substrate 1 also has a gate stack structure. For the specific type of the substrate 1, the material for manufacturing the substrate 1, the type of the active region 11, and the like, reference is made to the foregoing, and no further description is given here.
Step S102: a bit line structure 2 is formed on a substrate 1. It should be understood that when the substrate 1 has the active regions 11, the bit line structure 2 is electrically connected to the source (or drain) of the corresponding active region 11. Illustratively, the bit line structure 2 includes bit lines 21 and spacers 22 on the respective bit lines 21. Of course, in some cases, the bit line contact structure may be considered as part of the bit line structure 2. For the specific structure of the bit line structure 2 and the materials contained in each portion of the bit line structure 2, reference is made to the foregoing, and details are not repeated herein. Specifically, the above-described bit line structure 2 may be formed in various ways. How the bit line structure 2 is formed is not a major feature of the embodiments of the present invention, and therefore, in this specification, it is only briefly described so that one of ordinary skill in the art can easily implement the embodiments provided by the present invention. Other ways of fabricating the bit line structure 2 are well within the contemplation of those of ordinary skill in the art.
Step S103: as shown in fig. 3 to 9, a sidewall structure is formed on a substrate 1, the sidewall structure surrounds a sidewall of a bit line structure 2, the sidewall structure includes an air sidewall 3 and a dielectric sidewall 4 surrounding the air sidewall 3, and a portion of the dielectric sidewall 4 located at the top of the air sidewall 3 contains a material with air permeability. For relevant parameters of the air sidewall 3, reference is made to the foregoing, and details are not repeated here.
As for the structure and the material of fabrication of the dielectric sidewall 4, reference is made to the foregoing. Illustratively, as shown in fig. 9, the dielectric sidewall 4 includes a first dielectric sidewall 41, a second dielectric sidewall 42, and a third dielectric sidewall 43. The first dielectric sidewall 41 and the second dielectric sidewall 42 are both formed on the substrate 1. The first dielectric sidewall 41 surrounds the sidewall of the bit line structure 2, the second dielectric sidewall 42 surrounds the first dielectric sidewall 41, and the third dielectric sidewall 43 is formed between the first dielectric sidewall 41 and the second dielectric sidewall 42. The first dielectric sidewall 41, the second dielectric sidewall 42 and the third dielectric sidewall 43 enclose an air sidewall 3. The top of the third dielectric sidewall 43 has a height greater than or equal to the height of the bit line 21 and less than the height of the isolation layer 22. Wherein, at least third medium side wall 43 is porous medium side wall. Specifically, the relevant parameters of the first dielectric sidewall 41, the second dielectric sidewall 42 and the third dielectric sidewall 43 may be referred to the foregoing, and will not be described herein again.
As a possible implementation manner, the forming a sidewall structure on the substrate 1 includes:
Step S103.1: a sacrificial layer 9 is formed on the substrate 1 around the sidewalls of the bit line structure 2. It should be understood that the region where the sacrificial layer 9 is located is a region where the air sidewall 3 is formed later. The shape parameters of the sacrificial layer 9 can be set with reference to the shape parameters of the air sidewall 3. Specifically, the material contained in the sacrificial layer 9 may be a material which contains carbon such as amorphous carbon and can be removed by ashing.
In an alternative manner, when the dielectric spacers 4 include the first dielectric spacer 41, the second dielectric spacer 42, and the third dielectric spacer 43, forming the sacrificial layer 9 surrounding the sidewall of the bit line structure 2 on the substrate 1 includes:
Step S103.1.1: a pre-sidewall structure 7 surrounding the periphery of the bit line structure 2 is formed on the substrate 1, and the top height of the pre-sidewall structure 7 is greater than or equal to the top height of the bit line structure 2, and the pre-sidewall structure 7 includes a first pre-sidewall 71, a second pre-sidewall 72, and a third pre-sidewall 73 located between the first pre-sidewall 71 and the second pre-sidewall 72.
It should be appreciated that the first pre-sidewall 71 may be subjected to subsequent processing to correspondingly form the first dielectric sidewall 41. The second pre-sidewall 72 is subjected to subsequent processing to correspondingly form the second dielectric sidewall 42. Parameters such as materials contained in the first pre-side wall 71 and the second pre-side wall 72 can be set according to parameters such as materials contained in the first dielectric side wall 41 and the second dielectric side wall 42 respectively. For the third pre-side wall 73, in order to facilitate the subsequent selective removal of the remaining third pre-side wall 73, the remaining first pre-side wall 71 and the remaining second pre-side wall 72 are not affected. The material of the third pre-sidewall 73 needs to be a material that is convenient to remove and needs to be different from the materials of the first pre-sidewall 71 and the second pre-sidewall 72. Illustratively, the first pre-sidewall 71 and the second pre-sidewall 72 are both SiN and the third pre-sidewall 73 is SiO 2.
Step S103.1.2: the pre-sidewall structure 7 is etched back to leave a first pre-sidewall 71, a second pre-sidewall 72 and a third pre-sidewall 73 of a predetermined height on the substrate 1. It should be appreciated that the remaining first pre-sidewall 71 correspondingly forms the first dielectric sidewall 41. The remaining second pre-sidewall 72 correspondingly forms the second dielectric sidewall 42. The positions of the remaining third pre-side walls 73 are correspondingly formed with third dielectric side walls 43 and air side walls 3. The relevant parameters (height parameters, etc.) of the remaining first pre-side wall 71 may be set according to the relevant parameters of the first dielectric side wall 41. The parameters associated with the remaining second pre-sidewall 72 may be set according to the parameters associated with the second dielectric sidewall 42. The parameters related to the remaining third pre-side wall 73 may be set according to the parameters related to the third dielectric side wall 43 and the air side wall 3.
Step S103.1.3: the remaining third pre-sidewall 73 is removed by wet etching. For example, the remaining third pre-sidewall 73 may be removed by wet etching to form the recess 8 between the first pre-sidewall 71 and the second pre-sidewall 72. The etching solution used for removing the remaining third pre-side wall 73 by wet etching includes HF solution. Of course, other satisfactory etching solutions may be used.
Step S103.1.4: a sacrificial material is filled between the remaining first pre-sidewall 71 and the remaining second pre-sidewall 72.
For example, as shown in fig. 6, when the sacrificial layer 9 is a spin-on hard mask, a spin-coating method may be used to form a sacrificial material covering the substrate 1 and the recess 8 on the substrate 1 on which the bit line structure 2, the first pre-sidewall 71 and the second pre-sidewall 72 are formed. It will be appreciated that the width of the recess 8 between the remaining first pre-sidewall 71 and the remaining second pre-sidewall 72 is smaller and that the weight molecular weight and/or concentration of the sacrificial material needs to be adjusted in order to form the sacrificial material within the smaller width recess 8. The weight molecular weight or concentration of the sacrificial material may be set according to the shape parameters of the grooves 8. In particular, the smaller the weight molecular weight or concentration of the sacrificial material, the easier it is for the sacrificial material to enter the smaller width recess 8. And, after the sacrificial material enters the grooves 8, the sacrificial material may be heat treated to harden the sacrificial material. Specifically, the temperature of the heat treatment may be set according to the actual application scenario, as long as it can be applied to the manufacturing method of the semiconductor device.
Step S103.1.5: the sacrificial material is subjected to a back etching process to form a sacrificial layer 9.
Illustratively, as shown in FIG. 6, after the sacrificial material is formed, it is necessary to etch back the sacrificial material, leaving only the sacrificial material in the recess 8. In addition, in order to form the third dielectric sidewall 43 between the first pre-sidewall 71 and the second pre-sidewall 72 later, the sacrificial material in the groove 8 needs to be etched back again, and the remaining sacrificial material in the groove 8 after the etching back correspondingly forms the sacrificial layer 9. Specifically, the thickness of the sacrificial material etched back in the recess 8 may be set according to the thickness of the third dielectric sidewall 43. Illustratively, the sacrificial material within recess 8 is etched back to a thickness of 10 angstroms to 300 angstroms.
Step S103.2: a dielectric spacer 4 is formed on the substrate 1 around the periphery of the sacrificial layer 9.
Illustratively, after forming the sacrificial layer 9 within the recess 8, an atomic deposition process is used to deposit a layer of gas permeable material over the substrate 1 and within the recess 8. Thereafter, the breathable material may be selectively etched by wet etching to remove the breathable material located outside the recess 8. At this time, the third medium sidewall 43 is correspondingly formed by the remaining air-permeable material in the groove 8. The remaining first pre-sidewall 71 correspondingly forms the first dielectric sidewall 41. The remaining second pre-sidewall 72 correspondingly forms the second dielectric sidewall 42. The type of the breathable material and the thickness of the breathable material may be set with reference to the material contained in the third medium sidewall 43 and the thickness of the third medium sidewall 43, which are not described herein.
Step S103.3: and removing the sacrificial layer 9 by adopting a dry etching mode to obtain the air side wall 3.
In an alternative manner, the dry etching manner includes an ashing manner, that is, the sacrificial layer 9 may be removed by an ashing manner, so as to obtain the air sidewall 3.
Specifically, the substrate 1 on which the bit line structure 2, the sacrificial layer 9, and the dielectric sidewall 4 are formed is placed in a chamber provided in an ashing process apparatus. And a reaction gas such as O 2 is introduced into the chamber, and the reaction gas can be excited into plasma. The resulting plasma can pass through at least the third dielectric sidewall 43 formed of a gas permeable material, contact the sacrificial layer 9, and react with the sacrificial layer 9. The sacrificial layer 9 is converted into gas (for example, gaseous hydrocarbon), and after the gas is exhausted from the third medium sidewall 43, the air sidewall 3 is correspondingly formed in the area where the original sacrificial layer 9 is located. Therefore, when the air side wall 3 is formed in an ashing treatment mode, etching solution used in wet etching is not introduced, and electrochemical corrosion of the corresponding contact structure is not caused when the air side wall 3 is formed, so that the corresponding contact structure has good conductivity. Specifically, since the ashing process is an existing mature process, details of the ashing process may be determined according to actual application scenarios, which will not be described herein.
Illustratively, if the material contained in the sacrificial layer 9 is amorphous carbon, the ashing treatment is performed on the sacrificial layer 9 after the sacrificial layer 9 and the dielectric sidewall 4 are formed. The plasma used in the ashing process was O 2 plasma, wherein the concentration of O 2 plasma was 1000ppm to 99999ppm. The O 2 plasma may pass through the third dielectric sidewall 43 and react with the sacrificial layer 9. The oxidized sacrificial layer 9 is converted into a gas, and the gas can be discharged through the third dielectric sidewall 43, thereby forming the air sidewall 3 at the position of the original sacrificial layer 9.
As a possible implementation, as shown in fig. 9, the top height of the air sidewall 3 is smaller than the top height of the bit line structure 2. In other words, the air sidewall 3 is formed only on a sidewall of a part of the height of the bit line structure 2. For example, when the bit line structure 2 includes the bit lines 21 and the spacers 22 on the corresponding bit lines 21 as described above, the height of the air sidewall 3 may be greater than or equal to the top height of the bit lines 21 and less than the top height of the spacers 22.
In the above case, as shown in fig. 11, the above semiconductor device further includes a storage contact 6 and a landing pad 5 formed on the substrate 1. The storage contact 6 is electrically connected to a drain (or source) provided in the corresponding active region 11. Landing pads 5 are formed on the storage contacts 6. Reference is made to the foregoing for the structure and the material of construction of the storage contact 6, and no further description is given here.
Specifically, when the semiconductor device further includes the storage contact portion 6, the step of fabricating the storage contact structure 6 after forming the bit line structure 2 on the substrate 1 and before forming the sidewall structure on the substrate 1, the step of fabricating the storage contact structure 6 includes:
Step S104: a storage contact 6 is formed on the substrate 1.
Specifically, when the semiconductor device is applied to a DRAM, the surface of the substrate 1 is the surface of a dielectric layer formed on a transistor. A via is opened in the dielectric layer between adjacent bit line structures 2, the bottom of the via being in contact with the drain (or source) provided in the corresponding active region 11. A contact material layer 10 is formed within the via. Then, the contact material layer 10 is etched by wet etching or dry etching, and only the portion of the contact material layer 10 located above the corresponding active region 11 is left, thereby obtaining the memory contact portion 6. For the contact material layer 10, the material contained in the contact material layer 10 may be a conductive material such as doped polysilicon or boron doped silicon germanium.
It should be noted that, the above-mentioned manufacturing steps of the storage contact portion 6 may be performed after the bit line structure 2 is formed on the substrate 1 and before the sidewall structure is formed on the substrate 1. It is also possible that after the formation of the sidewall structure on the substrate 1 and before the formation of the landing pad 5. Specifically, the order of the steps of manufacturing the memory contact portion 6 may be designed according to the actual application scenario, as long as it can be applied to the manufacturing method of the present semiconductor device.
For the landing pad 5, the step of forming the landing pad 5 after forming the sidewall structure on the substrate 1 by dry etching (specifically, after forming the air sidewall 3) specifically includes:
Step S105: as shown in fig. 10 and 11, a landing pad 5 is formed on the substrate 1. At this time, the width variation of the landing pad 5 is less than or equal to the preset threshold in the height direction of the landing pad 5. Reference is made to the foregoing for the material contained in the landing pad 5, and no further description is given here. Illustratively, as shown in fig. 10 and 11, after the air sidewall 3 is formed, a metal material layer 20 is formed over the substrate 1 to cover the substrate 1 by direct deposition or the like. Thereafter, the metal material layer 20 is etched to form landing pads 5 at the respective regions. Specifically, the height of the metal material layer 20 determines the height of the landing pad 5. The material contained in the metal material layer 20 determines the material contained in the landing pad 5. The height and fabrication material of the metal material layer 20 may be set according to the height and fabrication material of the landing pad 5.
The embodiment of the invention also provides electronic equipment, which comprises the semiconductor device provided by the embodiment. The electronic device may be a communication device or a terminal device, etc., but is not limited thereto. Further, the terminal device includes a mobile phone, a smart phone, a tablet computer, a computer, an artificial intelligent device, a mobile power supply, and the like. The communication device includes a base station and the like, but is not limited thereto.
The beneficial effects of the electronic device provided by the embodiment of the present invention are the same as those of the semiconductor device provided by the above embodiment, and will not be described here again.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (17)
1. A semiconductor device, comprising:
a substrate having an active region;
A bit line structure formed on the active region; the bit line structure includes a bit line, and an isolation layer formed on the bit line;
The side wall structure is formed on the substrate and surrounds the side wall of the bit line structure, the side wall structure comprises an air side wall and a medium side wall surrounding the air side wall, and the part of the medium side wall located at the top of the air side wall is made of a breathable material; the top height of the air side wall is larger than or equal to the top height of the bit line and smaller than the top height of the isolation layer; the dielectric side walls comprise a first dielectric side wall, a second dielectric side wall and a third dielectric side wall, and the first dielectric side wall and the second dielectric side wall are formed on the substrate; the first dielectric side wall surrounds the side wall of the bit line structure, the second dielectric side wall surrounds the first dielectric side wall, and the third dielectric side wall is formed between the first dielectric side wall and the second dielectric side wall; the first medium side wall, the second medium side wall and the third medium side wall enclose the air side wall; the top height of the third dielectric side wall is larger than or equal to the top height of the bit line and smaller than the top height of the isolation layer.
2. The semiconductor device of claim 1, wherein the gas permeable material is a porous insulating material.
3. The semiconductor device of claim 1, wherein a top height of the air sidewall is less than a top height of the bit line structure.
4. A semiconductor device according to claim 1 or 3, further comprising storage contacts and landing pads formed on the substrate, each of the storage contacts being electrically connected to a corresponding one of the active regions, the landing pads being formed on the storage contacts, a width of the landing pads varying by an amount less than or equal to a preset threshold in a height direction of the landing pads.
5. A method of fabricating a semiconductor device, comprising:
providing a substrate, wherein the substrate is provided with an active area;
Forming a bit line structure on the active region; the bit line structure includes a bit line, and an isolation layer formed on the bit line;
Forming a side wall structure on the substrate, wherein the side wall structure surrounds the side wall of the bit line structure, the side wall structure comprises an air side wall and a medium side wall surrounding the air side wall, and the part of the medium side wall positioned at the top of the air side wall is made of a breathable material; the top height of the air side wall is larger than or equal to the top height of the bit line and smaller than the top height of the isolation layer; the dielectric side walls comprise a first dielectric side wall, a second dielectric side wall and a third dielectric side wall, and the first dielectric side wall and the second dielectric side wall are formed on the substrate; the first dielectric side wall surrounds the side wall of the bit line structure, the second dielectric side wall surrounds the first dielectric side wall, and the third dielectric side wall is formed between the first dielectric side wall and the second dielectric side wall; the first medium side wall, the second medium side wall and the third medium side wall enclose the air side wall; the top height of the third dielectric side wall is larger than or equal to the top height of the bit line and smaller than the top height of the isolation layer.
6. The method of manufacturing a semiconductor device according to claim 5, wherein forming a sidewall structure on the substrate comprises:
Forming a sacrificial layer surrounding the bit line structure sidewall on the substrate;
Forming the medium side wall surrounding the periphery of the sacrificial layer on the substrate;
and removing the sacrificial layer by adopting a dry etching mode to obtain the air side wall.
7. The method of manufacturing a semiconductor device according to claim 6, wherein the dry etching method comprises an ashing method.
8. The method of claim 5, wherein the air sidewall has a height less than a top height of the bit line structure.
9. The method of claim 6, wherein forming a sacrificial layer on the substrate around the sidewall of the bit line structure comprises:
Forming a pre-side wall structure surrounding the periphery of the bit line structure on the substrate, wherein the top height of the pre-side wall structure is larger than or equal to that of the bit line structure, and the pre-side wall structure comprises a first pre-side wall, a second pre-side wall and a third pre-side wall positioned between the first pre-side wall and the second pre-side wall;
carrying out back etching treatment on the pre-side wall structure so as to reserve the first pre-side wall, the second pre-side wall and the third pre-side wall with preset heights on the substrate;
Removing the residual third pre-side wall by adopting a wet etching mode;
Filling sacrificial materials between the remaining first pre-side wall and the remaining second pre-side wall;
and carrying out back etching treatment on the sacrificial material to form a sacrificial layer.
10. The method of manufacturing a semiconductor device according to claim 9, wherein the etching solution used for removing the remaining third pre-sidewall by wet etching includes an HF solution.
11. The method of manufacturing a semiconductor device according to claim 9, wherein a weight molecular weight and/or a concentration of the sacrificial material is adjusted to fill the sacrificial material between the remaining first pre-sidewall and the remaining second pre-sidewall.
12. The method of claim 9, wherein the sacrificial material is etched back to a depth of 10a to 300 a.
13. The method of manufacturing a semiconductor device according to claim 6, wherein forming the dielectric sidewall around the sacrificial layer on the substrate comprises:
Forming a gas-permeable material on the top of the sacrificial layer and on the top and the side wall of the bit line structure by adopting an atomic deposition mode;
And selectively etching the breathable material in a wet etching mode to enable the residual breathable material to form the third medium side wall.
14. The method of manufacturing a semiconductor device according to claim 5, wherein the gas permeable material is a porous insulating material.
15. The method for manufacturing a semiconductor device according to claim 6 or 8, wherein,
After the bit line structure is formed on the active region and before the side wall structure is formed on the substrate, the manufacturing method of the semiconductor device further comprises the following steps:
Forming storage contacts on the substrate, each storage contact being electrically connected to a respective active region;
After the side wall structure is formed on the substrate, the manufacturing method of the semiconductor device further comprises the following steps:
And forming a landing pad on the storage contact part, wherein the width variation of the landing pad is smaller than or equal to a preset threshold value along the height direction of the landing pad.
16. An electronic device comprising the semiconductor device according to any one of claims 1 to 4.
17. The electronic device of claim 16, wherein the electronic device comprises a terminal device or a communication device.
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