CN113689824A - Emission control driver and display device - Google Patents
Emission control driver and display device Download PDFInfo
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- CN113689824A CN113689824A CN202111038288.8A CN202111038288A CN113689824A CN 113689824 A CN113689824 A CN 113689824A CN 202111038288 A CN202111038288 A CN 202111038288A CN 113689824 A CN113689824 A CN 113689824A
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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Abstract
The present disclosure provides an emission control driver and a display device. The emission control driver comprises a multi-stage emission control driving circuit used for outputting emission control signals to corresponding display pixels in the display pixel array, a first stage emission control driving circuit in the multi-stage emission control driving circuit takes an externally input time sequence signal as a trigger signal, and other stages of emission control driving circuits take an emission stage signal output by the first stage emission control driving circuit as the trigger signal. By adopting the technical scheme provided by the disclosure, the emission control driver can output a high-level emission control signal which is in line with expectation to the display panel, and the display quality of the display device is improved.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to an emission control driver and a display device.
Background
With the rapid development of internet technology and mobile communication technology, the world enters a brand new information age, the information content is increasingly rich and colorful, and as an important constituent part of the information industry, the display technology plays an important role in the development process of the information technology all the time. Nowadays, various Display devices are present in many fields of daily life and work, for example, AMOLED (Active Matrix Organic Light Emitting Diode) is considered as a new generation Display technology following LCD (Liquid Crystal Display) devices due to its characteristics of high contrast, high color gamut, wide viewing angle, etc.
For the OLED, the pixel driving circuit has an internal compensation function to compensate the shift of the threshold voltage of the thin film transistor for driving the OLED to emit light, and in the compensation process, an emission control signal is generally required to be provided to control the OLED not to emit light, so as to improve the compensation effect. The emission control signal may be provided by the emission control driver shown in fig. 1 and 2. The emission control driver in fig. 1 is formed by a P-type LTPS TFT (Low-Temperature-Poly-Silicon Thin-Film-Transistor), and the Low level of the output cannot maintain the lowest level, but does not have a significant negative effect on transmitting the high level. However, for the emission control driver composed of the N-type LTPS TFT, as shown in fig. 2, the level of its output cannot reach the desired high level, thus affecting the display quality of the device.
Disclosure of Invention
The present disclosure provides an emission control driver and a display device capable of causing the emission control driver to output a high-level emission control signal according to expectations to a display panel.
In one aspect, the present disclosure provides an emission control driver for displaying a pixel array, the emission control driver including a plurality of stages of emission control driving circuits, wherein each stage of the emission control driving circuits includes:
a first control module configured to control a level of the first node and a level of the second node in response to a trigger signal, a first clock signal, and a second clock signal; an output pull-up module configured to output an emission control signal of a high level to a corresponding display pixel in the display pixel array and output an emission stage transfer signal of a high level to a next stage emission control driving circuit in response to a level of the second node and a first high level signal; a second control module configured to control a level of a third node and a level of a fourth node in response to the first clock signal, the second clock signal, the first high level signal, and a first low level signal; an output pull-down module configured to output an emission control signal of a low level to a corresponding display pixel in the display pixel array and an emission level signal of a low level to a next-stage emission control driving circuit in response to the level of the fourth node, the first low-level signal, and the second low-level signal; the first stage emission control drive circuit in the multi-stage emission control drive circuit takes an externally input time sequence signal as a trigger signal, and the other stages of emission control drive circuits take an emission stage signal output by the first stage emission control drive circuit as the trigger signal.
In some embodiments of the present disclosure, the first control module comprises: the display device includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first capacitor, and a second capacitor.
A gate of the first thin film transistor receives the first clock signal, a first terminal of the first thin film transistor receives the trigger signal, and a second terminal of the first thin film transistor is connected to the first node; a gate and a first terminal of the second thin film transistor are connected to the first node, and a second terminal of the second thin film transistor is connected to the second node; a gate of the third thin film transistor is connected to the third node, a first terminal of the third thin film transistor is connected to the first node, and a second terminal of the third thin film transistor is connected to the second node; a gate of the fourth thin film transistor is connected to the fourth node, a first terminal of the fourth thin film transistor receives the first low-level signal, and a second terminal of the fourth thin film transistor is connected to the first node; a first terminal of the first capacitor receives the second clock signal, and a second terminal of the first capacitor is connected to the first node; a first terminal of the second capacitor receives the first high level signal, and a second terminal of the second capacitor is connected to the second node.
In some embodiments of the present disclosure, the output pull-up module comprises: a fifth thin film transistor and a sixth thin film transistor.
A gate of the fifth thin film transistor is connected to the second node, a first terminal of the fifth thin film transistor receives the first high level signal, and a second terminal of the fifth thin film transistor outputs the high level emitter pass signal; a gate of the sixth thin film transistor is connected to the second node, a first end of the sixth thin film transistor receives the first high level signal, and a second end of the sixth thin film transistor outputs the high level emission control signal
In some embodiments of the present disclosure, the second control module comprises: a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor, a twelfth thin film transistor, a thirteenth thin film transistor, a third capacitor, and a fourth capacitor.
A gate of the ninth thin film transistor is connected to the first node, the ninth thin film transistor receives the first clock signal, and a second terminal of the ninth thin film transistor is connected to the third node; a gate of the tenth thin film transistor receives the first clock signal, a first terminal of the tenth thin film transistor receives the first high level signal, and a second terminal of the tenth thin film transistor is connected to the third node; a gate of the eleventh thin film transistor is connected to the third node, a first terminal of the eleventh thin film transistor receives the second clock signal, and a second terminal of the eleventh thin film transistor is connected to a first terminal of the twelfth thin film transistor; a gate of the twelfth thin film transistor receives the second clock signal, and a second end of the twelfth thin film transistor is connected to the fourth node; a gate of the thirteenth thin film transistor is connected to the second node, a first terminal of the thirteenth thin film transistor receives the first low-level signal, and a second terminal of the thirteenth thin film transistor is connected to the fourth node; a first terminal of the third capacitor is connected to the third node, and a second terminal of the third capacitor is connected to a first terminal of the twelfth thin film transistor; a first terminal of the fourth capacitor receives the first low level signal, and a second terminal of the fourth capacitor is connected to the fourth node.
In some embodiments of the present disclosure, the output pull-down module comprises: a seventh thin film transistor and an eighth thin film transistor.
A gate of the seventh thin film transistor is connected to the fourth node, a first terminal of the seventh thin film transistor receives the first low-level signal, and a second terminal of the seventh thin film transistor outputs the low-level emitter signal; a gate of the eighth thin film transistor is connected to the fourth node, a first end of the eighth thin film transistor receives the second low-level signal, and a second end of the eighth thin film transistor outputs the emission control signal of the low level.
In some embodiments of the present disclosure, the thin film transistor in each stage of the emission control driving circuit is an N-type thin film transistor.
In some embodiments of the present disclosure, the operation process of each stage of the emission control driving circuit driven by the first clock signal varying periodically and the second clock signal varying periodically includes an initialization stage, an output stage, a reset stage and an idle stage.
In the initialization stage, when the trigger signal is at a low level, the first clock signal is at a high level, and the second clock signal is at a low level, the first thin film transistor and the ninth thin film transistor are turned on, so that the level of the first node and the level of the second node are initialized to a low level, and the level of the third node is initialized to a high level;
in the output stage, when the trigger signal is at a low level, the first clock signal is at a low level, and the second clock signal is at a high level, the eleventh thin film transistor and the twelfth thin film transistor are turned on, so that the level of the fourth node is raised to a high level; in response to the high level of the fourth node, the seventh thin film transistor and the eighth thin film transistor are turned on, so that the output pull-down module outputs the low-level emitter signal and the low-level emitter control signal under the action of the first low-level signal and the second low-level signal, respectively.
In the reset and idle stages, when the trigger signal is at a high level, the first clock signal is at a high level, and the second clock signal is at a low level, the first thin film transistor and the third thin film transistor are turned on, and the second thin film transistor is in a diode state, so that the level of the first node and the level of the second node are raised to a high level; in response to a high level of the second node, the thirteenth thin film transistor is turned on, so that a level of the third node is lowered to a low level; in response to the high level of the second node, the fifth thin film transistor and the sixth thin film transistor are turned on, so that the output pull-up module outputs the high-level emitter pass signal and the high-level emission control signal under the action of the first high-level signal;
in the reset and idle stages, when the trigger signal is at a high level, the first clock signal is at a low level, and the second clock signal is at a high level, the level of the first node is increased under the coupling action of the first capacitor, and then the first node is shunted to the second node through the second thin film transistor in a conducting state, so that the level of the second node is increased;
in the reset and idle stages, the level of the second node is gradually increased under the action of the first clock signal and the second clock signal which are periodically changed, and the high-level transmitting stage transmission signal and the high-level transmitting control signal output by the output pull-up module conform to an expected high-level signal in response to the change of the level of the second node.
In some embodiments of the present disclosure, the expected high level signal is the first high level signal.
In some embodiments of the present disclosure, each of the emission control driving circuits has a plurality of pins connected to an outside to receive the first high level signal, the first low level signal, the second low level signal, the first clock signal, and the second clock signal, wherein two clock pins of the plurality of pins of the emission control driving circuits of the odd-numbered stages are sequentially connected to a signal terminal of the first clock and a signal terminal of the second clock, and two clock pins of the plurality of pins of the emission control driving circuits of the even-numbered stages are sequentially connected to a signal terminal of the second clock and a signal terminal of the first clock.
Accordingly, the present disclosure provides a display device comprising any of the emission control drivers as described above. Illustratively, the display device further includes a timing controller for supplying a first clock signal and a second clock signal to the emission control driver to cause the emission control driver to supply the emission control signal to the display panel.
Compared with the prior art, the emission control driver provided by the disclosure can stably output the expected high-level emission control signal to the display panel, so that the display quality of the display device is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other embodiments based on the drawings without creative efforts.
Fig. 1 is a schematic diagram of an nth stage transmission circuit in a conventional transmission control driver composed of P-type LTPS TFTs;
fig. 2 is a schematic diagram of an nth stage transmission circuit in a conventional transmission control driver composed of N-type LTPS TFTs;
fig. 3 is a schematic structural diagram of a display device according to an embodiment of the disclosure;
fig. 4 is a schematic structural diagram of a sub-pixel driving circuit according to an embodiment of the disclosure;
fig. 5 is a schematic diagram of a cascade structure of an emission control driver provided in an embodiment of the present disclosure;
fig. 6 is a schematic configuration diagram of an nth-stage emission control driving circuit of the emission control driver shown in fig. 5;
fig. 7 is an operation waveform diagram of an nth-stage emission control driving circuit of the emission control driver shown in fig. 5.
Description of reference numerals:
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure. Furthermore, it should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, and are not intended to limit the present disclosure. In the present disclosure, unless otherwise specified, use of the directional terms "upper" and "lower" generally refer to upper and lower, and specifically to the orientation of the drawing figures in the drawings, in the actual use or operating condition of the device; while "inner" and "outer" are with respect to the outline of the device.
The present disclosure provides an emission control driver applicable to at least an organic light emitting display device. Therefore, before describing the emission control driver provided in the present disclosure, the structure and the operation principle of the display device to which the emission control driver is applied will be described first.
Fig. 3 is a schematic structural diagram of a display device according to an embodiment of the present disclosure, where the display device is an organic light emitting display device.
Specifically, as shown in fig. 3, the organic light emitting display device includes a timing controller 100, a data driver 110, an emission control driver 120, a scan control driver 130, and a display panel 140.
The timing controller 100 is configured to provide working driving signals to the data driver 110, the emission control driver 120, the scan control driver 130 and the display panel 140, so that the data driver 110 provides a data writing signal to the display panel 140, the emission control driver 120 provides an emission control signal to the display panel 140, and the scan control driver 130 provides a scan driving signal to the display panel 140.
Further, the display panel 140 includes an array substrate (not shown), and the display panel 140 can be divided into a display area and a non-display area (not shown), and a portion of the array substrate corresponding to the display area is formed by a plurality of pixel driving circuits distributed in an array. Each pixel driving circuit includes a plurality of sub-pixel driving circuits for driving corresponding sub-pixel units to emit light, and for the organic light emitting display device, the sub-pixel units are usually disposed in an organic light emitting layer of the display panel. The sub-pixel driving circuit generates a constant current under the action of the scanning driving signal, the data writing signal and the emission control signal, and the corresponding organic light emitting device (sub-pixel unit) emits light under the driving of the constant current.
Specifically, please refer to fig. 4, which is a schematic structural diagram of a sub-pixel driving circuit according to an embodiment of the present disclosure.
It should be noted that, in the sub-pixel driving circuit provided by this example, the first driving switching tube T1, the second auxiliary switching tube T2, and the third auxiliary switching tube T3 are all N-type thin film transistors. It is understood that, for an N-type thin film transistor, applying a high voltage to its gate can control its source and drain to be on, and applying a low voltage to its gate can control the channel between its source and drain to be off.
In the data writing stage of the sub-pixel driving circuit during operation, the emission control driver 120 outputs a low-level emission control signal EM [ i ] to control the turn-off of T3 in the sub-pixel driving circuit of the ith row, so that the corresponding organic light emitting device D1 does not emit light; the SCAN control driver 130 outputs a SCAN control signal SCAN [ i ] of a high level to control T2 in the subpixel driving circuit of the ith row to be turned on; the DATA driver 110 outputs a DATA write signal DATA [ j ] to write a corresponding DATA voltage to the gate of T1 and the storage capacitor C1 of the sub-pixel driving circuit located at the ith row and the jth column.
Further, in the light-emitting driving stage of the sub-pixel driving circuit during operation, the SCAN control driver 130 outputs SCAN [ i ] at a low level, and controls T2 to turn off; emission control driver 120 outputs high level EM [ i ], controlling T3 to conduct; the T1 is turned on by the first power signal ELVDD and generates a current corresponding to the written data voltage, and then drives the organic light emitting device D1 to emit light with a corresponding brightness through the T3 in the on state.
It follows that the light emission period of the sub-pixel unit is associated with the emission control driver.
In a display device, in order to precisely control each sub-pixel unit, an emission control driver generally includes a multi-stage emission circuit.
Fig. 5 is a schematic diagram of a cascade structure of an emission control driver according to an embodiment of the present disclosure.
As shown, the emission control driver includes n stages of emission control driving circuits, which are respectively represented by stage [1], stage [2], stage [3], … …, stage [ n-1], and stage [ n ].
The emission control driving circuit of each stage is connected to the first high level signal terminal, the first low level signal terminal, and the second low level signal terminal to receive the first high level signal VGH, the first low level signal VGL1, and the second low level signal VGL 2.
And the emission control driving circuit of the odd-numbered stage is sequentially connected with the first clock signal terminal and the second clock signal terminal to sequentially receive the first clock signal CK and the second clock signal XCK. The even-numbered stages of emission control driving circuits are sequentially connected with the second clock signal terminal and the first clock signal terminal to sequentially receive the second clock signal XCK and the first clock signal CK.
Furthermore, the emission control driving circuit of each stage outputs an emission stage signal EMC and an emission control signal EM through an emission stage signal end and an emission control signal end, respectively.
Illustratively, stage [ i ] outputs EMC [ i ] and EM [ i ], i being positive integers. Wherein, EM [ i ] is provided for the sub-pixel driving circuit in the ith stage (row) pixel driving circuit to control the on or off of the first end of the T3 source in the sub-pixel driving circuit, thereby controlling the light-emitting time period of the corresponding sub-pixel unit.
EMC [ i ] is supplied to the emission control drive circuit of the next stage as a trigger signal. Note that, since the stage [1] does not have a previous stage emission control driving circuit, the stage [1] uses a frame start signal (STV signal) supplied from the timing controller 100 as a trigger signal.
In order to solve the problem that an emission control driving circuit composed of N-type thin film transistors cannot output an expected high level signal and the high level signal is significantly reduced in a transmission process, the present disclosure provides a novel emission control driving circuit based on an emission control driver of a cascade structure shown in fig. 5, wherein the nth stage emission control driving circuit is structured as shown in fig. 6.
Specifically, as shown in fig. 6, the emission control drive circuit provided by the present disclosure includes: a first control module 131, an output pull-up module 132, an output pull-down module 133, and a second control module 134.
Wherein the first control module 131 includes: a first thin film transistor T11, a second thin film transistor T12, a third thin film transistor T13, a fourth thin film transistor T14, a first capacitor C11, and a second capacitor C12.
The output pull-up module 132 includes: a fifth thin film transistor T21, and a sixth thin film transistor T22.
The output pull-down module 133 includes: a seventh thin film transistor T31, and an eighth thin film transistor T32.
The second control module 134 includes: a ninth thin film transistor T41, a tenth thin film transistor T42, an eleventh thin film transistor T43, a twelfth thin film transistor T44, a thirteenth thin film transistor T45, a third capacitor C41, and a fourth capacitor C42.
It should be noted that, the thin film transistors in the novel emission control driving circuit provided by the present disclosure are all N-type thin film transistors. It is understood that, for an N-type thin film transistor, applying a high voltage to its gate can control its source and drain to be on, and applying a low voltage to its gate can control the channel between its source and drain to be off. In addition, the thin film transistor may include a first terminal and a second terminal, which are symmetrically disposed, in addition to the gate electrode, and both the first terminal and the second terminal may operate as a source electrode or a drain electrode according to a received signal.
With reference to fig. 6, the structure of each module in the emission control driving circuit will be described.
In the first control module 131:
the gate of T11 is connected to the first clock signal terminal for receiving CK; a first terminal of the T11 is connected to a transmission stage signal terminal of an n-1 th stage (previous stage) transmission control drive circuit to receive EMC [ n-1 ]; a second end of T11 is connected to a first node Q1.
The gate of T12 is connected to Q1; a first end of T12 is connected to Q1; a second end of T12 is connected to a second node Q2.
The gate of T13 is connected to the third node QB 1; a first end of T13 is connected to Q1; the second end of T13 is connected to Q2.
The gate of T14 is connected to the fourth node QB 2; a first terminal of T14 is connected to the first low signal terminal to receive VGL 1; the second end of T14 is connected to Q1.
A first terminal of C11 is connected to the second clock signal terminal for receiving XCK; the second end of C11 is connected to Q1.
A first end of the C12 is connected to the first high level signal end to receive VGH; the second end of C12 is connected to Q2.
In the output pull-up module 132:
the gate of T21 is connected to Q2; a first terminal of T21 is connected to the first high level signal terminal to receive VGH; the second terminal of T21 is connected to the transmission stage signal terminal of the nth stage (present stage) transmission control drive circuit to output EMC [ n ].
The gate of T22 is connected to Q2; a first terminal of T22 is connected to the first high level signal terminal to receive VGH; the second terminal of T22 is connected to the emission control signal terminal of the nth stage (present stage) emission control drive circuit to output EM [ n ].
In the output pulldown module 133:
the gate of T31 is connected to QB 2; a first terminal of T31 is connected to the first low signal terminal to receive VGL 1; the second terminal of T31 is connected to the transmission stage signal terminal of the nth stage (present stage) transmission control drive circuit to output EMC [ n ].
The gate of T32 is connected to QB 2; a first terminal of T31 is connected to the second low signal terminal to receive VGL 2; the second terminal of T31 is connected to the emission control signal terminal of the nth stage (present stage) emission control drive circuit to output EM [ n ].
In the second control module 134:
the gate of T41 is connected to Q1; a first terminal of T41 is connected to the first clock signal terminal for receiving CK; the second end of T41 is connected to QB 1.
The gate of T42 is connected to the first clock signal terminal for receiving CK; a first terminal of T42 is connected to the first high level signal terminal to receive VGH; the second end of T42 is connected to QB 1.
The gate of T43 is connected to QB 1; a first terminal of T43 is connected to the second clock signal terminal for receiving XCK; the second end of T43 is connected to the first end of T44.
The gate of T44 is connected to the second clock signal terminal for receiving XCK; the second end of T44 is connected to QB 2.
The gate of T45 is connected to Q2; a first terminal of T45 is connected to the first low signal terminal to receive VGL 1; the second end of T45 is connected to QB 2.
The first end of C41 is connected to QB 1; the second end of C41 is connected to both the second end of T43 and the first end of T44.
A first terminal of the C42 is connected to the first low signal terminal to receive VGL 1; the second end of C42 is connected to QB 2.
Further, referring to fig. 7 in combination, the operation process of the novel emission control driving circuit provided by the present disclosure mainly includes an initialization phase (t)1) An output stage (t)2) Reset and idle phases (t)3)。
In the initialization phase:
when EMC [ n-1] is low, CK is high, and XCK is low, T11 and T41 conduct.
For T11, since EMC [ n-1] is low at this time, Q1 is discharged to low.
For T41, since CK is high at this time, QB1 is charged high.
QB1 is high, controlling T13, T43 to conduct.
For T13, since Q1 has been discharged to a low level at this time, Q2 is discharged to a low level, keeping T21, T22 off.
When EMC [ n-1] is low, CK, and XCK are all low, Q1, Q2, and QB2 are all low, QB1 is kept high by C41, and the initialization process of each node is finished.
In the output stage:
t44 is conductive when EMC [ n-1] is low, CK is low, and XCK is high.
For T44, since QB1 is high at this time, T43 is controlled to be on, and therefore QB2 is charged only high.
QB2 is high to control T14, T31 and T32 to turn on.
For T31, the output pull-down module 133 in the nth stage (present stage) emission control drive circuit outputs EMC [ n ] of a low level by the action of VGL 1.
For T32, the output pull-down block 133 in the nth stage (present stage) emission control drive circuit outputs EM [ n ] of a low level by the action of VGL 2.
As can be seen from fig. 7, in the whole output stage, under the action of CK and XCK which change periodically, the output pull-down module 133 of the nth stage (this stage) emission control driving circuit continuously outputs EMC [ n ] of low level to the (n + 1) th stage (next stage) emission control driving circuit.
In the reset and idle phases:
when EMC [ n-1] is high, CK is high, and XCK is low, T11, T42 are conductive.
For T11, since EMC [ n-1] at this time is high, Q1 is charged high.
Q1 is high, and T12 and T41 are controlled to be conducted.
QB1 is high, controlling T13 to turn on.
For T13, since Q1 is high at this time, Q2 is charged high.
Q2 is high, and controls T21, T22 and T45 to be conductive.
For T45, QB2 is discharged to low level by VGL1, and T31, T32 are turned off.
For T21, the emission stage signal terminal of the nth stage (present stage) emission control drive circuit outputs EMC [ n ] of high level under the action of VGH.
For T22, the emission control signal terminal of the nth stage (present stage) emission control drive circuit outputs EM [ n ] at a high level under the action of VGH.
When EMC [ n-1] is high, CK is low, and XCK is high, the level of Q1 rises under the coupling action of C11, so that a voltage difference exists between Q1 and Q2, and since T12 of the diode structure is in a conducting state at this time, a shunt phenomenon occurs between Q1 and Q2, the level of Q1 falls, and the level of Q2 rises. When the voltage difference between Q1 and Q2 is equal to the threshold voltage of T12, the levels of Q1 and Q2 are each stable.
Since the level of Q2 fails to reach a level comparable to VGH, typically lower than VGH, just as the reset and idle phases are entered. If the level of Q2 remains unchanged, then EMC [ n ] output by the pull-up module 132 is finally output]And EM [ n ]]Is below VGH. Because, V when T21(T22)gs＝VthAt this time, T21(T22) is turned off, and V of T21(T22) is at this timesIs equal to VQ2-VthTherefore, EMC [ n ] output in this case]And EM [ n ]]Is equal to VsAnd is smaller than VGH.
However, for the emission control driving circuit provided in the present disclosure, when XCK is switched to high level, the coupling effect of Q1 at C11 increases the level, and Q1 shunts to Q2 through T12, so that Q2 rises in level, and thus EMC [ n ] and EM [ n ] output by the output pull-up module 132 rises in level.
Further, under the action of CK and XCK, which are alternately changed, the level of Q2 is gradually increased, and accordingly EMC [ n ] and EM [ n ] output by the output pull-up module 132 can also be gradually increased to VGH.
For the sub-pixel driving circuit in the display panel, the higher level of EM can prolong the time that T3 is turned on, i.e., the light emitting time period of the corresponding sub-pixel unit (e.g., organic light emitting device).
It is understood that in other embodiments of the present disclosure, the specific potential values of EMC [ n ] and EM [ n ] output by the output pull-up module 132 need to correspond to the required light-emitting duration of the sub-pixel cell it indirectly controls, and are not limited to VGH as described above.
In addition, during the whole reset and idle phases, since Q1 is high, T41 is kept in a conducting state, when CK is switched from high level to low level, QB1 is discharged to low level, and T13 is turned off. With the periodic variation of CK, the reset process of each node is ended, i.e., Q1, Q2 are stably at high level, QB1, QB2 are stably at low level, the operation of the emission control driving circuit enters an idle state, and the outputs continuously and stably conform to the expected high levels EMC [ n ] and EM [ n ] through the output pull-up module 132, respectively.
Further, the present disclosure provides a display device including any of the emission control drivers described above.
The emission control driver and the display device provided by the embodiments of the present disclosure are described in detail above, and the principles and embodiments of the present disclosure are explained herein by applying specific examples, and the above description of the embodiments is only used to help understanding the method and the core idea of the present disclosure; meanwhile, for those skilled in the art, according to the idea of the present disclosure, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present description should not be construed as a limitation to the present disclosure.
Claims (10)
1. An emission control driver for a display pixel array, the emission control driver comprising a plurality of stages of emission control driving circuits, wherein each stage of emission control driving circuits comprises:
a first control module configured to control a level of the first node and a level of the second node in response to a trigger signal, a first clock signal, and a second clock signal;
an output pull-up module configured to output an emission control signal of a high level to a corresponding display pixel in the display pixel array and output an emission stage transfer signal of a high level to a next stage emission control driving circuit in response to a level of the second node and a first high level signal;
a second control module configured to control a level of a third node and a level of a fourth node in response to the first clock signal, the second clock signal, the first high level signal, and a first low level signal;
an output pull-down module configured to output an emission control signal of a low level to a corresponding display pixel in the display pixel array and an emission level signal of a low level to a next-stage emission control driving circuit in response to the level of the fourth node, the first low-level signal, and the second low-level signal;
the first stage emission control drive circuit in the multi-stage emission control drive circuit takes an externally input time sequence signal as a trigger signal, and the other stages of emission control drive circuits take an emission stage signal output by the first stage emission control drive circuit as the trigger signal.
2. The launch control driver of claim 1, wherein the first control module comprises: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first capacitor, and a second capacitor;
a gate of the first thin film transistor receives the first clock signal, a first terminal of the first thin film transistor receives the trigger signal, and a second terminal of the first thin film transistor is connected to the first node;
a gate and a first terminal of the second thin film transistor are connected to the first node, and a second terminal of the second thin film transistor is connected to the second node;
a gate of the third thin film transistor is connected to the third node, a first terminal of the third thin film transistor is connected to the first node, and a second terminal of the third thin film transistor is connected to the second node;
a gate of the fourth thin film transistor is connected to the fourth node, a first terminal of the fourth thin film transistor receives the first low-level signal, and a second terminal of the fourth thin film transistor is connected to the first node;
a first terminal of the first capacitor receives the second clock signal, and a second terminal of the first capacitor is connected to the first node;
a first terminal of the second capacitor receives the first high level signal, and a second terminal of the second capacitor is connected to the second node.
3. The launch control driver of claim 1, wherein the output pull-up module comprises: a fifth thin film transistor and a sixth thin film transistor;
a gate of the fifth thin film transistor is connected to the second node, a first end of the fifth thin film transistor receives the first high-level signal, and a second end of the fifth thin film transistor outputs the high-level emitter signal;
a gate of the sixth thin film transistor is connected to the second node, a first end of the sixth thin film transistor receives the first high level signal, and a second end of the sixth thin film transistor outputs the emission control signal of the high level.
4. The launch control driver of claim 1, wherein the second control module comprises: a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor, a twelfth thin film transistor, a thirteenth thin film transistor, a third capacitor, and a fourth capacitor;
a gate of the ninth thin film transistor is connected to the first node, the ninth thin film transistor receives the first clock signal, and a second terminal of the ninth thin film transistor is connected to the third node;
a gate of the tenth thin film transistor receives the first clock signal, a first terminal of the tenth thin film transistor receives the first high level signal, and a second terminal of the tenth thin film transistor is connected to the third node;
a gate of the eleventh thin film transistor is connected to the third node, a first terminal of the eleventh thin film transistor receives the second clock signal, and a second terminal of the eleventh thin film transistor is connected to a first terminal of the twelfth thin film transistor;
a gate of the twelfth thin film transistor receives the second clock signal, and a second end of the twelfth thin film transistor is connected to the fourth node;
a gate of the thirteenth thin film transistor is connected to the second node, a first terminal of the thirteenth thin film transistor receives the first low-level signal, and a second terminal of the thirteenth thin film transistor is connected to the fourth node;
a first terminal of the third capacitor is connected to the third node, and a second terminal of the third capacitor is connected to a first terminal of the twelfth thin film transistor;
a first terminal of the fourth capacitor receives the first low level signal, and a second terminal of the fourth capacitor is connected to the fourth node.
5. The launch control driver of claim 1, wherein the output pulldown module comprises: a seventh thin film transistor and an eighth thin film transistor;
a gate of the seventh thin film transistor is connected to the fourth node, a first end of the seventh thin film transistor receives the first low-level signal, and a second end of the seventh thin film transistor outputs the low-level emitter signal;
a gate of the eighth thin film transistor is connected to the fourth node, a first end of the eighth thin film transistor receives the second low-level signal, and a second end of the eighth thin film transistor outputs the emission control signal of the low level.
6. The emission control driver according to any one of claims 2 to 5, wherein the thin film transistor in the emission control driving circuit of each stage is an N-type thin film transistor.
7. The emission control driver of claim 6, wherein the operation process of each stage of the emission control driving circuit driven by the first clock signal varying periodically and the second clock signal varying periodically comprises an initialization stage, an output stage, a reset stage and an idle stage;
in the initialization stage, when the trigger signal is at a low level, the first clock signal is at a high level, and the second clock signal is at a low level, the first thin film transistor and the ninth thin film transistor are turned on, so that the level of the first node and the level of the second node are initialized to a low level, and the level of the third node is initialized to a high level;
in the output stage, when the trigger signal is at a low level, the first clock signal is at a low level, and the second clock signal is at a high level, the eleventh thin film transistor and the twelfth thin film transistor are turned on, so that the level of the fourth node is raised to a high level; in response to the high level of the fourth node, the seventh thin film transistor and the eighth thin film transistor are turned on, so that the output pull-down module outputs the low-level emitter signal and the low-level emitter control signal under the action of the first low-level signal and the second low-level signal, respectively.
8. The emission control driver of claim 7,
in the reset and idle stages, when the trigger signal is at a high level, the first clock signal is at a high level, and the second clock signal is at a low level, the first thin film transistor and the third thin film transistor are turned on, and the second thin film transistor is in a diode state, so that the level of the first node and the level of the second node are raised to a high level; in response to a high level of the second node, the thirteenth thin film transistor is turned on, so that a level of the third node is lowered to a low level; in response to the high level of the second node, the fifth thin film transistor and the sixth thin film transistor are turned on, so that the output pull-up module outputs the high-level emitter pass signal and the high-level emission control signal under the action of the first high-level signal;
in the reset and idle stages, when the trigger signal is at a high level, the first clock signal is at a low level, and the second clock signal is at a high level, the level of the first node is raised under the coupling effect of the first capacitor, and then the first node is shunted to the second node through the second thin film transistor in a conducting state, so that the level of the second node is raised;
in the reset and idle stages, the level of the second node is gradually increased under the action of the first clock signal and the second clock signal which are periodically changed, and the high-level emission control signal output by the output pull-up module corresponds to an expected high-level signal in response to the change of the level of the second node.
9. The emission control driver of claim 8, wherein each of the emission control driving circuits has a plurality of pins connected to an outside to receive the first high level signal, the first low level signal, the second low level signal, the first clock signal, and the second clock signal, wherein two clock pins of the plurality of pins of the emission control driving circuits of the odd-numbered stages are sequentially connected to a signal terminal of the first clock and a signal terminal of the second clock, and two clock pins of the plurality of pins of the emission control driving circuits of the even-numbered stages are sequentially connected to a signal terminal of the second clock and a signal terminal of the first clock.
10. A display device characterized in that the display device comprises the emission control driver as claimed in any one of claims 1 to 9.
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