CN113687549A - Display panel, manufacturing method of display panel and display device - Google Patents
Display panel, manufacturing method of display panel and display device Download PDFInfo
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- CN113687549A CN113687549A CN202111115625.9A CN202111115625A CN113687549A CN 113687549 A CN113687549 A CN 113687549A CN 202111115625 A CN202111115625 A CN 202111115625A CN 113687549 A CN113687549 A CN 113687549A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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Abstract
The embodiment of the application provides a display panel, a manufacturing method of the display panel and a display device. The pixel units are positioned on the substrate and distributed in a matrix manner, and at least one pixel unit comprises a transistor and a pixel electrode connected with the transistor; the first insulating layer is positioned on one side of the transistor far away from the substrate base plate; the second insulating layer is located on one side, far away from the transistor, of the first insulating layer, a first through hole is formed in the second insulating layer, the pixel electrode is connected with the transistor through the first through hole, the first through hole comprises a first hole section penetrating through the first insulating layer and a second hole section penetrating through the second insulating layer, and the second insulating layer covers at least part of the hole wall of the first hole section. Among the above-mentioned display panel, the second insulating layer covers at least part pore wall of first hole section, and the pore wall of first via hole is gentler, and the pore wall is laminated more to the pixel electrode, reduces display panel and takes place the probability that shows badly.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display panel, a method for manufacturing the display panel, and a display device.
Background
Because of the advantages of large area, high integration level, high resolution, low power consumption, and the like, TFT-LCD (Thin Film Transistor-Liquid Crystal Display) devices are receiving more and more attention as the basis of the new generation of Display devices.
In the related art, a pixel unit of a TFT-LCD display panel includes a transistor, a pixel electrode, and a common electrode. The pixel electrode can be connected with the transistor through the via structure, and when the pixel electrode is connected with the transistor, poor connection is easily caused due to factors such as poor contact between the pixel electrode and the hole wall of the via structure, and poor display of the display panel is further caused.
Disclosure of Invention
An object of the present invention is to provide a display panel, a method for manufacturing the display panel, and a display device, so as to reduce the probability of display defects of the display panel. The specific technical scheme is as follows:
embodiments of a first aspect of the present application provide a display panel, comprising:
the pixel structure comprises a substrate base plate and a plurality of pixel units which are positioned on the substrate base plate and distributed in a matrix manner, wherein at least one pixel unit comprises a transistor and a pixel electrode connected with the transistor;
a first insulating layer on a side of the transistor remote from the substrate base plate;
the second insulating layer, the second insulating layer is located keeping away from of first insulating layer one side of transistor, be equipped with first via hole on the second insulating layer, the pixel electrode passes through first via hole with the transistor is connected, first via hole is including running through the first hole section of first insulating layer and running through the second hole section of second insulating layer, the second insulating layer covers at least part pore wall of first hole section.
In some embodiments, at least one transistor includes a first metal layer including a gate electrode, a gate insulating layer, a second metal layer including a source electrode and a drain electrode, and an active layer on one side of the substrate, and the pixel electrode is connected to the drain electrode through the first via hole.
In some embodiments, the second insulating layer completely covers the pore walls of the first pore section, and the second insulating layer is in contact with the drain.
In some embodiments, at least one pixel unit further includes a common electrode disposed opposite to the pixel electrode, a second via hole is disposed on the second insulating layer, and the common electrode is connected to the gate through the second via hole.
In some embodiments, the second via includes a third hole segment through the first insulating layer, a fourth hole segment through the second insulating layer, and a fifth hole segment through the gate insulating layer, the second insulating layer covering hole walls of the third and fifth hole segments.
In some embodiments, the common electrodes of at least some of the pixel cells are connected.
In some embodiments, the common electrode and the pixel electrode are both transparent metal oxide electrodes.
In some embodiments, the material of the first insulating layer comprises silicon nitride, and the material of the second insulating layer comprises resin.
A second aspect of the embodiments of the present application provides a method for manufacturing a display panel, where the method for manufacturing a display panel includes:
providing a substrate base plate;
forming a transistor on one side of the substrate base plate;
forming a first insulating layer on one side of the transistor far away from the substrate base plate;
forming a second insulating layer on one side of the first insulating layer, which is far away from the transistor;
forming a first via hole on the second insulating layer, the first via hole comprising a first hole section penetrating through the first insulating layer and a second hole section penetrating through the second insulating layer;
heating the second insulating layer at a preset temperature to enable the second insulating layer to flow and cover at least part of the hole wall of the first hole section;
and forming a pixel electrode, wherein the pixel electrode is connected with the transistor through the first through hole.
In some embodiments, the predetermined temperature is 200 to 250 degrees celsius.
A third aspect of embodiments of the present application provides a display device, which is characterized by including any one of the display panels described above.
The embodiment of the application has the following beneficial effects:
according to the display panel, the manufacturing method of the display panel and the display device, the display panel comprises a substrate base plate and a plurality of pixel units located on the substrate base plate. The pixel unit includes a transistor and a pixel electrode connected to the transistor. The display panel further comprises a first insulating layer positioned on the transistor of the pixel unit and a second insulating layer positioned on the first insulating layer. The second insulating layer is provided with a first via hole, so that the pixel electrode can be connected with the transistor through the second via hole. The first via hole comprises a first hole section and a second hole section which respectively penetrate through the first insulating layer and the second insulating layer, and the second insulating layer covers at least part of the hole wall of the first hole section. In the display panel provided by the embodiment of the application, the second hole section penetrates through the second insulating layer, and the second insulating layer covers at least part of the hole wall of the first hole section, so that the second insulating layer at least partially covers the joint of the first hole section and the second hole section, and the hole wall of the first via hole is smooth. Based on this, when the pixel electrode is connected with the transistor of the pixel unit through the first via hole, the pixel electrode can be attached to the hole wall of the first via hole, so that the probability of poor contact between the pixel electrode and the hole wall of the first via hole is reduced, the probability of poor connection between the pixel electrode and the transistor is reduced, and the probability of poor display of the display panel is reduced.
Of course, not all advantages described above need to be achieved at the same time in the practice of any one product or method of the present application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and it is also obvious for a person skilled in the art to obtain other embodiments according to the drawings.
FIG. 1 is a schematic diagram of a display panel according to the related art;
FIG. 2 is a schematic view of a display panel according to some embodiments of the present disclosure;
FIG. 3 is a cross-sectional view taken along the line A-A in FIG. 2;
FIG. 4 is another cross-sectional view taken along the line A-A in FIG. 2;
FIG. 5 is a further sectional view taken along line A-A of FIG. 2;
fig. 6 is a flowchart of a method for manufacturing a display panel according to some embodiments of the present disclosure.
Reference numerals: 100-a display panel; 200-a light emitting layer; 210-an organic light emitting layer; 300-a liquid crystal layer; 1-a substrate base plate; 2-pixel cells; 21-a transistor; 211 — a first metal layer; 2111-gate; 212-gate insulation layer; 213-a second metal layer; 2131-a source; 2132-a drain electrode; 214-an active layer; 22-pixel electrodes; 23-a common electrode; 3-a first insulating layer; 4-a second insulating layer; 5-a first via; 51-a first bore section; 52-a second bore section; 6-a second via; 61-a third pore section; 62-a fourth pore section; 63-fifth hole section.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the description herein are intended to be within the scope of the present disclosure.
It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element may also be present. Like reference numerals refer to like elements throughout.
In the related art, as shown in fig. 1, the display panel includes a substrate base 1 ' and a pixel unit 2 ' on the substrate base 1 ', and the pixel unit 2 ' includes a transistor 21 ' and a pixel electrode 22 ' connected to the transistor 21 '. The display panel further includes a first insulating layer 3 ' on the transistor 21 ' and a second insulating layer 4 ' on the first insulating layer 3 ', the second insulating layer 4 ' having a via structure 5 ' provided thereon, and the pixel electrode 22 ' being connected to the transistor 21 ' through the via structure 5 '. In the related art, since the first insulating layer 3 'and the second insulating layer may be made of different materials, when the via hole structure 5' is formed, the second hole segment 52 'of the via hole structure 5' may be formed on the second insulating layer by using techniques such as exposure and development, and then the first insulating layer 3 'may be processed by using methods such as etching to form the first hole segment 51' of the via hole structure 5 ', so as to form the via hole structure 5'. After the first insulating layer is etched, as shown in fig. 1, an inverse section may be formed on the first hole segment 51 ' of the first insulating layer 3 ', that is, the hole wall of the first hole segment 51 ' is not located on the same plane as the hole wall of the second hole segment 52 ', and therefore, when the pixel electrode 22 ' is connected to the transistor 21 ' through the via structure 5 ', poor contact is easily generated between the pixel electrode 22 ' and the hole wall of the first hole segment 51 ', which results in poor overlapping between the pixel electrode 22 ' and the transistor 21 ', and thus poor display of the display panel.
Therefore, in order to reduce the probability of the display panel having the display failure, embodiments of the present application provide a display panel, a method for manufacturing the display panel, and a display device. The Display panel includes, but is not limited to, an OLED (Organic Light-Emitting Display), a QLED (Quantum Dot Light-Emitting Display), a Quantum Dot Light-Emitting Display, a TFT-LCD (Thin Film Transistor-Liquid Crystal Display), and the like.
As shown in fig. 2 and fig. 3, an embodiment of the first aspect of the present application provides a display panel 100, where the display panel 100 includes a substrate 1, a plurality of pixel units 2, a first insulating layer 3, and a second insulating layer 4. The pixel units 2 are located on the substrate 1 and distributed in a matrix, and at least one pixel unit 2 includes a transistor 21 and a pixel electrode 22 connected to the transistor 21. The first insulating layer 3 is located on the side of the transistor 21 remote from the base substrate 1. The second insulating layer 4 is located on one side of the first insulating layer 3, which is far away from the transistor 21, a first via hole 5 is formed in the second insulating layer 4, the pixel electrode 22 is connected with the transistor 21 through the first via hole 5, the first via hole 5 includes a first hole section 51 penetrating through the first insulating layer 3 and a second hole section 52 penetrating through the second insulating layer 4, and the second insulating layer 4 covers at least a part of a hole wall of the first hole section 51.
In the display panel 100 provided in the embodiment of the application, the second insulating layer 4 is provided with the first via hole 5, so that the pixel electrode 22 of the pixel unit 2 can be connected to the transistor 21 through the first via hole 5. The first via hole 5 includes a first hole section 51 and a second hole section 52 penetrating through the first insulating layer 3 and the second insulating layer 4, respectively, and the second insulating layer 4 covers at least a part of a hole wall of the first hole section 51. The second hole section 52 penetrates through the second insulating layer 4, and the second insulating layer 4 covers at least part of the hole wall of the first hole section 51, so that the second insulating layer 4 at least partially covers the joint of the first hole section 51 and the second hole section 52, and the hole wall of the first via hole 5 is smooth. Based on this, when the pixel electrode 22 is connected to the transistor 21 of the pixel unit 2 through the first via hole 5, the pixel electrode 22 can be more attached to the hole wall of the first via hole 5, so that the probability of poor contact between the pixel electrode 22 and the hole wall of the first via hole 5 is reduced, the probability of poor connection between the pixel electrode 22 and the transistor 21 is further reduced, and the probability of poor display of the display panel 100 is reduced.
The substrate 1 may be a rigid substrate, such as a glass substrate. The substrate 1 may also be a flexible substrate, such as a polyimide substrate, and the like, which is not particularly limited in this embodiment.
Further, the material of the first insulating layer 3 includes silicon nitride (SiNx), and the material of the second insulating layer 4 includes resin. Here, since the materials of the first insulating layer 3 and the second insulating layer 4 may be different, when the first via hole 5 is formed on the second insulating layer 4, the second hole segment 52 of the first via hole 5 needs to be formed on the second insulating layer 4, and then the first hole segment 51 needs to be further formed on the first insulating layer 3, so as to form the first via hole 5. Specifically, taking the material of the first insulating layer 3 as SiNx and the material of the second insulating layer 4 as resin as an example, when the first via hole 5 is formed in the second insulating layer 4, a second hole section 52 penetrating through the second insulating layer 4 is formed in the second insulating layer 4 by exposure and development, and then a first hole section 51 penetrating through the first insulating layer 3 is formed in the first insulating layer 3 by dry etching. Since the material of the second insulating layer 4 is resin, after the first via hole 5 is formed, the second insulating layer 4 is heated at a high temperature of 200 to 250 ℃, so that the second insulating layer 4 flows and covers the etched edge of SiNx, even if the second insulating layer 4 flows to cover the hole wall of the first hole section 51 and the joint of the first hole section 51 and the second hole section 52. The second insulating layer 4 is then cured under the effect of elevated temperature. Based on this, a relatively gentle transition is formed at the first hole section 51 and the second hole section 52, so that the hole wall of the first via hole 5 is more flat. In a specific embodiment, the second insulating layer 4 may be heated with a high temperature of 230 degrees celsius.
In some embodiments, as shown in fig. 3, at least one transistor 21 includes a first metal layer 211, a gate insulating layer 212, a second metal layer 213 and an active layer 214 on one side of the substrate base plate 1. The first metal layer 211 includes a gate 2111, the second metal layer 213 includes a source 2131 and a drain 2132, and the pixel electrode 22 is connected to the drain 2132 through a first via 5.
In the embodiment of the present application, the pixel electrode 22 is disposed on the second insulating layer 4, and the pixel electrode 22 is connected to the drain 2132 of the transistor 21 through the first via 5. The materials of the first metal layer 211 and the second metal layer 213 may include metal materials such as copper, aluminum, silver, and the like, or alloy materials containing the above metal materials. The material of the gate insulating layer 212 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, or may include an organic insulating material such as polyimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenol resin. Further, the gate 2111 may have a stacked structure of a copper layer and a molybdenum niobium layer for protecting the copper layer. In addition, the source electrode 2131 and the drain electrode 2132 may each include a copper layer and a molybdenum niobium layer for protecting the copper layer, and similarly, the molybdenum niobium layer has a protective effect on the copper layer to prevent the copper layer from being corroded.
In some embodiments, the second insulating layer 4 completely covers the hole wall of the first hole segment 51, and the second insulating layer 4 contacts the drain electrode 2132.
In the embodiment of the present application, as shown in fig. 3, the second insulating layer 4 may extend from a connection portion of the first hole section 51 and the second hole section 52 toward the drain electrode 2132 until the second insulating layer 4 extends to the drain electrode 2132 and covers a part of the surface of the drain electrode 2132. Based on this, the second insulating layer 4 completely covers the joint of the first hole section 51 and the second hole section 52 and the hole wall of the first hole section 51, so that the hole wall of the first via hole 5 is covered by the second insulating layer 4 to form a whole, and the hole wall of the first via hole 5 is more gradual. When the pixel electrode 22 is connected to the transistor 21 of the pixel unit 2 through the first via hole 5, the pixel electrode 22 can be more attached to the hole wall of the first via hole 5, and the probability of poor contact between the pixel electrode 22 and the hole wall of the first via hole 5 is further reduced, so that the probability of poor connection between the pixel electrode 22 and the transistor 21 is further reduced, and the probability of poor display of the display panel 100 is reduced.
In some embodiments, as shown in fig. 3, at least one pixel unit 2 further includes a common electrode 23 disposed opposite to the pixel electrode 22, a second via 6 is disposed on the second insulating layer 4, and the common electrode 23 is connected to the gate 2111 through the second via 6.
In the embodiment, the common electrode 23 may be disposed on the first insulating layer 3, the pixel electrode 22 may be disposed on the second insulating layer 4, the pixel electrode 22 and the common electrode 23 are separated by the second insulating layer 4, and the first via 5 is disposed through the first insulating layer 3 and the second insulating layer 4, so that a part of the structure of the pixel electrode 22 may extend into the first via 5 to be connected to the drain electrode 2132 located below the first insulating layer 3 through the first via 5. The second via 6 is disposed through the first insulating layer 3, the second insulating layer 4, and the gate insulating layer 212 so that the common electrode 23 may extend into the second via 6 to be connected through the gate 2111 of the second via 6 under the gate insulating layer 212.
In some embodiments, the second via 6 includes a third hole section 61 penetrating through the first insulating layer 3, a fourth hole section 62 penetrating through the second insulating layer 4, and a fifth hole section 63 penetrating through the gate insulating layer 212, and the second insulating layer 4 covers hole walls of the third hole section 61 and the fifth hole section 63.
In the embodiment of the present application, the second insulating layer 4 covers at least part of the hole walls of the third hole section 61 and the fifth hole section 63, so that the second insulating layer 4 at least partially covers the connection between the third hole section 61 and the fourth hole section 62, and the connection between the fourth hole section 62 and the fifth hole section 63, so that the hole wall of the second via hole 6 is relatively smooth. Based on this, when the common electrode 23 is connected to the gate 2111 of the transistor 21 through the second via hole 6, the common electrode 23 can be more attached to the hole wall of the second via hole 6, so that the probability of poor contact between the common electrode 23 and the hole wall of the second via hole 6 is reduced, the probability of poor connection between the common electrode 23 and the transistor 21 is further reduced, and the probability of poor display of the display panel 100 is reduced.
Further, as shown in fig. 3, the second insulating layer 4 may completely cover the hole walls of the third hole section 61 and the fifth hole section 63, and the second insulating layer 4 may extend toward the gate 2111 until contacting the gate 2111. The second insulating layer 4 completely covers the hole walls of the third hole section 61 and the fifth hole section 63, so that the hole walls of the second via holes 6 are completely covered by the second insulating layer 4 to form a whole, and the hole walls of the second via holes 6 are more gentle. Based on this, when the common electrode 23 is connected to the gate 2111 through the second via hole 6, the common electrode 23 can be more attached to the hole wall of the second via hole 6, so that the probability of poor overlapping between the common electrode 23 and the gate 2111 is reduced, and the probability of poor display of the display panel 100 is further reduced.
The first via hole 5 and the second via hole 6 may be formed simultaneously, and after the first via hole 5 and the second via hole 6 are formed, the second insulating layer 4 is heated at a high temperature of 200 to 250 degrees celsius, so that the second insulating layer 4 can flow and cover the first hole section 51 of the first via hole 5, the third hole section 61 and the fifth hole section 63 of the second via hole 6, and then the second insulating layer 4 is cured under the action of the high temperature.
In some embodiments, the common electrodes 23 of at least some of the pixel cells 2 are connected.
In the embodiment of the present application, the plurality of pixel units 2 on the substrate 1 are distributed in a matrix. The partial pixel units 2 may be a plurality of pixel units 2 located in the same row, and the partial pixel units 2 may also be a plurality of pixel units 2 located in different rows. That is, the common electrodes 23 of the plurality of pixel units 2 located in the same row may be connected as an integral structure, and the common electrodes 23 of the pixel units 2 located in different rows may also be connected as an integral structure. The common electrodes 23 of some of the pixel units 2 are connected to form an integral structure, so that the common electrodes 23 of a plurality of the pixel units 2 have an equal potential, thereby improving the display effect of the display panel 100.
Further, the common electrodes 23 of all the pixel units 2 of the display panel 100 are connected, so that the common electrodes 23 of all the pixel units 2 have an equal potential, and the display effect of the display panel 100 is further improved.
The common electrodes 23 of the plurality of pixel units 2 may be directly connected, and the common electrodes 23 of the plurality of pixel units 2 may also be connected through an auxiliary electrode line. Specifically, when the common electrodes 23 of a plurality of pixel units 2 are connected by an auxiliary electrode line, the common electrode 23 of a pixel unit 2 is connected to one end of the auxiliary electrode line by a via structure, and the common electrode 23 of a pixel unit 2 adjacent to the pixel unit 2 is connected to the other end of the auxiliary electrode line by a via structure, so as to connect the common electrodes 23 of two adjacent pixel units 2. The material of the auxiliary electrode line may include a metal material such as copper, aluminum, silver, or an alloy material containing the metal material, and the material of the auxiliary electrode line may also be a transparent metal oxide.
In some embodiments, the common electrode 23 and the pixel electrode 22 are both transparent metal oxide electrodes. That is, the common electrode 23 and the pixel electrode 22 are made of transparent metal oxide, such as IZO (indium zinc oxide), ITO (indium tin oxide), and the like. The common electrode 23 and the pixel electrode 22 are made of transparent metal oxide, so that the blocking rate of the common electrode 23 and the pixel electrode 22 to light is reduced, and the light transmittance of the display panel 100 is improved.
In some embodiments, the materials of the common electrode 23 and the pixel electrode 22 may further include a metal material such as copper, aluminum, silver, or an alloy material containing the above metal materials.
In the embodiment of the present application, when the display panel 100 is an organic light emitting display panel, as shown in fig. 4, the organic light emitting display panel includes the substrate 1, the transistor 21, and the light emitting layer 200 located on a side of the transistor 21 away from the substrate 1. The transistor 21 is used to drive the light emitting layer 200 to emit light. The pixel electrode 22 may be an anode layer in the light emitting layer 200, the common electrode 23 may be a cathode layer in the light emitting layer 200, and an organic light emitting layer 210 for emitting light is further disposed between the pixel electrode 22 and the common electrode 23.
When the display panel 100 is a thin film transistor liquid crystal display panel, as shown in fig. 5, the display panel 100 includes the substrate 1, the transistor 21, the pixel electrode 22, the common electrode 23, and the liquid crystal layer 300 located on a side of the common electrode 23 away from the substrate 1, and the transistor 21 is used for driving liquid crystal in the liquid crystal layer 300 to generate directional deflection.
Embodiments of the second aspect of the present application provide a method for manufacturing a display panel, as shown in fig. 6, the method includes the following steps:
in step S601, a substrate is provided.
In step S602, a transistor is formed on one side of a substrate.
In step S603, a first insulating layer is formed on a side of the transistor away from the substrate.
In step S604, a second insulating layer is formed on a side of the first insulating layer away from the transistor.
Step S605 is to form a first via hole on the second insulating layer, where the first via hole includes a first hole section penetrating through the first insulating layer and a second hole section penetrating through the second insulating layer.
The specific process of forming the first via hole may be to form a second hole section penetrating through the second insulating layer on the second insulating layer by means of exposure, development, and the like, and then etch the first insulating layer below the second insulating layer by means of dry etching and the like, so as to form a first hole section penetrating through the first insulating layer on the first insulating layer, thereby forming the first via hole.
Step S606, the second insulating layer is heated at a preset temperature, so that the second insulating layer flows and covers at least a part of the hole wall of the first hole section.
Further, the preset temperature is 200 to 250 ℃. In one example, the preset temperature may be 230 degrees celsius.
In step S607, a pixel electrode is formed, and the pixel electrode is connected to the transistor through the first via hole.
According to the manufacturing method of the display panel, the second hole section penetrates through the second insulating layer, and the second insulating layer covers at least part of the hole wall of the first hole section, so that the second insulating layer at least partially covers the joint of the first hole section and the second hole section, and the hole wall of the first via hole is smooth. Based on this, when the pixel electrode is connected with the transistor of the pixel unit through the first via hole, the pixel electrode can be attached to the hole wall of the first via hole, so that the probability of poor contact between the pixel electrode and the hole wall of the first via hole is reduced, the probability of poor connection between the pixel electrode and the transistor is reduced, and the probability of poor display of the display panel is reduced.
Further, step S605 may be refined to form a first via hole and a second via hole on the second insulating layer, where the first via hole includes a first hole section penetrating through the first insulating layer and a second hole section penetrating through the second insulating layer, and the second via hole includes a third hole section penetrating through the first insulating layer, a fourth hole section penetrating through the second insulating layer, and a fifth hole section penetrating through the gate insulating layer in the transistor.
Further, step S606 may be refined by heating the second insulating layer at a predetermined temperature, so that the second insulating layer flows to cover at least a part of the hole walls of the first hole segment, and the second insulating layer flows to cover a part of the hole walls of the third hole segment and the fifth hole segment.
Further, the manufacturing method further comprises: and forming a common electrode, wherein the common electrode is connected with the transistor through a second through hole.
In this application embodiment, the second insulating layer covers at least part pore wall of third pore section and fifth pore section, and this makes the second insulating layer at least partially cover the junction of third pore section and fourth pore section to and the junction of fourth pore section and fifth pore section, and this makes the pore wall of second via hole comparatively gentle. Based on this, when the common electrode is connected with the grid of transistor through the second via hole, the common electrode can laminate the pore wall of second via hole more to reduced the probability of common electrode with the pore wall contact failure of second via hole, and then reduced the probability of common electrode with transistor connection failure, reduced display panel and taken place the probability of bad display.
Embodiments of a third aspect of the present disclosure provide a display device including the display panel 100 in any of the above embodiments. The display device includes, but is not limited to, a mobile phone, a tablet computer, a display, a television, a picture screen, an advertisement screen, electronic paper, and the like. Since the display device includes the display panel 100, the display device has all advantages of a low probability of occurrence of a display failure in the display panel 100.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only for the preferred embodiment of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application are included in the protection scope of the present application.
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| CN114864606A (en) * | 2022-05-18 | 2022-08-05 | 福州京东方光电科技有限公司 | Display panel, manufacturing method of display panel and display device |
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