CN113675812A - Relay protection device framework based on SOC chip - Google Patents
Relay protection device framework based on SOC chip Download PDFInfo
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- CN113675812A CN113675812A CN202010405295.6A CN202010405295A CN113675812A CN 113675812 A CN113675812 A CN 113675812A CN 202010405295 A CN202010405295 A CN 202010405295A CN 113675812 A CN113675812 A CN 113675812A
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- 238000004891 communication Methods 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 32
- 230000008569 process Effects 0.000 claims abstract description 31
- 238000005070 sampling Methods 0.000 claims abstract description 24
- 230000003287 optical effect Effects 0.000 claims abstract description 14
- 230000005540 biological transmission Effects 0.000 claims abstract description 11
- 230000009471 action Effects 0.000 claims abstract description 4
- 230000003993 interaction Effects 0.000 claims abstract description 4
- 238000012937 correction Methods 0.000 abstract description 3
- 238000012545 processing Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H1/00—Details of emergency protective circuit arrangements
- H02H1/0092—Details of emergency protective circuit arrangements concerning the data processing means, e.g. expert systems, neural networks
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H1/00—Details of emergency protective circuit arrangements
- H02H1/0007—Details of emergency protective circuit arrangements concerning the detecting means
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H1/00—Details of emergency protective circuit arrangements
- H02H1/0061—Details of emergency protective circuit arrangements concerning transmission of signals
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H1/00—Details of emergency protective circuit arrangements
- H02H1/0061—Details of emergency protective circuit arrangements concerning transmission of signals
- H02H1/0069—Details of emergency protective circuit arrangements concerning transmission of signals by means of light or heat rays
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- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Artificial Intelligence (AREA)
- Evolutionary Computation (AREA)
- Emergency Protection Circuit Devices (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses a relay protection device architecture based on an SOC chip, which comprises: the system comprises two SOC chips, two paths of independent ADC sampling modules, two independent process layer communication networks, two paths of optical modules and a redundant outlet relay. Each SOC chip is provided with a CPU and an FPGA; each SOC chip is respectively connected with one ADC sampling module, and analog quantity sampling is carried out through the ADC sampling module; a data transmission channel is arranged between the two SOC chips and is used for data transmission between the SOC chips; each SOC chip carries out message interaction with one independent process layer communication network through one optical module; each SOC chip controls the action of one relay. The relay protection device architecture based on the SOC chip comprehensively covers redundancy mutual correction from analog quantity sampling, process layer communication, processor logic calculation to each link of a relay outlet.
Description
Technical Field
The invention belongs to the field of relay protection of power systems, and relates to a high-reliability framework of a relay protection device based on an SOC chip.
Background
The relay protection device is used as a core device of a power grid, and the automatic control of the relay protection device plays a key role in safe and stable operation of the power grid. However, at present, various relay protection device core chips in China generally depend on foreign imports.
The current digital protection device supporting the process layer communication generally adopts a double-CPU architecture, one CPU is responsible for protecting logic, the other CPU is responsible for starting the logic, the logic independence of protection and starting is realized from hardware, and the system reliability is improved to a certain extent. However, only one module for processing the process layer communication network message is provided, and the module is usually an FPGA chip, and after the FPGA processes the process layer data, the FPGA simultaneously transmits the process layer data to the protection and start-up CPUs for use. If the FPGA process layer data processing module is abnormal, the protection and the starting can be simultaneously received with wrong data, and the risk of misoperation or failure is further generated.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a relay protection device architecture based on an SOC chip, which comprehensively covers redundancy mutual correction from analog quantity sampling, process layer communication, processor logic calculation to each link of a relay outlet.
In order to achieve the above purpose, the solution of the invention is:
a relay protection device architecture based on SOC chips comprises: the system comprises two SOC chips, two paths of independent ADC sampling modules, two independent process layer communication networks, two paths of optical modules and a redundant outlet relay; wherein:
each SOC chip is provided with a CPU and an FPGA;
each SOC chip is respectively connected with one ADC sampling module, and analog quantity sampling is carried out through the ADC sampling module;
a data transmission channel is arranged between the two SOC chips and is used for data transmission between the SOC chips;
each SOC chip carries out message interaction with one independent process layer communication network through one optical module;
each SOC chip controls the action of one relay.
In a preferred scheme, one SOC chip of the two SOC chips is internally provided with a protection CPU and a main FPGA, and an independent process layer communication network communicated with the protection CPU and the main FPGA is a protection communication network; and a starting CPU and a slave FPGA are arranged in the other SOC chip, and an independent process layer communication network communicated with the starting CPU and the slave FPGA is a starting communication network.
In a preferred scheme, each ADC is an independent power supply; the two SOC chips respectively control one ADC sampling module through the FPGA.
In the preferred scheme, for process layer communication input, messages are synchronously transmitted to two FPGA pins through a protection communication network and a starting communication network respectively, and are decoded by the FPGA and then transmitted to respective CPUs for use; for process layer communication output, a starting CPU sends a starting data frame containing a starting mark to a slave FPGA, and then sends the starting data frame to a master FPGA through a data transmission channel between two SOC; the protection CPU sends a protection data frame containing a protection mark to the main FPGA; and the main FPGA checks the consistency of the starting data frame and the protection data frame, if the two data frames are consistent, the main FPGA sends the protection data frame to a protection communication network through the optical module, and the main FPGA sends the starting data frame to the starting communication network through the optical module.
In a preferred scheme, the redundant outlet relay comprises a starting relay and an outlet relay; starting the CPU to send out a starting signal to trigger the starting relay to act, and opening the positive power supply of the outlet relay; the protection CPU sends out a trip signal to trigger the outlet relay to act.
The invention has the beneficial effects that: the invention discloses a high-reliability framework of a relay protection device based on an SOC chip, which comprises 2 SOC chips, 2 paths of independent ADC sampling, a redundant process layer communication network and a redundant outlet relay. The invention inherits the classic redundant design of protection and starting of the conventional relay protection, fully evaluates the error risk of each link of the protection calculation on the basis, and adopts a relay protection system architecture based on the redundant SOC to comprehensively cover the redundant mutual correction of each link from analog quantity sampling, process layer communication, processor logic calculation to the relay outlet.
Drawings
Fig. 1 is a schematic diagram of a relay protection device based on an SOC chip.
Detailed Description
The technical scheme of the invention is explained in detail in the following with the accompanying drawings.
Fig. 1 shows a high-reliability architecture of a relay protection device based on an SOC chip. The method comprises the following steps: the system comprises two SOC chips, two paths of independent ADC sampling modules, two independent process layer communication networks, two paths of optical modules and a redundant outlet relay.
and a.2 SOC chips.
And each SOC chip is provided with a CPU and an FPGA. Wherein: a protection CPU and a main FPGA are arranged in one SOC chip, and an independent process layer communication network communicated with the SOC chip is a protection communication network; and a starting CPU and a slave FPGA are arranged in the other SOC chip, and an independent process layer communication network communicated with the starting CPU and the slave FPGA is a starting communication network. Each SOC chip is respectively connected with one path of ADC sampling module, and analog quantity sampling is carried out through the ADC sampling module. And a data transmission channel is arranged between the two SOC chips and is used for data transmission between the two SOC chips. And each SOC chip respectively performs message interaction with one independent process layer communication network through one optical module. Each SOC chip controls the action of one relay.
And b.2 paths of independent ADC sampling.
Each ADC is an independent power supply; the two SOC chips respectively control one ADC sampling module through the FPGA.
c. A redundant process layer communication network.
For process layer communication input, messages are synchronously transmitted to two FPGA pins through a protection communication network and a starting communication network respectively, and are decoded by the FPGA and then are transmitted to respective CPUs for use.
For process layer communication output, a starting CPU sends a starting data frame containing a starting mark to a slave FPGA, and then sends the starting data frame to a master FPGA through a data transmission channel between two SOC; the protection CPU sends a protection data frame containing a protection mark to the main FPGA; and the main FPGA checks the consistency of the starting data frame and the protection data frame, if the two data frames are consistent, the main FPGA sends the protection data frame to a protection communication network through the optical module, and the main FPGA sends the starting data frame to the starting communication network through the optical module.
d. Redundant outlet relays.
The redundant outlet relay comprises a starting relay and an outlet relay; starting the CPU to send out a starting signal to trigger the starting relay to act, and opening the positive power supply of the outlet relay; the protection CPU sends out a trip signal to trigger the outlet relay to act.
The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the protection scope of the present invention.
Claims (5)
1. A relay protection device architecture based on SOC chips, comprising: the system comprises two SOC chips, two paths of independent ADC sampling modules, two independent process layer communication networks, two paths of optical modules and a redundant outlet relay; wherein:
each SOC chip is provided with a CPU and an FPGA;
each SOC chip is respectively connected with one ADC sampling module, and analog quantity sampling is carried out through the ADC sampling module;
a data transmission channel is arranged between the two SOC chips and is used for data transmission between the SOC chips;
each SOC chip carries out message interaction with one independent process layer communication network through one optical module;
each SOC chip controls the action of one relay.
2. The relay protection device architecture based on the SOC chip of claim 1, wherein: in the two SOC chips, a protection CPU and a main FPGA are arranged in one SOC chip, and an independent process layer communication network communicated with the protection CPU and the main FPGA is a protection communication network; and a starting CPU and a slave FPGA are arranged in the other SOC chip, and an independent process layer communication network communicated with the starting CPU and the slave FPGA is a starting communication network.
3. The relay protection device architecture based on the SOC chip of claim 1, wherein: each ADC is an independent power supply; the two SOC chips respectively control one ADC sampling module through the FPGA.
4. The relay protection device architecture based on the SOC chip of claim 2, wherein: for process layer communication input, messages are synchronously transmitted to two FPGA pins through a protection communication network and a starting communication network respectively, and are respectively transmitted to respective CPUs for use after being decoded by the FPGAs;
for process layer communication output, a starting CPU sends a starting data frame containing a starting mark to a slave FPGA, and then sends the starting data frame to a master FPGA through a data transmission channel between two SOC; the protection CPU sends a protection data frame containing a protection mark to the main FPGA; and the main FPGA checks the consistency of the starting data frame and the protection data frame, if the two data frames are consistent, the main FPGA sends the protection data frame to a protection communication network through the optical module, and the main FPGA sends the starting data frame to the starting communication network through the optical module.
5. The relay protection device architecture based on the SOC chip of claim 2, wherein: the redundant outlet relay comprises a starting relay and an outlet relay; starting the CPU to send out a starting signal to trigger the starting relay to act, and opening the positive power supply of the outlet relay; the protection CPU sends out a trip signal to trigger the outlet relay to act.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010405295.6A CN113675812A (en) | 2020-05-14 | 2020-05-14 | Relay protection device framework based on SOC chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010405295.6A CN113675812A (en) | 2020-05-14 | 2020-05-14 | Relay protection device framework based on SOC chip |
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| CN113675812A true CN113675812A (en) | 2021-11-19 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106684838A (en) * | 2016-12-29 | 2017-05-17 | 许继集团有限公司 | Local relay protection control device and relay projection method |
| US20190190315A1 (en) * | 2015-12-16 | 2019-06-20 | Nr Electric Co., Ltd | Apparatus and method for ensuring reliability of protection trip of intelligent substation |
-
2020
- 2020-05-14 CN CN202010405295.6A patent/CN113675812A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20190190315A1 (en) * | 2015-12-16 | 2019-06-20 | Nr Electric Co., Ltd | Apparatus and method for ensuring reliability of protection trip of intelligent substation |
| CN106684838A (en) * | 2016-12-29 | 2017-05-17 | 许继集团有限公司 | Local relay protection control device and relay projection method |
Non-Patent Citations (1)
| Title |
|---|
| 许宗光等: "一种基于数据冗余校验的数字化变电站继电保护装置防误方法", 电力系统保护与控制, pages 166 - 170 * |
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Application publication date: 20211119 |