CN113674699A

CN113674699A - Driving method and device and display device

Info

Publication number: CN113674699A
Application number: CN202110970299.3A
Authority: CN
Inventors: 王斌; 李世明
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-08-23
Filing date: 2021-08-23
Publication date: 2021-11-19

Abstract

The embodiment of the disclosure provides a driving method and device and a display device. The driving method comprises the following steps: when the display panel is driven, the following operations are executed for each frame of display duration: in a first display period, providing a first scanning start signal and an enabling initial signal to a first gate driver, controlling the first gate driver to scan a plurality of gate lines of a first display area line by line in a first driving period, and suspending the operation in a first holding period after the first driving period; and in a second display period, providing a second scanning start signal and an enabling initial signal to the second gate driver, controlling the second gate driver to scan the plurality of gate lines of the second display area line by line in a second driving period, and suspending the operation in a second holding period after the second driving period.

Description

Driving method and device and display device

Technical Field

The embodiment of the disclosure relates to but is not limited to the technical field of display, and in particular relates to a driving method and device and a display device.

Background

An Organic Light Emitting Diode (OLED) is an active Light Emitting display device, and has the advantages of self-luminescence, wide viewing angle, high contrast, very high response speed, thinness, flexibility, low cost, and the like. With the development of display technology, display devices using OLEDs as light emitting devices and signal control by Thin Film Transistors (TFTs) have become mainstream products in the display field.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

In a first aspect, an embodiment of the present disclosure provides a driving method applied to a display panel, where the display panel includes: the display panel comprises a first display area and a second display area, wherein a plurality of grid lines of the first display area are connected with a first grid driver, and a plurality of grid lines of the second display area are connected with a second grid driver; the driving method includes: when the display panel is driven, the following operations are executed for each frame of display duration:

in a first display period, providing a first scanning start signal and an enabling initial signal to the first gate driver, controlling the first gate driver to scan a plurality of gate lines of the first display area line by line in a first driving period, and suspending the operation in a first holding period after the first driving period;

and in a second display period, providing a second scanning starting signal and the enabling initial signal to the second gate driver, controlling the second gate driver to scan the plurality of gate lines of the second display area line by line in a second driving period, and suspending the operation in a second holding period after the second driving period.

In a second aspect, an embodiment of the present disclosure provides a driving apparatus applied to a display panel, where the display panel includes: a first display area and a second display area, the first display area and the second display area respectively comprising: a plurality of gate lines;

the driving device includes: the display device comprises a driving controller, a first grid driver and a second grid driver, wherein the first grid driver and the second grid driver are connected with the driving controller; wherein the content of the first and second substances,

the driving controller is configured to provide a first scanning start signal and an enable initial signal to the first gate driver in a first display period, control the first gate driver to scan a plurality of gate lines of the first display region line by line in the first driving period, and suspend operation in a first retention period after the first driving period; in a second display period, providing a second scanning start signal and the enable initial signal to the second gate driver, controlling the second gate driver to scan the plurality of gate lines of the second display region line by line in a second driving period, and suspending operation in a second holding period after the second driving period;

the first gate driver is configured to scan a plurality of gate lines of the first display region line by line in a first driving period and suspend operation in a first holding period based on the first scan start signal and an enable initial signal;

the second gate driver is configured to scan a plurality of gate lines of the second display region line by line in a second driving period and pause operation in a second holding period based on the second scan start signal and the enable initial signal.

In a third aspect, an embodiment of the present disclosure provides a display device, including: the display panel and the driving apparatus described in the above embodiments, wherein the display panel includes: a first display area and a second display area, the first display area and the second display area respectively including: a plurality of gate lines.

According to the driving method and device and the display device provided by the embodiment of the disclosure, the display panel is at least divided into the first display area and the second display area, that is, the grid lines of the display panel are at least divided into the grid lines of the first display area and the grid lines of the second display area, when the display panel is driven, in each frame of display duration, in the first display period, under the control of the first scanning start signal GSTV1 and the enable initial signal ESTV, the grid lines of the first display area are scanned line by line through the first grid driver, and after the grid lines of the first display area are scanned, the first grid driver stops working for a certain duration; then, in a second display period after the first display period, under the control of the second scan start signal GSTV2 and the enable initial signal ESTV, the plurality of gate lines of the second display area are scanned line by the second gate driver, and after the plurality of gate lines of the second display area are scanned, the second gate driver is suspended for a certain period of time. Therefore, compared with the driving scheme of driving all grid lines of the display panel within the display time of each frame, under the condition that the driving frequency is not changed (namely the display time of one frame is not changed), the grid driver is controlled to pause after the scanning of the plurality of grid lines of each display area is finished, and partial power consumption can be effectively reduced.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the disclosure. Other advantages of the disclosure may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide an understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure. The shapes and sizes of the various elements in the drawings are not to be considered as true proportions, but are merely intended to illustrate the present disclosure.

FIG. 1 is a timing diagram of signals in a driving mode;

fig. 2 is a schematic structural diagram of a display panel in an exemplary embodiment of the present disclosure;

FIG. 3 is a flow chart diagram of a driving method in an exemplary embodiment of the present disclosure;

FIG. 4 is a signal timing diagram in a driving method in an exemplary embodiment of the disclosure;

fig. 5 is a schematic structural diagram of a driving device in an exemplary embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a display device in an exemplary embodiment of the present disclosure.

Detailed Description

Various embodiments are described herein, but the description is intended to be exemplary, rather than limiting and many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

In describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps herein, the method or process should not be limited to the particular sequence of steps. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present disclosure.

In the drawings of the present disclosure, the size of each component, the thickness of a layer, or a region may be exaggerated for clarity. Therefore, one aspect of the present disclosure is not necessarily limited to the dimensions, and the shapes and sizes of the respective components in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

In the exemplary embodiments of the present disclosure, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of constituent elements, and are not limited in number.

In the exemplary embodiments of the present disclosure, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used for convenience to explain positional relationships of constituent elements with reference to the drawings, only for convenience in describing the specification and simplifying the description, but not to indicate or imply that the referred devices or elements must have a specific orientation, be configured in a specific orientation, and operate, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In the exemplary embodiments of the present disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise explicitly specified or limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood in specific instances by those of ordinary skill in the art.

In this specification, a transistor refers to an element including at least three terminals, i.e., a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (which may also be referred to as a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (which may also be referred to as a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region where current mainly flows.

In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

"about" in the exemplary embodiments of the present disclosure refers to a numerical value that is not strictly limited, allowing for process and measurement error.

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure.

Currently, the OLED display device is always pursuing Low power consumption and multi-frequency driving, and the carrier mobility of Low Temperature Polycrystalline Oxide (LTPO) is 20 to 30 times of that of amorphous silicon (a-Si), which can greatly improve the charging and discharging rate of a Thin Film Transistor (TFT) to a Pixel electrode, improve the response speed of the Pixel, achieve faster refresh rate, and simultaneously improve the row scanning rate of the Pixel greatly due to faster response, so that ultra high resolution (Pixel Per Inch, PPI) becomes possible in the OLED display device. However, as shown in fig. 1, when a Low Temperature Poly-Silicon (LTPS) OLED display device is used for driving, the current driving scheme generally adopts a driving method of driving all gate lines of a display panel within each frame of display duration under the control of a scan start signal GSTV and an enable start signal ESTV, and therefore, power is continuously supplied to a pixel driving circuit connected to the gate lines during each frame of display duration, which results in higher power consumption of the display panel.

The embodiment of the present disclosure provides a driving method, which may be applied to driving a display panel. For example, the display panel may include: the display panel comprises a first display area and a second display area, wherein a plurality of grid lines of the first display area are connected with a first grid driver, and a plurality of grid lines of the second display area are connected with a second grid driver. The driving method comprises the following steps: when the display panel is driven, the following operations are executed for each frame of display duration: in a first display period, providing a first scanning start signal and an enabling initial signal to a first gate driver, controlling the first gate driver to scan a plurality of gate lines of a first display area line by line in a first driving period, and suspending the operation in a first holding period after the first driving period; and in a second display period, providing a second scanning start signal and an enabling initial signal to the second gate driver, controlling the second gate driver to scan the plurality of gate lines of the second display area line by line in a second driving period, and suspending the operation in a second holding period after the second driving period.

In one exemplary embodiment, the "the first gate driver scans the plurality of gate lines of the first display region row by row for the first driving period" may include: the first gate driver sequentially outputs scanning signals to the pixel driving circuits respectively connected with the plurality of gate lines included in the first display area, and the pixel driving circuits respectively connected with the plurality of gate lines included in the first display area are started.

In one exemplary embodiment, the "first gate driver is suspended for a first holding period after the first driving period" may refer to that the first gate driver does not scan any one of the plurality of gate lines of the first display region for the first holding period after the first driving period, but the pixel in the first display region may maintain a light emitting state. For example, the "first gate driver suspends the operation for the first holding period after the first driving period" may include: in a first holding period after the first driving period, the first gate driver may stop outputting a scan signal or outputting an invalid signal to the pixel driving circuit connected to each of the plurality of gate lines of the first display region, so as to prevent any one of the plurality of gate lines of the first display region from being scanned.

In one exemplary embodiment, the "the second gate driver scans the plurality of gate lines of the second display region row by row in the second driving period" may include: the second gate driver sequentially outputs effective scanning signals to the pixel driving circuits respectively connected with the plurality of gate lines included in the second display area, and the pixel driving circuits respectively connected with the plurality of gate lines included in the second display area are started.

In one exemplary embodiment, the "second gate driver is suspended for a second holding period after the second driving period" may refer to that the second gate driver does not scan any one of the plurality of gate lines of the second display region for the second holding period after the second driving period, but the pixels in the second display region may maintain a light emitting state. For example, the "the second gate driver suspends the operation for the second holding period after the second driving period" may include: in a second holding period after the second driving period, the second gate driver may stop outputting the scan signal or outputting the invalid signal to the pixel driving circuit connected to each of the plurality of gate lines of the second display region, so as to prevent any one of the plurality of gate lines of the second display region from being scanned, at this time, the second gate driver stops charging the pixel driving circuit corresponding to the pixel of the second display region, the pixel driving circuit only needs to hold, and does not need to be powered up to maintain the electric quantity of the pixel, and the sufficient electric quantity may be maintained to maintain the brightness of the pixel through good TFT characteristics in the pixel driving circuit.

The driving method provided by the embodiment of the disclosure divides the display panel into at least a first display area and a second display area, that is, the gate lines of the display panel are divided into at least a plurality of gate lines of the first display area and a plurality of gate lines of the second display area, and when the display panel is driven, the plurality of gate lines of the first display area are scanned line by a first gate driver in a first display time interval within each frame display time length under the control of a first scanning start signal GSTV1 and an enable initial signal ESTV, and the first gate driver stops working for a certain time length after the plurality of gate lines of the first display area are scanned; then, in a second display period after the first display period, under the control of the second scan start signal GSTV2 and the enable initial signal ESTV, the plurality of gate lines of the second display area are scanned line by the second gate driver, and after the plurality of gate lines of the second display area are scanned, the second gate driver is suspended for a certain period of time. Thus, when the driving method is applied to driving the LTPO display panel, the pause operation period is added after the scanning of the plurality of gate lines in each display area is finished, and in the pause (pa μ se) operation period, the gate driver pauses (pa μ se) operation, that is, the gate lines are not scanned, but the pixels can keep a light-emitting state. Therefore, compared with a driving mode of driving all the grid lines of the display panel within each frame of display duration, under the condition that the driving frequency is not changed (namely, one frame of display duration is not changed), the scanning time of the grid lines can be reduced by increasing the pause working duration, namely, the charging time of the TFT is reduced, and therefore, part of power consumption can be effectively reduced. Moreover, during the pause (pa μ se) operation, since the good TFT characteristics of LTPO can keep enough electric quantity to maintain the brightness of the pixel, flicker (flicker) can be effectively improved, and thus, the display effect of the display panel can be improved.

The driving method provided by the embodiment of the present disclosure is explained below with reference to the drawings.

Fig. 2 is a schematic structural diagram of a display panel in an exemplary embodiment of the disclosure, and as shown in fig. 2, the display panel may include, in a plane parallel to the display panel: a display area 100 and a non-display area located at a periphery of the display area 100, wherein the non-display area may include: a binding region 200 located at one side of the display region 100, and a bezel region 300 located at the other side of the display region 100. For example, the binding area 200 may be located at one side (upper side) of the display area 100 in the first direction DR 1.

In an exemplary embodiment, the display area 100 may include: a plurality of display areas. For example, the display area may include: two display areas, three display areas, or four display areas, etc. For example, the plurality of display areas may be uniformly divided, or may be non-uniformly divided. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the number of display regions included in the display panel may be divided by using a uniform dividing manner or a non-uniform dividing manner according to the number of gate lines included in the display panel, where when the uniform dividing manner is used, the number of gate lines included in a plurality of display regions may be equal, or when the non-uniform dividing manner is used, the number of gate lines included in at least two display regions in the plurality of display regions may be unequal. Here, the embodiment of the present disclosure does not limit this.

For example, taking the display panel as a Full High Definition (FHD) panel, that is, the number of gate lines (i.e., the number of rows) included in the display panel may be 1080, for example, when a uniform dividing manner is adopted according to the number of gate lines included in the display panel, the display area of the display panel may be divided into 2 display areas, at this time, the number of gate lines included in each display area may be 540, or the display area of the display panel may be divided into 3 display areas, at this time, the number of gate lines included in each display area may be 360. For another example, taking the number of gate lines (i.e., the number of rows) included in the display panel as 1440 as an example, when a uniform division manner is adopted according to the number of gate lines included in the display panel, the display area of the display panel may be divided into 2 display regions, at this time, the number of gate lines included in each display region may be 720, or the display area of the display panel may be divided into 4 display regions, at this time, the number of gate lines included in each display region may be 360.

In an exemplary embodiment, taking the display panel as an example that can be divided into two display areas, as shown in fig. 2, the display panel may include: a first display area 101 (upper display area) and a second display area 102 (lower display area) sequentially arranged along the first direction DR 1. Wherein, the first display area 101 and the second display area 102 may each include: a plurality of gate lines (may also be referred to as scan signal lines). For example, the first display region 101 may include: the plurality of gate lines (S11 to S1m), m may be a natural number, and n may be a natural number, and the second display region 102 may include the plurality of gate lines (S21 to S2 n). For example, the display panel may further include: a first gate driver, a second gate driver, and a driving controller connected to the first gate driver and the second gate driver, wherein the plurality of gate lines (S11 to S1m) of the first display region 101 may be connected to the first gate driver, the plurality of gate lines (S21 to S2n) of the second display region 102 may be connected to the second gate driver, and the driving controller may be configured to control the first gate driver to apply a scan signal and the second gate driver to apply a scan signal. The plurality of gate lines (S11 to S1m) of the first display region 101, the plurality of gate lines (S21 to S2n) of the second display region 102 may extend in the second direction DR2, and the second direction DR2 crosses the first direction DR 1. For example, the second direction DR2 and the first direction DR1 may be perpendicular. Here, the number of display areas and the positional relationship in fig. 2 are merely an exemplary illustration, and do not represent the actual number and positional relationship. The number and the position relationship of the signal lines in the display panel in fig. 2 are only an exemplary illustration, and the actual number and the arrangement position may be designed according to the application scenario.

In one exemplary embodiment, a display panel includes: the first display area and the second display area are exemplified, and the first display area and the second display area may be divided uniformly or may be divided non-uniformly. Here, the embodiment of the present disclosure does not limit this.

In one exemplary embodiment, a display panel includes: for example, the number of gate lines in the first display region may be equal to the number of gate lines in the second display region.

In one exemplary embodiment, a display panel includes: for example, the first display region and the second display region may include gate lines included in the first display region and gate lines included in the second display region without overlapping.

Fig. 3 is a flowchart illustrating a driving method in an exemplary embodiment of the disclosure, and as shown in fig. 3, the driving method may include: when the display panel in one or more embodiments described above is driven, the following operations may be performed for each frame display duration T0:

step 31: supplying a first scan start signal GSTV1 and an enable initial signal escv to the first gate driver for a first display period T1, controlling the first gate driver to scan a plurality of gate lines (S11 to S1m) of the first display region line by line for a first driving period T11, and suspending operation for a first sustain period T12 after the first driving period T11;

step 32: in the second display period T2, the second scan start signal GSTV2 and the enable initial signal escv are supplied to the second gate driver, the second gate driver is controlled to scan the plurality of gate lines (S21 to S2n) of the second display region line by line in the second driving period T21, and to pause the operation in the second holding period T22 after the second driving period T21.

In an exemplary embodiment, step 31 may include: supplying the first scan start signal GSTV1 and the enable initialization signal escv to the first gate driver for the first display period T1; the first gate driver sequentially turns on pixel driving circuits to which a plurality of gate lines (S11 to S1m) included in the first display region are respectively connected, under the control of the first scan start signal GSTV1 and the enable start signal escv. Next, after the pixel driving circuits connected to the gate lines (S11 to S1m) are sequentially turned on, the first gate driver is in a suspended state, and stops outputting the scan signal or the disable signal to the pixel driving circuits connected to the gate lines (S11 to S1m), and stops charging the pixel driving circuits.

In an exemplary embodiment, step 32 may comprise: supplying the second scan start signal GSTV2 and the enable initialization signal escv to the second gate driver for the second display period T2; the second gate driver sequentially turns on pixel driving circuits respectively connected to a plurality of gate lines (S21 to S2n) included in the second display region under the control of the second scan start signal GSTV2 and the enable start signal escv. Then, after the pixel driving circuits respectively connected to the gate lines (S21 to S2n) included in the second display region are sequentially turned on, the second gate driver is in a suspended state, and stops outputting the scan signal or the invalid signal to the pixel driving circuits respectively connected to the gate lines (S21 to S2n) included in the second display region, thereby stopping charging the pixel driving circuits.

In an exemplary embodiment, the display area of the display panel may be divided into a plurality of display areas, and then, the one-frame display duration may include: a plurality of display periods each including a driving period and a holding period, that is, one frame display duration may include: a plurality of driving periods and a plurality of holding periods alternately arranged. Wherein a plurality may include, but is not limited to, meaning two, three, or four, etc. Here, the embodiment of the present disclosure does not limit this.

For example, the display area of the display panel is divided into two display areas, including: for example, the first display area and the second display area, the display duration of one frame may include: the first display period T1 (corresponding to the first display region, may include the first driving period T11 and the first holding period T12) and the second display period T2 (corresponding to the second display region, may include the second driving period T21 and the second holding period T22), that is, the one-frame display duration may include: the first driving period T11, the first holding period T12, the second driving period T21, and the second holding period T22 are sequentially set.

For example, the display area of the display panel is divided into three display areas, including: for example, the first display area, the second display area, and the third display area, the display duration of one frame may include: the first display period T1 (corresponding to the first display region, may include a first driving period T11 and a first holding period T12), the second display period T2 (corresponding to the second display region, may include a second driving period T21 and a second holding period T22), and the third display period T3 (corresponding to the third display region, may include a third driving period T31 and a fourth holding period T32).

In an exemplary embodiment, the one-frame display duration T0 may refer to the time taken to actually display a frame of image. Here, the embodiment of the present disclosure does not limit this.

In one exemplary embodiment, the one-frame display duration T0 is related to the driving frequency f, where T0 is 1/f (seconds). For example, taking the driving frequency as 60Hz (hertz), the display duration of one frame may be about 16.67ms (milliseconds).

In an exemplary embodiment, the time length of the first display period T1 (i.e., the display time length corresponding to the first display region) and the time length of the second display period T2 (i.e., the display time length corresponding to the second display region) may be equal or may not be equal according to the difference between the number of gate lines of the first display region and the number of gate lines of the second display region. Here, the embodiment of the present disclosure does not limit this.

For example, taking the number of gate lines of the first display region and the number of gate lines of the second display region as an example, then, the one-frame display time period T0 may be uniformly divided into the first display period T1 and the second display period T2, i.e., the time period of the first display period T1 (i.e., the display time period corresponding to the first display region) and the time period of the second display period T2 (i.e., the display time period corresponding to the second display region) may be equal. For example, taking the driving frequency of 60Hz (hertz) as an example, the one-frame display period T0 may be about 16.67ms (milliseconds), and since the periods of the display periods of the plurality of display regions may be equal, the period of one display region per one-frame display period T0/number of display regions, that is, the period of the first display period T1 and the period of the second display period T2 may each be about 8.33 ms.

In an exemplary embodiment, for at least one display period (including a driving period and a holding period) of a plurality of display periods in one frame display period, a ratio between a period of the driving period and a period of the holding period may be a preset integer value, wherein the preset integer value may include, but is not limited to, 2 or 3, and the like. For example, the display area of the display panel is divided into two display areas, including: for the first and second display regions as an example, the ratio between the duration of the first driving period T11 and the duration of the first holding period T12 and the ratio between the duration of the second driving period T21 and the duration of the second holding period T22 may each include, but are not limited to, 2, 3, or the like. Thus, not only can low power consumption be ensured, but also flicker (flicker) can be improved more effectively. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the enable initialization signal escv may be a pulse width modulation PWM signal, and the one-frame display period T0 may include, but is not limited to, K times the period T of the PWM signal, i.e., the one-frame display period T0 includes K periods of the PWM signal, where T0 is K × T. For example, K may include, but is not limited to, any of 6, 8, and 12. Thus, not only can low power consumption be ensured, but also flicker (flicker) can be improved more effectively. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the time interval between the trigger time T _ g2 of the second scan start signal GSTV2 and the trigger time T _ g1 of the first scan start signal GSTV1 may include, but is not limited to, one-half (1/2) times the display time duration T0 of one frame, i.e., T _ g2-T _ g 1-0.5 × T0. For example, the time interval between the trigger time T _ g2 of the second scan start signal GSTV2 and the trigger time T _ g1 of the first scan start signal GSTV1 may include, but is not limited to, one-half of the one-frame display time period T0. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the same signal line may be used to provide the first scan start signal GSTV1 to the first gate driver and the second scan start signal GSTV2 to the second gate driver, i.e., the initial input signals provided by the signal lines providing the second scan start signal GSTV2 may share the initial input signals of the signal lines of the first scan start signal GSTV1, only at the time of triggering that the second scan start signal GSTV2 is 1/2 frames later than the GSTV 1. Here, the embodiment of the present disclosure does not limit this.

In the description of the embodiments of the present disclosure, the symbol GSTV1 may denote both the first scan start signal and a signal line that supplies the first scan start signal. The symbol GSTV2 may indicate both the second scan start signal and a signal line that supplies the second scan start signal. The symbol ESTV may indicate both an enable initial signal and a signal line that supplies the enable initial signal.

The following is divided into two display regions by the display region of the display panel, including: the driving method provided by the exemplary embodiment of the present disclosure is described by taking as an example that the number of gate lines included in the first display region is equal to the number of gate lines included in the second display region.

Fig. 4 is a signal timing diagram in a driving method in an exemplary embodiment of the present disclosure, in which waveforms of the first scan start signal GSTV1, the second scan start signal GSTV2, and the enable start signal escv in a one-frame display duration are shown in fig. 4.

In an exemplary embodiment, as shown in fig. 4, the duty cycle of the enable initialization signal escv may include, but is not limited to, 50%. Here, the duty ratio of the enable initialization signal ESTV may refer to a ratio between a pulse width (which may also be referred to as a pulse width) ton of the enable initialization signal ESTV and a period T of the enable initialization signal ESTV, and the pulse width ton of the enable initialization signal ESTV may refer to a duration of a pulse having a turn-on level (e.g., a low level). Here, the duty ratio of the enable initial signal escv in fig. 4 is merely an exemplary illustration, and the duty ratio of the actual enable initial signal escv may be designed according to the requirements (e.g., brightness requirements) of the application scenario. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, as shown in fig. 4, the enable initialization signal escv may be a PWM signal, and the number of periods of the PWM signal included in the one-frame display period T0 may include, but is not limited to, 6. The number of periods of the PWM signal included in the one-frame display period T0 in fig. 4 is merely an exemplary illustration, and the actual number of periods of the PWM signal included in the one-frame display period T0 may be designed according to the requirements of the application scenario. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, as shown in fig. 4, the duration of the first display period T1 (i.e., the display duration corresponding to the first display region) and the duration of the second display period T2 (i.e., the display duration corresponding to the second display region) are equal, wherein the duration of the first display period T1 may include 3 number of cycles of the PWM signal, the duration of the second display period T2 may include 3 number of cycles of the PWM signal, the duration of the first driving period T11 in the first display period T1 may include 2 number of cycles of the PWM signal, the duration of the first holding period T12 in the first display period T1 may include 1 number of cycles of the PWM signal, the duration of the second driving period T21 in the second display period T2 may include 2 number of cycles of the PWM signal, the duration of the second holding period T22 in the second display period T2 may include 1 number of cycles, that is, the ratio between the duration of the first driving period T11 and the duration of the first holding period T12 may be 2, and the ratio between the duration of the second driving period T21 and the duration of the second holding period T22 may be 2.

For example, taking the driving frequency as 60Hz (hertz), the one-frame display duration T0 may be 16.67ms (milliseconds). And the one-frame display period T0 is the period of the first display period T1 + the period of the second display period T2, when the period of the first display period T1 is equal to the period of the second display period T2, the periods of the first display period T1 and the second display period T2 may each be about 8.33 ms.

For example, taking the case where the duration of the first display period T1 may be about 8.33ms, and the duration of the first display period T1 is equal to the duration of the first drive period T11 + the duration of the first holding period T12, when the ratio between the duration of the first drive period T11 and the duration of the first holding period T12 is 2, the duration of the first drive period T11 may be about 5.55ms, and the duration of the first holding period T12 may be about 2.78 ms. For example, taking the number of gate lines included in the first display area as 540 as an example, the one-line scanning Time 1 htime in the first display area is equal to the duration of the first driving period T11/the number of gate lines included in the first display area is equal to 5.55ms/540 which is equal to 10.27 μ s (microseconds).

For example, taking the case where the duration of the second display period T2 may be about 8.33ms, and the duration of the second display period T2 is equal to the duration of the second driving period T21 + the duration of the second holding period T22, when the ratio between the duration of the second driving period T21 and the duration of the second holding period T22 is 2, the duration of the second driving period T21 may be about 5.55ms, and the duration of the second holding period T22 may be about 2.78 ms. For example, taking the number of gate lines included in the second display area as 540 as an example, the one-line scanning Time 1 hmetime in the second display area is equal to the duration of the second driving period T21/the number of gate lines included in the second display area is equal to 5.55ms/540, which is equal to 10.27 μ s.

The inventor of the present disclosure verifies that: in a gray255 (white) screen, the result (JEITA value) of the flicker (flicker) of the display panel is verified on a Field Programmable Gate Array (FPGA), and the test result is: when the LTPS display panel is driven by the driving method shown in fig. 1, the result of the LTPS display panel flickering (JEITA value) is-26.34 db, whereas when the LTPO display panel is driven by the driving method provided by the embodiment of the present disclosure, the result of the LTPO display panel flickering (JEITA value) is-37.69 db. It can be seen from experimental results that the driving method provided by the exemplary embodiment of the present disclosure can not only effectively reduce the power consumption of the display panel, but also effectively improve the flicker problem of the display panel.

The embodiment of the disclosure provides a driving device, which can be applied to driving a display panel. For example, the driving device can be applied to a display device, and the driving device can be connected with a display panel in the display device.

The embodiment of the disclosure also provides a display device. The display device may include: a display panel in one or more exemplary embodiments and a driving device in one or more exemplary embodiments, the driving device being connected to the display panel.

Fig. 5 is a schematic structural diagram of a driving device in an exemplary embodiment of the present disclosure. Fig. 6 is a schematic structural diagram of a display device in an exemplary embodiment of the present disclosure. In fig. 6, the display panel includes 2 display regions as an example. The driving device and the display device provided in the embodiments of the present disclosure are described below with reference to fig. 5 and 6.

In an exemplary embodiment, as shown in fig. 5 and 6, the display panel may include: a first display region 101 and a second display region 102, the first display region 101 may include a plurality of gate lines (S11 to S1m), and the second display region 102 may include: a plurality of gate lines (S21 to S2n), m may be a natural number, and n may be a natural number. The driving device may include: a driving controller 50, and a first gate driver 51 and a second gate driver 52 connected to the driving controller 50. The first gate driver 51 is connected to the plurality of gate lines (S11 to S1m) of the first display region 101, and the second gate driver 52 is connected to the plurality of gate lines (S21 to S2n) of the second display region 102; wherein the driving controller 50 is configured to supply the first scan start signal GSTV1 and the enable initial signal ESTV to the first gate driver 51 for the first display period T1, control the first gate driver 51 to scan the plurality of gate lines (S11 to S1m) of the first display region 101 line by line for the first driving period T11, and to suspend operation for a first holding period T12 after the first driving period T11; supplying the second scan start signal GSTV2 and the enable initialization signal escv to the second gate driver 52 for the second display period T2, controlling the second gate driver 52 to scan the plurality of gate lines (S21 to S2n) of the second display region line by line for the second driving period T21, and to pause the operation for a second holding period T22 after the second driving period T21; a first gate driver 51 configured to scan a plurality of gate lines (S11 to S1m) of the first display region 101 line by line for a first driving period T11 based on the first scan start signal GSTV1 and the enable initial signal escv, and to pause an operation for a first holding period T12 after the first driving period T11; and a second gate driver 52 configured to scan the plurality of gate lines (S21 to S2n) of the second display region row by row for a second driving period T21 and to pause an operation for a second holding period T22 after the second driving period T21, based on the second scan start signal GSTV2 and the enable initial signal escv.

In an exemplary embodiment, as shown in fig. 5 and 6, the driving controller 50, configured to provide the first scan start signal GSTV1 and the enable start signal escv to the first gate driver 51 for the first display period T1, controls the first gate driver 51 to sequentially turn on the pixel driving circuits to which the plurality of gate lines (S11 to S1m) included in the first display region 101 are respectively connected. Next, after the pixel driving circuits connected to the gate lines (S11 to S1m) are sequentially turned on, the first gate driver 51 is in a suspended state, and stops outputting the scan signal or the disable signal to the pixel driving circuits connected to the gate lines (S11 to S1m), and stops charging the pixel driving circuits.

In an exemplary embodiment, as shown in fig. 5 and 6, the driving controller 50 is configured to supply the second scan start signal GSTV2 and the enable initialization signal ESTV to the second gate driver 52 and control the second gate driver 52 to sequentially turn on the pixel driving circuits respectively connected to the plurality of gate lines (S21 to S2n) included in the second display region 102 for the second display period T2. Next, after the pixel driving circuits respectively connected to the gate lines (S21 to S2n) included in the second display region 102 are sequentially turned on, the second gate driver 52 is in a suspended state, and stops outputting the scan signal or the invalid signal to the pixel driving circuits respectively connected to the gate lines (S21 to S2n) included in the second display region 102, thereby stopping charging the pixel driving circuits.

In an exemplary embodiment, the drive controller may be implemented in various forms. For example, the driving controller may be a timing control circuit (T-con). For example, the drive controller may be a Micro Control Unit (MCU). For example, the driver controller may comprise a processor and a memory, the memory comprising executable code, the processor running the executable code to perform the above-described driving method. Here, the embodiment of the present disclosure does not limit this.

For example, the Processor may be a Central Processing Unit (CPU) or other form of Processing device having data Processing capabilities and/or instruction execution capabilities, and may include, for example, other general purpose processors, Digital Signal Processors (DSPs), Programmable Logic Controllers (PLCs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic, discrete hardware components, application specific integrated circuits, etc. The general-purpose Processor may be a Microprocessor (MPU) or the Processor may be any conventional Processor. For example, the Memory may include a volatile Memory in a computer-readable storage medium, a Random Access Memory (RAM), a nonvolatile Memory (Flash RAM), a Read Only Memory (ROM), or a Flash Memory, and the Memory includes at least one Memory chip. One or more computer program instructions may be stored on a computer readable storage medium and a processor may execute the desired functions of the program instructions. Various applications and various data may also be stored in the computer-readable storage medium. Here, the embodiment of the present disclosure does not limit this.

In one exemplary embodiment, the first gate driver may be configured to generate a scan signal to be supplied to the gate lines S11, S12, S13, … …, and S1m of the first display region 101 by receiving the first scan start signal GSTV1 or the like from the driving controller to enable progressive scanning of the gate lines of the first display region 101. For example, the first gate driver may be configured to sequentially supply scan signals having on-level pulses to the gate lines S11, S12, S13, … …, and S1m of the first display region 101. For example, the first Gate Driver may be a Gate Driver on Array (GOA) circuit, and the GOA circuit may be configured in the form of a shift register, including: a plurality of cascaded shift registers may be configured to generate a scan signal in such a manner that a first scan start signal GSTV1 provided in the form of an on-level pulse is sequentially transmitted to a next stage circuit.

In one exemplary embodiment, the second gate driver may be configured to generate scan signals to be supplied to the gate lines S21, S22, S23, … …, and S2n of the second display region 102 by receiving the second scan start signal GSTV2 or the like from the driving controller to enable progressive scanning of the gate lines of the second display region 102. For example, the second gate driver may be configured to sequentially supply scan signals having on-level pulses to the gate lines S21, S22, S23, … …, and S2n of the second display region 102. For example, the second gate driver may be a GOA circuit, which may be configured in the form of a shift register, including: a plurality of cascaded shift registers, and may be configured to generate the scan signal in such a manner that the second scan start signal GSTV2 provided in the form of an on-level pulse is sequentially transmitted to the next stage circuit.

In an exemplary embodiment, taking the gate driver as a GOA circuit as an example, the first gate driver includes: a first shift register set including: a plurality of cascaded first shift registers; the second gate driver includes: a second shift register group, the second shift register group comprising: a plurality of cascaded second shift registers; a driving controller configured to supply the first scan start signal GSTV1 and the enable start signal escv to a first stage shift register of the plurality of cascaded first shift registers in a first display period T1; in the second display period T2, the second scan start signal GSTV2 and the enable initial signal escv are supplied to the first stage shift register of the plurality of cascaded second shift registers.

For example, as shown in fig. 6, a signal line supplying a first scan start signal, a signal line supplying a second scan start signal, and a signal line supplying an enable initial signal may extend in the first direction DR 1.

In one exemplary embodiment, as shown in fig. 6, the first gate driver 51 may be disposed in a bezel region corresponding to the first display region 101. For example, the first gate driver may be located in a bezel region on a side (left side) opposite to the second direction DR2 of the first display region 101, or may be located in a bezel region on a side (right side) of the second direction DR2 of the first display region 101. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, as shown in fig. 6, the second gate driver 52 may be disposed in a bezel region corresponding to the second display region 102. For example, the second gate driver may be located in a bezel region on a side (left side) opposite to the second direction DR2 of the second display region 102, or may be located in a bezel region on a side (right side) of the second display region 102 in the second direction DR 2. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the display area may include: a plurality of pixel units arranged in a matrix, at least one of the plurality of pixel units may include: the plurality of sub-pixels Pxij, i and j may be natural numbers, and at least one sub-pixel Pxij may include: a pixel driving circuit and a light emitting device. The pixel driving circuit in the sub-pixel is respectively connected with the signal lines such as the grid line and the data signal line, the light-emitting device in the sub-pixel is respectively connected with the pixel driving circuit of the sub-pixel, the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output corresponding current to the light-emitting device under the control of the signal line such as the grid line, and the light-emitting device is configured to emit light with corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

In an exemplary embodiment, as shown in fig. 6, the display panel may further include: a plurality of data signal lines (D1 to Dk), the driving device may further include: and a data signal driver connected to the plurality of data signal lines (D1 to Dk), k being a natural number.

In an exemplary embodiment, the plurality of data signal lines (D1 to Dk) and the plurality of gate lines (S11 to S1m) included in the first display region 101 cross each other to define a plurality of pixel cells distributed in an array in the first display region 101, and the plurality of data signal lines (D1 to Dk) and the plurality of gate lines (S21 to S2n) included in the second display region 102 cross each other to define a plurality of pixel cells distributed in an array in the second display region 102, at which time, the pixel driving circuits respectively connected to the plurality of gate lines (S11 to S1m) included in the first display region 101 and the pixel driving circuits respectively connected to the plurality of gate lines (S21 to S2n) included in the second display region 102 may share the same data signal lines (D1 to Dk), and it may be ensured that mischarging is not possible.

In one exemplary embodiment, the driving controller may be configured to supply the gray value and the control signal suitable for the specification of the data signal driver to the data signal driver. The data signal driver is configured to generate data voltages to be supplied to the data signal lines D1, D2, D3, … …, and Dk using the gray scale value and the control signal received from the driving controller. For example, the data signal driver is configured to sample a gray value and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dk in units of pixel rows, k may be a natural number.

In an exemplary embodiment, the plurality of sub-pixels in the pixel unit may be arranged in a horizontal parallel manner, a vertical parallel manner, an X-shape, a cross-shape, a delta-shape, or the like. For example, taking the case that the pixel unit includes three sub-pixels, the three sub-pixels may be arranged in a horizontal parallel manner, a vertical parallel manner, a delta-shaped manner, or the like. For example, taking the pixel unit including four sub-pixels as an example, the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or Square (Square) manner. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the shape of the sub-pixel may be any one or more of a triangle, a square, a rectangle, a rhombus, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the pixel driving circuit may include, but is not limited to, pTqC (p, q are positive integers) pixel driving circuits of 2T1C (i.e., two transistors and one storage capacitor), 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T 1C. Here, the embodiment of the present disclosure does not limit this.

In one exemplary embodiment, the light emitting device may be an organic electroluminescent diode (OLED) including a first pole (e.g., as an anode), an organic light emitting layer, and a second pole (e.g., as a cathode) stacked. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the display panel may include, but is not limited to, an OLED display panel, and the like.

In one exemplary embodiment, the display panel may include, but is not limited to, an LTPO display panel. For example, the first display area and the second display area may include: a pixel driving circuit. For example, the pixel driving circuit may include: oxide transistors (Oxide TFTs) and Low Temperature polysilicon thin film transistors (LTPS TFTs). Thus, in the retention period, the good TFT characteristics of LTPO can retain enough electric quantity to maintain the luminance of the pixel, and black stripes and flickers are less likely to occur compared to LTPS display panels.

In addition, the display device in the embodiment of the disclosure may include other necessary components and structures besides the structures of the display panel and the driving device, for example, a Source Driver (Source Driver) circuit, and the like, and those skilled in the art may design and supplement the display device accordingly according to the type of the display device, and will not be described herein again.

In an exemplary embodiment, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer or a navigator, etc. Here, the embodiment of the present disclosure does not limit the type of the display device. Other essential components of the display device are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present disclosure.

The above description of the apparatus embodiments, similar to the above description of the method embodiments, has similar beneficial effects as the method embodiments. For technical details that are not disclosed in the embodiments of the display device of the present disclosure, those skilled in the art should understand the description in the embodiment of the driving method of the present disclosure with reference to the description, and thus the description is omitted here.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

Although the embodiments disclosed in the present disclosure are described above, the above description is only for the convenience of understanding the present disclosure, and is not intended to limit the present disclosure. It will be understood by those skilled in the art of the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the terms of the appended claims.

Claims

1. A driving method applied to a display panel, the display panel comprising: the display panel comprises a first display area and a second display area, wherein a plurality of grid lines of the first display area are connected with a first grid driver, and a plurality of grid lines of the second display area are connected with a second grid driver;

the driving method includes: when the display panel is driven, the following operations are executed for each frame of display duration:

2. The driving method according to claim 1, wherein the enable initialization signal is a Pulse Width Modulation (PWM) signal, one frame display duration is K times a period of the PWM signal, and K is any one of 6, 8, and 12.

3. The driving method according to claim 1, wherein a duration of the first display period and a duration of the second display period are equal.

4. A driving method according to any one of claims 1 to 3, wherein the ratio between the duration of the first driving period and the duration of the first holding period and the ratio between the duration of the second driving period and the duration of the second holding period are both preset integer values, the preset integer values being 2 or 3.

5. The driving method according to claim 1, wherein a time interval between a trigger timing of the second scan start signal and a trigger timing of the first scan start signal is one-half of a display time period of one frame.

6. A driving apparatus, applied to a display panel, the display panel comprising: a first display area and a second display area, the first display area and the second display area respectively comprising: a plurality of gate lines;

7. The drive device according to claim 6,

the first gate driver includes: a first shift register set, the first shift register set comprising: a plurality of cascaded first shift registers;

the second gate driver includes: a second shift register set, the second shift register set comprising: a plurality of cascaded second shift registers;

the driving controller configured to supply the first scan start signal and the enable start signal to a first stage shift register of the plurality of cascaded first shift registers in a first display period; and providing the second scan start signal and the enable initialization signal to a first stage shift register of the plurality of cascaded second shift registers in a second display period.

8. The driving apparatus according to claim 6, wherein the enable initialization signal is a Pulse Width Modulation (PWM) signal, a frame display duration is K times a period of the PWM signal, and K is any one of 6, 8, and 12.

9. The driving apparatus according to claim 6, wherein the duration of the first display period and the duration of the second display period are equal.

10. The drive device according to claim 6, wherein a ratio between a time length of the first drive period and a time length of the first holding period and a ratio between a time length of the second drive period and a time length of the second holding period are both preset integer values, and the preset integer value is 2 or 3.

11. The driving apparatus according to claim 6, wherein a time interval between a trigger timing of the second scan start signal and a trigger timing of the first scan start signal is one-half of a display time period of one frame.

12. A display device, comprising: a display panel and a driving device according to any one of claims 6 to 11, wherein the display panel includes: a first display area and a second display area, the first display area and the second display area respectively including: a plurality of gate lines.

13. The display device according to claim 12, wherein the first display region and the second display region respectively include: a pixel drive circuit, the pixel drive circuit comprising: oxide thin film transistors and low temperature polysilicon thin film transistors.