CN113672550A - Computing system, server and signal transmission method - Google Patents
Computing system, server and signal transmission method Download PDFInfo
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Abstract
A computing system, a server and a signal transmission method are used for improving data transmission speed and data quantity between chips. In the application, the computing system comprises a first chip, a first transceiver, a second chip and a second transceiver, wherein the first transceiver is connected with the first chip, and the second transceiver is connected with the second chip; the first chip transmits the parallel signal. The first transceiver receives the parallel signal, converts the parallel signal into an optical signal, and transmits the optical signal to the second transceiver. The second transceiver receives the optical signal, converts the optical signal into a parallel signal and transmits the parallel signal to the second chip; thereafter, the second chip may receive the parallel signal. The data interaction between the first chip and the second chip is based on the optical signal. Compared with an electric signal, the optical signal has the advantages of stronger anti-interference performance, high transmission speed, better data integrity and higher data transmission efficiency. The optical signal can load more data, and the data volume of data transmission between chips is improved.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a computing system, a server, and a signal transmission method.
Background
With the rapid development of artificial intelligence and big data, in order to meet the demand of computing diversification, other hardware, such as Accelerators (ACC) such as a Graphic Processing Unit (GPU), an application-specific integrated circuit (ASIC), a programmable gate array (FPGA), etc., is introduced into a computing system in addition to a Central Processing Unit (CPU), and these newly introduced hardware and the CPU cooperate to realize various different computing tasks. Based on the above, a novel computing system, namely a heterogeneous computing system, is formed.
By heterogeneous computing system is meant that the various hardware in the system, such as CPUs, GPUs, ASICs, FPGAs, etc., use different types of instruction sets. However, the core of the heterogeneous computing system is still a CPU, the CPU as a dispatcher needs to perform a large amount of data interaction with other hardware, and at present, an electrical interface is usually adopted in the heterogeneous computing system to perform data interaction, that is, a high speed serial deserializer (HSS) is used to transmit and receive an electrical signal.
However, as the performance of the CPU is improved, the data processing capability of the CPU is also improved significantly, the amount of data interaction between the CPUs and other hardware is also increased, and the disadvantages of the electrical interface in terms of bandwidth, interference resistance and signal loss are increasingly highlighted.
Disclosure of Invention
The application provides a computing system, a server and a signal transmission method, which are used for improving the data transmission speed and the data volume between chips.
In a first aspect, an embodiment of the present application provides a computing system, which includes a first chip, a first transceiver, a second chip, and a second transceiver, where the first transceiver is connected to the first chip, and the second transceiver is connected to the second chip; in the computing system, a first chip may transmit parallel signals. The first transceiver receives the parallel signal, converts the parallel signal into an optical signal, and transmits the optical signal to the second transceiver, for example, the first transceiver may transmit the optical signal to the second transceiver through an optical switching network. The second transceiver receives the optical signal, converts the optical signal into a parallel signal and transmits the parallel signal to the second chip; thereafter, the second chip receives the parallel signal, and may perform a subsequent data processing operation.
With the above computing system, the data interaction between the first chip and the second chip is no longer based on electrical signals, but on optical signals. Compared with an electric signal, the optical signal has the advantages of stronger anti-interference performance, high transmission speed, better data integrity and higher data transmission efficiency. In addition, more data can be loaded by the optical signal, and the data volume of data transmission between chips is also improved.
In one possible design, the first transceiver is built into the first chip and the second transceiver is built into the second chip.
Through the computing system, the first chip and the second chip have the photoelectric conversion function, the conversion between the parallel signals and the optical signals is more efficient, the building process of the computing system is simplified, and the structure of the computing system is simpler.
In one possible design, the first transceiver includes a transmitter including a first serializer, a modulator, and a first optical waveguide; the first deserializer can perform serial-parallel conversion and convert a parallel signal into a serial signal; the modulator can adjust signals and modulate serial signals on original optical signals to generate optical signals; the first optical waveguide is used for transmitting an optical signal. The first transceiver may further include a receiver having a structure similar to that of the receiver in the second transceiver, the receiver being capable of converting the received optical signal into a parallel signal.
Through the computing system, the transmitter and the receiver in the first transceiver can realize photoelectric conversion and serial-parallel conversion, and the system is simple in structure and easy to realize.
In one possible design, if the modulator generates a plurality of optical signals, the first transceiver may further include a first wavelength division multiplexer; the first wavelength division multiplexer is capable of modulating the plurality of optical signals on the first optical waveguide, selecting a transmission path on the first optical waveguide for the plurality of optical signals.
Through the computing system, the first wavelength division multiplexer can process a plurality of optical signals, the data volume which can be transmitted in one time in the data transmission process is further improved, and meanwhile, the data transmission efficiency is also guaranteed.
In one possible design, the second transceiver includes a receiver including a second serializer, a demodulator, and a second optical waveguide; the second optical waveguide may receive an optical signal; the demodulator can demodulate signals and demodulate optical signals into serial signals; thereafter, the second deserializer may perform serial-to-parallel conversion, converting the serial signal to a parallel signal. The second transceiver may further include a transmitter having a structure similar to that of the transmitter in the first transceiver, the transmitter being capable of converting the received parallel signal into an optical signal.
Through the computing system, the transmitter and the receiver in the second transceiver can realize photoelectric conversion and serial-parallel conversion, and the system is simple in structure and easy to realize.
In a possible design, if the second optical waveguide receives a plurality of optical signals, the receiver further includes a second wavelength division multiplexer; the second wavelength division multiplexer may obtain a plurality of optical signals from the second optical waveguide.
Through the computing system, the second wavelength division multiplexer can process a plurality of optical signals, the data volume which can be transmitted in one time in the data transmission process is further improved, and the data transmission efficiency is higher.
In a second aspect, embodiments of the present application provide a server comprising a computing system as provided in the first aspect and as in any one of the possible designs of the first aspect.
In a third aspect, the present application provides a signal transmission method, and beneficial effects may refer to related descriptions of the first aspect, which are not described herein again. The method is executed by a computing system, wherein the computing system comprises a first chip, a first transceiver, a second chip and a second transceiver, the first transceiver is connected with the first chip, the second transceiver is connected with the second chip, the first chip sends signals, the second chip receives signals as an example, and a signal transmission method in the computing system is explained;
the first chip may transmit the parallel signal to the first transceiver; after receiving the parallel signals, the first transceiver converts the parallel signals into optical signals and transmits the optical signals to the second transceiver through the optical switching network; after receiving the optical signal, the second transceiver can convert the optical signal into a parallel signal and transmit the parallel signal to the second chip; thereafter, the second chip may receive the parallel signal.
In one possible design, the first transceiver includes a transmitter including a first deserializer, a modulator, and a first optical waveguide, the first transceiver converts a parallel signal into an optical signal after receiving the parallel signal, and the first deserializer in the transmitter converts the parallel signal into a serial signal when transmitting the optical signal to the second transceiver over the optical switching network; then, the modulator modulates the serial signal on the original optical signal to generate an optical signal; the first optical waveguide re-transmits the optical signal.
In one possible design, if the modulator generates a plurality of optical signals, the first transceiver further comprises a first wavelength division multiplexer, and the first wavelength division multiplexer may modulate the plurality of optical signals onto the first optical waveguide.
In one possible design, the second transceiver includes a receiver, the receiver includes a second serializer/deserializer, a demodulator, and a second optical waveguide, the second transceiver converts the optical signal into a parallel signal after receiving the optical signal, and the second optical waveguide in the receiver receives the optical signal when transmitting the parallel signal to the second chip; then, the demodulator demodulates the optical signal into a serial signal; the second serializer deserializes the serial signal into a parallel signal.
In one possible design, the second optical waveguide receives the plurality of optical signals, and the receiver further includes a second wavelength division multiplexer that can tap the plurality of optical signals from the second optical waveguide.
Drawings
FIG. 1A is a schematic diagram of a computing system according to the present application;
FIG. 1B is a diagram illustrating signal transmission in a computing system according to the present application;
fig. 2 is a schematic structural diagram of a first chip provided in the present application;
FIGS. 3A-3B are schematic structural diagrams of a computing system according to the present application;
fig. 4 is a schematic structural diagram of a first transceiver provided in the present application;
fig. 5 is a schematic structural diagram of a second transceiver provided in the present application;
fig. 6A to 6C are schematic structural diagrams of a first transmitter provided in the present application;
fig. 7A to 7C are schematic structural diagrams of a first transmitter provided in the present application;
FIG. 8 is a schematic diagram of a server according to the present application;
fig. 9 is a schematic diagram of a signal transmission method provided in the present application.
Detailed Description
For convenience of description, only two chips, namely a first chip and a second chip, are included in the computing system.
Referring to fig. 1A, the computing system 10 includes a first chip 100, a first transceiver 200, a second chip 300, and a second transceiver 400. The first chip 100 is connected to the first transceiver 200, the first chip 100 and the first transceiver 200 can perform signal transmission therebetween, the second chip 300 and the second transceiver 400 are connected, and the second chip 300 and the second transceiver 400 can perform signal transmission therebetween. It should be noted that the signal herein generally refers to an electrical signal loaded with data. The electrical signal may be a parallel signal or a serial signal, and in the embodiment of the present invention, the signals transmitted between the first chip 100 and the first transceiver 200 and between the second chip 300 and the second transceiver 400 are parallel signals, for example.
Referring to fig. 1B, fig. 1B is a schematic diagram of a signal transmission process in the computing system 10, where parallel solid lines indicate parallel signals, dashed lines indicate optical signals, and arrows indicate a transmission direction of the signals, the first chip 100 may generate the parallel signals, and the generated parallel signals may be transmitted to the first transceiver 200. After receiving the parallel signal, the first transceiver 200 may further process the parallel signal, convert the parallel signal into an optical signal, and transmit the optical signal to the second transceiver 400 through the optical switching network.
The optical switch network is a communication network including a plurality of optical fibers, and optionally, the optical switch network may further include an optical switch, where the optical switch is configured to select a transmission path for an optical signal transmitted in the optical switch network.
The optical switch network may transmit the optical signal from the first transceiver 200 to the second transceiver 400, after receiving the optical signal, the second transceiver 400 may further process the optical signal, convert the optical signal into a parallel signal, transmit the parallel signal to the second chip 300, and the second chip 300 receives the parallel signal, may obtain data loaded on the parallel signal, and perform data processing.
In the above description, only the first chip 100 is taken as an example of a transmitter of the parallel signal, and the second chip 300 is taken as an example of a receiver of the parallel signal, in fact, in a transmission process of the signal, a signal transmission process of the second chip 300 and the first chip 100 is mutual, that is, the second chip 300 may also send the parallel signal, and the parallel signal is transmitted to the first chip 100 after passing through the second transceiver 400, the optical switching network and the first transceiver 200.
In the computing system 10 as illustrated in fig. 1B, the data interaction between the first chip 100 and the second chip 300 is no longer based on electrical signals, but rather optical signals. Compared with an electric signal, the optical signal has stronger anti-interference performance and high transmission speed, and can ensure the integrity of data and the high efficiency of data transmission during data transmission between chips. And the optical signal can load more data, and the data volume of data transmission between chips is also improved.
The embodiment of the present application does not limit the type of the chip (the first chip 100 and the second chip 300), and the chip may be a CPU, or may be other accelerators, such as a GPU, an ASIC, and an FPGA. The embodiment of the present invention does not limit the specific structure of the chip, and may be a 2D chip, a 3D chip, or a neural Network Processing Unit (NPU). The 2D chip refers to a processing module in a chip, such as a wafer (die) of a CPU, and is disposed on the same plane as an input/output (IO) module, and the 3D chip refers to a processing module in a chip, such as a CPU die, and is disposed on a different plane from an input/output (IO) module.
As can be seen from the above description, the transceivers (the first transceiver 200 and the second transceiver 400) according to the embodiments of the present application have a signal conversion function and a signal transmission function, where the signal conversion function includes, but is not limited to: the parallel signal is converted into an optical signal, and the optical signal is converted into a parallel signal.
The embodiment of the present application does not limit the connection relationship between the transceiver and the chip, for example, the first transceiver 200 may be externally disposed on the periphery of the first chip 100. The first transceiver 200 may also be built in the first chip 100, that is, the first transceiver 200 may be built in the first chip 100 as a component of an IO module for signal transmission in the first chip 100. The connection relationship between the second transceiver 400 and the second chip 300 is similar to the connection relationship between the first transceiver 200 and the first chip 100, and is not described herein again.
Next, a mode in which the first chip 100 incorporates the first transceiver 200 will be described using the first chip 100 as a CPU. Fig. 2 is a schematic structural diagram of the first chip 100.
The first chip 100 uses a silicon chip as a substrate, and a first transceiver 200 and a plurality of CPU die are disposed on the silicon chip, and there is a connection between the plurality of CPU die to form a core of the CPU, which may also be regarded as a processing module of the CPU, and the plurality of CPU die are used to implement a data processing function of the CPU. The first transceiver 200 is connected to the CPU die, and the first transceiver 200 may receive a signal from the CPU die, transmit the signal to the outside, and transmit a signal received from the outside (e.g., an optical switching network) to the CPU die. The first transceiver 200 is capable of data transmission and can be regarded as an IO module of the CPU or as a component of the IO module. The number of the first transceivers 200 in the first chip 100 is not limited in the embodiments of the present application, and may be one or more.
In the computing system 10 provided in the embodiment of the present application, due to the photoelectric conversion, the first transceiver 200 needs to load the data carried by the parallel signal into the original optical signal to generate the optical signal, that is, the light source is required to generate the original optical signal. The light source may be external to the computing system 10, and if the first chip 100 and the first transceiver 200 are integrated into an on-chip system, the light source may be an off-chip light source, coupled to the computing system 10, and configured to transmit the original optical signal to the first transceiver 200 in the computing system 10 through an optical waveguide.
As shown in fig. 3A, an off-chip light source 500 may be disposed in the computing system 10, the off-chip light source 500 being configured to generate an original optical signal, the original optical signal being received by the first transceiver 200, and data carried on the parallel signal is loaded on the original optical signal to generate the optical signal.
The light source may be built in the computing system 10, or integrated on-chip if the first chip 100 and the first transceiver 200 are integrated as a system-on-chip, that is, the light source may be an on-chip light source.
As shown in fig. 3B, the computing system 10 may further include an on-chip light source 600, the on-chip light source 600 functions similarly to the off-chip light source 500, and the off-chip light source 500 and the on-chip light source 600 are different in arrangement position, which can be referred to in the foregoing description.
In the descriptions of fig. 3A and 3B, only the first chip 100 is used for transmitting the parallel signal and the light source is additionally provided as an example, and if the second chip 300 needs to transmit the parallel signal, the light source (such as the on-chip light source 600 or the off-chip light source 500) is also required to generate the original optical signal and transmit the original optical signal to the second transceiver 400.
The following describes the structures of the transceivers (the first transceiver 200 and the second transceiver 400) according to the embodiments of the present application. For convenience of description, the parallel signal transmitted by the first chip 100 is referred to as a first parallel signal, the optical signal transmitted by the first transceiver 200 is a first optical signal, the parallel signal transmitted by the second chip 300 is referred to as a second parallel signal (the second parallel signal may also be understood as a parallel signal that needs to be received by the first chip 100), and the optical signal transmitted by the second transceiver 400 is a second optical signal.
As shown in fig. 4, a schematic structural diagram of a first transceiver 200 according to an embodiment of the present disclosure is provided, where the first transceiver 200 includes a first transmitter 210 and a first receiver 220.
The first transmitter 210 is configured to convert the first parallel signal into a first optical signal, and transmit the first optical signal to the second transceiver 400 through the optical switching network.
The first receiver 220 is configured to receive a second optical signal from the second transceiver 400 through the optical switching network, convert the second optical signal into a second parallel signal, and send the second parallel signal to the first chip 100.
When the first transmitter 210 converts the first parallel signal into the first optical signal, it may perform serial-to-parallel conversion to convert the first parallel signal into the first serial signal, and then modulate the first serial signal onto the original optical signal to generate the first optical signal.
When the first receiver 220 converts the second optical signal into the second parallel signal, the second optical signal may be demodulated into a second serial signal, and then serial-to-parallel conversion may be performed to convert the second serial signal into the second parallel signal.
As shown in fig. 5, a schematic structural diagram of a second transceiver 400 provided in the embodiment of the present application is provided, where the second transceiver 400 includes a second transmitter 410 and a second receiver 420.
The second receiver 420 is configured to receive the first optical signal from the first transceiver 200 through the optical switch network, convert the first optical signal into a first parallel signal, and send the first parallel signal to the second chip 300.
A second transmitter 410, configured to convert the second parallel signal into a second optical signal, and transmit the second optical signal to the first transceiver 200 through the optical switching network.
When the second receiver 420 converts the first optical signal into the first parallel signal, the first optical signal may be demodulated into a first serial signal, and then converted into a first parallel signal by serial-to-parallel conversion.
The second transmitter 410 may perform serial-to-parallel conversion to convert the second parallel signal into the second serial signal when converting the second parallel signal into the second optical signal, and then modulate the second serial signal onto the original optical signal to generate the second optical signal.
The following describes the transmitters (the first transmitter 210 and the second transmitter 410) according to the present application, taking the first transmitter 210 as an example:
as shown in fig. 6A, for a first transmitter 210 according to an embodiment of the present application, the first transmitter 210 includes a first deserializer 211, a modulator 212, and a first optical waveguide 213.
The first deserializer 211 may perform serial-to-parallel conversion, and may convert the first parallel signal into a first serial signal; modulator 212 may modulate the first serial signal onto an original optical signal to generate a first optical signal; the first optical waveguide 213 may then transmit the first optical signal into an optical switching network.
If the modulator 212 generates a plurality of first optical signals, the first transmitter 210 may further include a first wavelength division multiplexer 214, as shown in fig. 6B, the first wavelength division multiplexer 214 may modulate the plurality of first optical signals on the first optical waveguide 213, each of the plurality of first optical signals may be transmitted on one transmission channel of the first optical waveguide 213, and each of the plurality of first optical signals may be transmitted on a different transmission channel, so that the plurality of first optical signals may propagate on the same first optical waveguide 213.
When the first deserializer 211 performs the serial-parallel processing, the generated first serial signal may be mixed with noise data and the signal strength may be weakened. As shown in fig. 6C, the first transmitter 210 may further include a pre-processing module 215, the pre-processing module 215 is located between the first deserializer 211 and the modulator 212, and is capable of calibrating the first serial signal, and the calibration operations performed by the pre-processing module 215 include, but are not limited to: denoising, signal enhancement and signal equalization.
The embodiment of the present application does not limit the connection manner between the first serializer 211 and the modulator 212, for example, when the first serializer 211 and the modulator 212 are integrated on the same silicon chip, an interconnect (interconnect) in a silicon-based inter-layer dielectric (silicon on insulator) in the silicon chip may be used. For another example, when the first deserializer 211 and the modulator 212 are integrated on the same substrate, they may be directly interconnected by a transmission line within the package substrate (package substrate). Also for example, the first serializer 211 and the modulator 212 may be interconnected by a high-density cable (cable).
In the embodiment of the present application, the connection modes between the modulator 212 and the first optical waveguide 213, between the modulator 212 and the first wavelength division multiplexer 214, and between the first wavelength division multiplexer 214 and the first optical waveguide 213 are not limited, and since optical signals need to be transmitted between the modulator 212 and the first optical waveguide 213, between the modulator 212 and the first wavelength division multiplexer 214, and between the first wavelength division multiplexer 214 and the first optical waveguide 213, optical fibers may be directly connected between the modulator 212 and the first optical waveguide 213, between the modulator 212 and the first wavelength division multiplexer 214, and between the first wavelength division multiplexer 214 and the first optical waveguide 213.
The following describes the receivers (the first receiver 220 and the second receiver 420) according to the present application, taking the second receiver 420 as an example:
as shown in fig. 7A, for a second receiver 420 provided in the embodiment of the present application, the second receiver 420 includes a second serializer 421, a demodulator 422, and a second optical waveguide 423;
the second optical waveguide 423 may receive a first optical signal from the optical switching network; thereafter, the demodulator 422 may demodulate the first optical signal into a first serial signal; the second serializer 421 may convert the first serial signal into a first parallel signal and transmit the first parallel signal to the second chip 300.
If the second optical waveguide 423 receives a plurality of first optical signals, and if a plurality of second optical signals exist, the receiver further includes a second wavelength division multiplexer 424; as shown in fig. 7B, the second wavelength division multiplexer 424 may obtain a plurality of first optical signals from the second optical waveguide 423, that is, the second wavelength division multiplexer 424 may obtain a plurality of first optical signals from a plurality of transmission channels of the second optical waveguide 423, and the second wavelength division multiplexer 424 may obtain one first optical signal from one transmission channel.
In the transmission process of the first optical signal, there may be signal attenuation and noise data may be introduced, so that the noise data may be mixed in the first parallel signal generated after the serial-parallel processing by the second serdes 421, and the signal intensity becomes small; the second deserializer 421 may also have signal attenuation or noise data introduced during the serial-parallel processing, and as shown in fig. 7C, the second receiver may further include a post-processing module 425, the post-processing module 425 is located at the output end side of the second deserializer 421, and can calibrate the second parallel signal, and the calibration operation performed by the post-processing module 425 includes but is not limited to: denoising, signal enhancement and signal equalization.
The connection between the second deserializer 421 and the demodulator 422 is similar to the connection between the first deserializer 211 and the modulator 212, which can be referred to the above specifically, and is not described herein again.
The connection manner between the demodulator 422 and the second optical waveguide 423 is similar to the connection manner between the modulator 212 and the first optical waveguide 213, the connection manner between the demodulator 422 and the second wavelength division multiplexer 424 is similar to the connection manner between the modulator 212 and the first wavelength division multiplexer 214, and the connection manner between the second wavelength division multiplexer 424 and the second optical waveguide 423 is similar to the connection manner between the first wavelength division multiplexer 214 and the first optical waveguide 213, which may be referred to the foregoing specifically, and is not described herein again.
As shown in fig. 8, the embodiment of the present application further provides a server, where the server 20 includes the computing system 10 in any of the foregoing embodiments.
In order to make the description of the scheme clearer, the following will generally describe the transmission flow of signals in the computing system provided in the embodiment of the present invention, by taking the computing system shown in fig. 1A and the signal transmission method shown in fig. 9 as an example, in combination with the foregoing embodiment. As shown in fig. 9, in the computing system 10, the first chip 100 may transmit a parallel signal to the first transceiver 200 (step 1); after receiving the parallel signal, the first transceiver 200 may convert the parallel signal into an optical signal (step 2), and transmit the optical signal to the second transceiver 400 through the optical switching network (step 3); after receiving the optical signal, the second transceiver 400 may convert the optical signal into a parallel signal (step 4), and transmit the parallel signal to the second chip 300 (step 5); thereafter, the second chip 300 may receive the parallel signal.
The information processing procedure of the transmitter 210 in the first transceiver 200 and the signal processing procedure of the receiver 420 in the second transceiver 400 can be referred to the foregoing description and are not described herein again.
It should be noted that the examples provided in this application are only illustrative. It will be apparent to those skilled in the art that, for convenience and brevity of description, the description of the various embodiments has been focused on, and for parts of one embodiment that are not described in detail, reference may be made to the description of other embodiments. The features disclosed in the embodiments of the invention, in the claims and in the drawings may be present independently or in combination. Features described in hardware in embodiments of the invention may be implemented by software and vice versa. And are not limited herein.
Claims (12)
1. A computing system comprising a first chip, a first transceiver, a second chip, and a second transceiver, wherein the first transceiver is connected to the first chip and the second transceiver is connected to the second chip;
the first chip is used for sending parallel signals;
the first transceiver is configured to receive the parallel signal, convert the parallel signal into an optical signal, and send the optical signal to the second transceiver through an optical switching network;
the second transceiver is configured to receive the optical signal, convert the optical signal into the parallel signal, and transmit the parallel signal to the second chip;
the second chip is used for receiving the parallel signals.
2. The computing system of claim 1, wherein the first transceiver is built in the first chip and the second transceiver is built in the second chip.
3. The computing system of claim 1 or 2, wherein the first transceiver comprises a transmitter comprising a first serializer, a modulator, and a first optical waveguide;
the first deserializer is used for converting the parallel signal into a serial signal;
the modulator is used for modulating the serial signal on an original optical signal to generate the optical signal;
the first optical waveguide is used for transmitting the optical signal.
4. The computing system of claim 3, wherein if the modulator generates a plurality of the optical signals, the first transceiver further comprises a first wavelength division multiplexer;
the first wavelength division multiplexer is configured to modulate a plurality of the optical signals onto the first optical waveguide.
5. The computing system of claim 1 or 2, wherein the second transceiver comprises a receiver comprising a second serializer, a demodulator, and a second optical waveguide;
the second optical waveguide is used for receiving the optical signal;
the demodulator is used for demodulating the optical signal into a serial signal;
the second serializer/deserializer is configured to convert the serial signal into the parallel signal.
6. The computing system of claim 5, wherein the second optical waveguide receives a plurality of the optical signals, the receiver further comprising a second wavelength division multiplexer;
the second wavelength division multiplexer is configured to obtain a plurality of optical signals from the second optical waveguide.
7. A server, comprising a computing system as claimed in any one of claims 1 to 6.
8. A method of signal transmission, the method performed by a computing system comprising a first chip, a first transceiver, a second chip, and a second transceiver, wherein the first transceiver is coupled to the first chip and the second transceiver is coupled to the second chip, the method comprising;
the first chip sends parallel signals to the first transceiver;
after receiving the parallel signal, the first transceiver converts the parallel signal into an optical signal and sends the optical signal to the second transceiver through an optical switching network;
after receiving the optical signal, the second transceiver converts the optical signal into the parallel signal and transmits the parallel signal to a second chip;
the second chip receives the parallel signal.
9. The method according to claim 8, wherein the first transceiver comprises a transmitter comprising a first serializer, a modulator, and a first optical waveguide, and wherein the first transceiver receives the parallel signal, converts the parallel signal into an optical signal, and transmits the optical signal to the second transceiver through an optical switching network, including;
the first deserializer converts the parallel signal into a serial signal;
the modulator modulates the serial signal on an original optical signal to generate the optical signal;
the first optical waveguide transmits the optical signal.
10. The method of claim 9, wherein if said modulator generates a plurality of said optical signals, said first transceiver further comprises a first wavelength division multiplexer, said method further comprising;
the first wavelength division multiplexer modulates the plurality of optical signals on the first optical waveguide.
11. The method of claim 8, wherein the second transceiver comprises a receiver, the receiver comprises a second serializer/deserializer, a demodulator and a second optical waveguide, and the second transceiver receives the optical signal, converts the optical signal into the parallel signal, and transmits the parallel signal to a second chip, specifically comprising:
the second optical waveguide receives the optical signal;
the demodulator demodulates the optical signal into a serial signal;
the second serializer deserializer converts the serial signal into the parallel signal.
12. The method of claim 11, wherein the second optical waveguide receives a plurality of the optical signals, the receiver further comprising a second wavelength division multiplexer, the method further comprising:
the second wavelength division multiplexer obtains a plurality of the optical signals from the second optical waveguide.
Priority Applications (2)
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| CN202010402044.2A CN113672550A (en) | 2020-05-13 | 2020-05-13 | Computing system, server and signal transmission method |
| PCT/CN2021/091219 WO2021227890A1 (en) | 2020-05-13 | 2021-04-29 | Computing system, server, and signal transmission method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010402044.2A CN113672550A (en) | 2020-05-13 | 2020-05-13 | Computing system, server and signal transmission method |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070060175A (en) * | 2005-12-08 | 2007-06-13 | 주식회사 하이닉스반도체 | Semiconductor integrated circuit |
| CN101573903A (en) * | 2006-11-08 | 2009-11-04 | 菲尼萨公司 | Serializer/deserializers for use in optoelectronic devices |
| CN102169270A (en) * | 2010-02-25 | 2011-08-31 | 三星电子株式会社 | Optical serializing/deserializing apparatus and method and method of manufacturing same |
| CN106508099B (en) * | 2009-06-17 | 2014-05-14 | 上海电控研究所 | Vehicle-mounted high speed fibre Transmission system |
| CN105610509A (en) * | 2015-12-21 | 2016-05-25 | 北京航天时代光电科技有限公司 | 160-M optical transmission device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104734781B (en) * | 2015-03-02 | 2017-04-12 | 中国人民解放军国防科学技术大学 | Optical transceiver with serial-parallel conversion function |
| JP6844229B2 (en) * | 2016-08-26 | 2021-03-17 | 住友電気工業株式会社 | Host board, optical receiver, optical transmitter, optical transceiver, and how to mount the optical transceiver on the host board |
-
2020
- 2020-05-13 CN CN202010402044.2A patent/CN113672550A/en active Pending
-
2021
- 2021-04-29 WO PCT/CN2021/091219 patent/WO2021227890A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070060175A (en) * | 2005-12-08 | 2007-06-13 | 주식회사 하이닉스반도체 | Semiconductor integrated circuit |
| CN101573903A (en) * | 2006-11-08 | 2009-11-04 | 菲尼萨公司 | Serializer/deserializers for use in optoelectronic devices |
| CN106508099B (en) * | 2009-06-17 | 2014-05-14 | 上海电控研究所 | Vehicle-mounted high speed fibre Transmission system |
| CN102169270A (en) * | 2010-02-25 | 2011-08-31 | 三星电子株式会社 | Optical serializing/deserializing apparatus and method and method of manufacturing same |
| CN105610509A (en) * | 2015-12-21 | 2016-05-25 | 北京航天时代光电科技有限公司 | 160-M optical transmission device |
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| WO2021227890A1 (en) | 2021-11-18 |
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