CN113672017B - Self-adaptive mode switching charge pump - Google Patents

Self-adaptive mode switching charge pump Download PDF

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CN113672017B
CN113672017B CN202110903453.5A CN202110903453A CN113672017B CN 113672017 B CN113672017 B CN 113672017B CN 202110903453 A CN202110903453 A CN 202110903453A CN 113672017 B CN113672017 B CN 113672017B
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forty
terminal
input
output
drain
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CN113672017A (en
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马迎
岑远军
刘中伟
冯浪
李永凯
王达海
张得力
文皓
刁小芃
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Chengdu Hua Microelectronics Technology Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters

Abstract

The invention relates to an adaptive mode switching charge pump, which relates to an integrated circuit and comprises a second power tube, a first power tube, a thirty-one MOS tube, a reference and adaptive mode switching circuit, a first comparator, a digital logic circuit, a second comparator, a third power tube and a fourth power tube. The whole circuit structure of the invention enables the chip to have the functions of boosting and reducing voltage, and the input voltage range is enlarged.

Description

Self-adaptive mode switching charge pump
Technical Field
The present invention relates to integrated circuit technology.
Background
In the practical application environment of the power management chip, the efficiency and the voltage input range are extremely important index parameters. Although the LDO can provide a low noise output voltage, its efficiency
Figure GDA0003676015270000011
Very low, e.g., Vin-5V, Vout-3.3V, whichThe efficiency is equal to about 66%.
The control mode of the charge pump chip includes many kinds, and the common control mode is the PWM control mode, see fig. 1 and fig. 2, and the control mode has the disadvantage that under the light load condition, the chip still operates according to the fixed conversion frequency, and the chip efficiency parameter is reduced.
The common charge pump has 1.5 times and 2 times of voltage, can not realize voltage reduction, and limits the range of input voltage.
Disclosure of Invention
The invention aims to solve the technical problem of providing a self-adaptive mode switching charge pump, so that a chip can reduce the conversion frequency, increase the cycle time and improve the efficiency under the condition of light load.
The technical scheme adopted by the invention for solving the technical problems is that the self-adaptive mode switching charge pump is characterized by comprising the following parts:
a second POWER tube (POWER2), the source terminal of which is connected with the voltage input point Vin, the gate terminal of which is connected with the output terminal of the second Buffer (Buffer2), and the drain terminal of which is connected with the third external connection point;
the drain terminal of the first POWER tube (POWER1) is connected with the drain terminal of the second POWER tube, the grid terminal is connected with the output terminal of the first Buffer (Buffer1), and the source terminal is grounded;
a thirty-first MOS tube, wherein the grid end of the thirty-first MOS tube is connected with the output end of the first Buffer (Buffer1), the source end of the thirty-first MOS tube is grounded, and the drain end of the thirty-first MOS tube is connected with the first output end of the reference and self-adaptive mode switching circuit;
a second output end of the reference and self-adaptive mode switching circuit is connected with a second input end of a first Buffer (Buffer1), a third output end and a fourth output end are respectively connected with two input ends of a first comparator, an input end (FB) of the reference and self-adaptive mode switching circuit is grounded through a first feedback resistor, and is also connected with a fourth external connection point through a second feedback resistor;
The output end of the first comparator is connected with the input end of the oscillator, and the output end of the oscillator is connected with the control end of the digital logic circuit;
a digital logic circuit, a first input of which is connected with the output end of the second comparator, a second input of which is connected with the output end of the first Buffer (Buffer1), a first output of which is connected with the first input end of the first Buffer (Buffer1), a second output of which is connected with the input end of the second Buffer (Buffer2), a third output of which is connected with the input end of the third Buffer (Buffer3), and a fourth output of which is connected with the input end of the fourth Buffer (Buffer 4);
a second comparator, the negative input end of which is connected with the voltage input point Vin, and the positive input end of which is connected with the first external connection point;
the source end of the third power tube is connected with the first external connection point, the grid end of the third power tube is connected with the output end of the third buffer, and the drain end of the third power tube is connected with the second external connection point and the source end of the fourth power tube;
and the grid end of the fourth power tube is connected with the output end of the fourth buffer, and the drain end of the fourth power tube is connected with the voltage input point Vin.
The invention may also connect the second external connection point and the third external connection point via a capacitor via an off-chip circuit connection. The first external connection point and the fourth external connection point are connected with a final-stage output point, and the final-stage output point is grounded through a capacitor.
The reference and adaptive mode switching circuit includes:
a forty-first NMOS transistor, wherein the drain end and the gate end of the forty-third PMOS transistor are connected with the drain end of the forty-third PMOS transistor, and the source end of the forty-first NMOS transistor is grounded through a resistor;
a forty-second NMOS transistor, wherein the gate end of the forty-second NMOS transistor is connected with the drain end of a forty-third PMOS transistor, the source end of the forty-second NMOS transistor is grounded through a resistor, and the drain end of the forty-fifth NMOS transistor is connected with the drain end of a forty-fifth PMOS transistor;
a gate end of the forty-third NMOS transistor is connected with a drain end of the forty-fifth PMOS transistor, a source end of the forty-third NMOS transistor is grounded through a resistor, and a drain end of the forty-sixth NMOS transistor is connected with a drain end of the forty-sixth PMOS transistor;
a forty-fifth NMOS transistor, wherein the drain terminal and the gate terminal of the forty-fifth NMOS transistor are connected with the fourth output terminal of the reference and adaptive mode switching circuit, and the source terminal of the forty-fifth NMOS transistor is connected with the first output terminal of the reference and adaptive mode switching circuit;
a forty-sixth NMOS transistor, the source terminal of which is connected with the second output terminal of the reference and adaptive mode switching circuit, the drain terminal of which is connected with the voltage input point Vin, the gate terminal of which is connected with the third output terminal of the reference and adaptive mode switching circuit, and the gate terminal of which is also connected with the fourth output terminal of the reference and adaptive mode switching circuit through a forty-sixth resistor;
a forty-seventh NMOS transistor, the drain terminal of which is connected with the second output terminal of the reference and adaptive mode switching circuit, the source terminal of which is grounded, and the gate terminal of which is connected with the third bias signal input terminal;
a forty-first PMOS transistor with its source terminal connected to the voltage input point Vin and gate terminal connected to the first bias signal input terminal, a forty-second PMOS transistor with its source terminal connected to the voltage input point Vin and gate terminal connected to the first bias signal input terminal,
A forty-third PMOS tube, wherein the source end of the forty-third PMOS tube is connected with the drain end of the forty-first PMOS tube, and the gate end of the forty-third PMOS tube is connected with the input end (FB) of the reference and self-adaptive mode switching circuit;
a forty-fifth PMOS tube, the source end of which is connected with the drain end of the forty-second PMOS tube, and the gate end of which is connected with the input end (FB) of the reference and self-adaptive mode switching circuit;
a forty-sixth PMOS tube, the source end of which is connected with the voltage input point Vin, the gate end of which is connected with the first bias signal input end, and the drain end of which is connected with the third output end of the reference and adaptive mode switching circuit;
a forty-seventh PMOS tube, the gate end of which is connected with the second bias signal input end, and the source end of which is connected with the voltage input point Vin;
a forty-eighth PMOS tube, the grid end of which is connected with the second bias signal input end, the source end of which is connected with the voltage input point Vin, and the drain end of which is connected with the third output end of the reference and self-adaptive mode switching circuit;
a collector of the first triode (491) is connected with a drain end of a forty-second PMOS tube, an emitter of the first triode is connected with an emitter of the second triode (492) through a resistor, and a base of the first triode is connected with an input end (FB) of the reference and self-adaptive mode switching circuit;
and a second triode (492), the collector of which is connected with the drain of the forty first PMOS tube, the emitter of which is grounded through a resistor, and the base of which is connected with the input end (FB) of the reference and self-adaptive mode switching circuit.
The digital logic circuit includes:
the first selector branch circuit is composed of a first selector, an eleventh inverter, a first NAND gate and a twelfth inverter which are sequentially connected in series according to the signal transmission direction, two input ends of the first selector are respectively connected with the control end and the second input end of the digital logic circuit, the other input end of the first NAND gate is connected with the first input end of the digital logic circuit, and the output end of the twelfth inverter is connected with the first output end of the digital logic circuit;
the second selector branch circuit is composed of a second selector, a twenty-first inverter and a twenty-second inverter which are sequentially connected in series according to the signal transmission direction, two input ends of the second selector are respectively connected with the control end and a second input end of the digital logic circuit, and the output end of the twenty-second inverter is connected with a fourth output end of the digital logic circuit;
the third selector branch circuit is composed of a third selector, a thirty-first inverter, a second NAND gate and a thirty-second inverter which are sequentially connected in series according to the signal transmission direction, two input ends of the third selector are respectively connected with the control end and the second input end of the digital logic circuit, the other input end of the second NAND gate is connected with the first input end of the digital logic circuit, and the output end of the thirty-second inverter is connected with the second output end of the digital logic circuit;
And the fourth selector branch circuit is composed of a fourth selector and a forty-first inverter which are sequentially connected in series according to the signal transmission direction, two input ends of the fourth selector are respectively connected with the control end and the second input end of the digital logic circuit, and the output end of the forty-first inverter is connected with the third output end of the digital logic circuit.
The invention designs the self-adaptive mode switching function on the basis of the voltage control mode, so that the conversion frequency of the chip is reduced, the cycle time is increased and the efficiency is improved under the condition of light load. Meanwhile, the whole circuit structure of the invention enables the chip to have the functions of boosting and reducing voltage, and the input voltage range is enlarged.
Drawings
Fig. 1 is a schematic diagram of the prior art.
Fig. 2 is a schematic diagram of a control waveform of the prior art.
Fig. 3 is an overall circuit schematic of the present invention.
Fig. 4 is a circuit diagram of a digital logic circuit.
FIG. 5 is a circuit diagram of the reference and adaptive mode switching circuit of the present invention.
FIG. 6 is a waveform of a cycle time simulation of the power supply input current under light load conditions.
Fig. 7 is a schematic of an efficiency curve of the present invention.
Fig. 8 is a waveform diagram of output ripple simulation under heavy load conditions.
Fig. 9 is a schematic diagram of the charging process in the boost mode.
Fig. 10 is a schematic diagram of a charge transfer process in the boost mode.
Fig. 11 is a schematic diagram in the buck mode.
Fig. 12 is a waveform diagram of simulation in the step-down mode.
Detailed Description
See fig. 3-12. The inside of the dotted line frame in fig. 3, 9, and 11 is divided into the inside of the chip, and the outside of the dotted line frame is divided into the outside of the chip.
Examples
An adaptive mode switching charge pump comprising the following components:
a second POWER transistor POWER2 having a source connected to the voltage input node Vin, a gate connected to the output node B _ output2 of the second Buffer2, and a drain connected to the third external node C XN ；
The drain end of the first POWER tube POWER1 is connected with the drain end of the second POWER tube POWER2, the gate end of the first POWER tube POWER1 is connected with the output end B _ output1 of the first Buffer1, and the source end of the first POWER tube POWER1 is grounded;
a thirty-first MOS transistor NMOS31, having a gate terminal connected to the output terminal B _ output1 of the first Buffer1, a source terminal connected to ground, and a drain terminal connected to the first output terminal N615_ S of the reference and adaptive mode switching circuit;
a reference and adaptive mode switching circuit, a second output terminal N583_ D of which is connected to a second input terminal B _ input2 of the first Buffer1, a third output terminal R55_ MINUS and a fourth output terminal R55_ PLUS are respectively connected to two input terminals of a first comparator (comparator 1 in the figure), an input terminal (FB) of which is connected to ground through a first feedback resistor Rf1, and a fourth external connection point through a second feedback resistor Rf 2;
The OUTPUT terminal X64_ a1 of the first comparator is connected to the input terminal OSC _ EN of the oscillator, and the OUTPUT terminal OSC _ OUTPUT of the oscillator is connected to the control terminal X1023_ a46 of the digital logic circuit;
a digital logic circuit, having a first input terminal S _ input1 connected to the output terminal of the second comparator (comparator 2 in the figure), a second input terminal S _ input2 connected to the output terminal of the first Buffer1, a first output terminal S _ output1 connected to the first input terminal B _ input1 of the first Buffer1, a second output terminal S _ input2 connected to the input terminal of the second Buffer2, a third output terminal S _ output3 connected to the input terminal of the third Buffer3, and a fourth output terminal S _ output4 connected to the input terminal of the fourth Buffer 4;
the negative input end of the second comparator is connected with the voltage input point Vin, and the positive input end of the second comparator is connected with the fifth external connection point;
a source end of the third POWER tube POWER3 is connected with the first external connection point, a gate end is connected with the output end of the third Buffer3, and a drain end is connected with the second external connection point and the source end of the fourth POWER tube POWER 4;
the gate of the fourth POWER transistor POWER4 is connected to the output terminal of the fourth Buffer4, and the drain thereof is connected to the voltage input point Vin.
The above embodiment is a portion integrated in the chip (a portion within a dashed line frame), and the present invention further includes an off-chip circuit portion connecting the second external connection point and the third external connection point via a capacitor. The first external connection point, the fourth external connection point and the fifth external connection point are connected to a final output point, and the final output point is grounded through a capacitor.
The reference and adaptive mode switching circuit includes:
a forty-first NMOS transistor NMOS41, the drain and gate terminals of which are connected to the drain terminal of a forty-third PMOS transistor PMOS43, and the source terminal of which is grounded through a resistor;
a forty-second NMOS transistor NMOS42, the gate of which is connected to the drain of the forty-third PMOS transistor PMOS43, the source of which is grounded through a resistor, and the drain of which is connected to the drain of the forty-fifth PMOS transistor PMOS 45;
a forty-third NMOS transistor NMOS43, the gate of which is connected to the drain of the forty-fifth PMOS transistor PMOS43, the source of which is grounded through a resistor, and the drain of which is connected to the drain of the forty-sixth PMOS transistor PMOS 46;
a forty-fifth NMOS transistor NMOS45, a connection point of a drain terminal and a gate terminal of which is used as a fourth output terminal R55_ PLUS connected to the reference and adaptive mode switching circuit, and a source terminal of which is used as a first output terminal N615_ S connected to the reference and adaptive mode switching circuit;
a forty-sixth NMOS transistor NMOS46, having a source terminal serving as the second output terminal N583_ D of the reference and adaptive mode switching circuit, a drain terminal connected to the voltage input point Vin, a gate terminal connected to the third output terminal R55_ MINUS of the reference and adaptive mode switching circuit, and a gate terminal further connected to the fourth output terminal R55_ PLUS of the reference and adaptive mode switching circuit through a fourth sixteen resistor R46;
a forty-seventh NMOS transistor, the drain terminal of which is connected with the second output terminal of the reference and adaptive mode switching circuit, the source terminal of which is grounded, and the gate terminal of which is connected with the third bias signal input terminal;
A forty-first PMOS transistor having a source terminal connected to the voltage input point Vin, a gate terminal connected to the first bias signal input terminal,
a forty-second PMOS transistor having a source terminal connected to the voltage input point Vin, a gate terminal connected to the first bias signal input terminal,
a forty-third PMOS tube, the source end of which is connected with the drain end of the forty-first PMOS tube, and the gate end of which is connected with the input end (FB) of the reference and self-adaptive mode switching circuit;
a forty-fifth PMOS tube, the source end of which is connected with the drain end of the forty-second PMOS tube, and the gate end of which is connected with the input end (FB) of the reference and self-adaptive mode switching circuit;
a forty-sixth PMOS tube, the source end of which is connected with the voltage input point Vin, the gate end of which is connected with the first bias signal input end, and the drain end of which is connected with the third output end of the reference and adaptive mode switching circuit;
a forty-seventh PMOS tube, the gate end of which is connected with the second bias signal input end, and the source end of which is connected with the voltage input point Vin;
a forty-eighth PMOS tube, the grid end of which is connected with the second bias signal input end, the source end of which is connected with the voltage input point Vin, and the drain end of which is connected with the third output end of the reference and self-adaptive mode switching circuit;
a collector of the first triode (491) is connected with a drain end of a forty-second PMOS tube, an emitter of the first triode is connected with an emitter of the second triode (492) through a resistor, and a base of the first triode is connected with an input end (FB) of the reference and self-adaptive mode switching circuit;
And a second triode (492), wherein the collector of the second triode is connected with the drain end of the forty-first PMOS tube, the emitter of the second triode is grounded through a resistor, and the base of the second triode is connected with the input end (FB) of the reference and self-adaptive mode switching circuit.
The digital logic circuit includes:
the first selector branch circuit is composed of a first selector, an eleventh inverter, a first NAND gate and a twelfth inverter which are sequentially connected in series according to the signal transmission direction, two input ends of the first selector are respectively connected with the control end and the second input end of the digital logic circuit, the other input end of the first NAND gate is connected with the first input end of the digital logic circuit, and the output end of the twelfth inverter is connected with the first output end of the digital logic circuit;
the second selector branch circuit is composed of a second selector, a twenty-first inverter and a twenty-second inverter which are sequentially connected in series according to the signal transmission direction, two input ends of the second selector are respectively connected with the control end and a second input end of the digital logic circuit, and the output end of the twenty-second inverter is connected with a fourth output end of the digital logic circuit;
the third selector branch circuit is composed of a third selector, a thirty-first inverter, a second NAND gate and a thirty-second inverter which are sequentially connected in series according to the signal transmission direction, two input ends of the third selector are respectively connected with the control end and the second input end of the digital logic circuit, the other input end of the second NAND gate is connected with the first input end of the digital logic circuit, and the output end of the thirty-second inverter is connected with the second output end of the digital logic circuit;
And the fourth selector branch circuit is composed of a fourth selector and a forty-first phase inverter which are sequentially connected in series according to the signal transmission direction, two input ends of the fourth selector are respectively connected with the control end and the second input end of the digital logic circuit, and the output end of the forty-first phase inverter is connected with the third output end of the digital logic circuit.
Referring to fig. 4, the digital logic circuit includes:
the first selector branch circuit is composed of a first selector, an eleventh inverter, a first NAND gate and a twelfth inverter which are sequentially connected in series according to the signal transmission direction, two input ends of the first selector are respectively connected with the control end X1023_ A46 and the second input end S _ input2 of the digital logic circuit, the other input end of the first NAND gate is connected with the first input end S _ input1 of the digital logic circuit, and the output end of the twelfth inverter is connected with the first output end S _ output1 of the digital logic circuit;
the second selector branch circuit is composed of a second selector, a twenty-first inverter and a twenty-second inverter which are sequentially connected in series according to the signal transmission direction, two input ends of the second selector are respectively connected with the control end and a second input end of the digital logic circuit, and the output end of the twenty-second inverter is connected with a fourth output end S _ output4 of the digital logic circuit;
The third selector branch circuit is composed of a third selector, a thirty-first inverter, a second NAND gate and a thirty-second inverter which are sequentially connected in series according to the signal transmission direction, two input ends of the third selector are respectively connected with the control end and the second input end of the digital logic circuit, the other input end of the second NAND gate is connected with the first input end of the digital logic circuit, and the output end of the thirty-second inverter is connected with the second output end S _ output2 of the digital logic circuit;
and the fourth selector branch is composed of a fourth selector and a forty-first inverter which are sequentially connected in series according to the signal transmission direction, two input ends of the fourth selector are respectively connected with the control end and the second input end of the digital logic circuit, and the output end of the forty-first inverter is connected with the third output end S _ output3 of the digital logic circuit.
The OUTPUT voltage OUTPUT of the charge pump is enabled to be a fixed value of 3.3V by utilizing a reference voltage of 1.2V and serially connecting feedback resistors RF1 and RF2, namely
Figure GDA0003676015270000081
Realize the functions of boosting and reducing voltage. Fig. 5 shows that the period is 1us in case of heavy load and 233us in case of light load. By increasing the period, the efficiency is improved.
The circuit adopts a voltage control mode and comprises series feedback resistors RF1 and RF2, a reference and adaptive mode switching circuit and 2 comparator circuits The circuit comprises a circuit, an oscillator, a digital logic circuit, 4 buffer circuits and 4 power switch tubes. The main function of the reference and self-adaptive mode switching circuit is to generate a reference voltage 1.2V, namely a line name FB, and meanwhile, the FB is also a feedback voltage; and secondly, when the load current is detected to be less than 20mA, the whole control loop enters an energy-saving mode, and when the load current is detected to be more than 20mA, the chip generates a fixed conversion frequency of 1 MHz. The main function of the series feedback resistors RF1 and RF2 is to make the output voltage Vout a fixed value,
Figure GDA0003676015270000082
the main function of the comparator 1 is to detect input signals R55_ MINUS and R55_ PLUS, when R55_ MINUS is greater than R55_ PLUS, the comparator 1 outputs a low level "0", and the signal enables an oscillator generating a frequency of 1MHz to control the switching frequency of the power tube through an OSC _ EN port, so that the switching frequency of the chip is a fixed value of 1 MHz. When R55_ MINUS is less than R55_ PLUS, comparator 1 outputs a high level "1" which disables the 1MHz frequency generated by the oscillator from being passed to the power transistor through the OSC _ EN port. At this time, the chip switching frequency is determined by the load current, and the power saving mode is entered.
The main function of the comparator 2 is to detect the buck mode, when the Vin voltage of the POWER supply is greater than the OUTPUT voltage, the comparator 2 OUTPUTs a low level "0", which controls the POWER transistor through the S _ input1 of the digital logic circuit, so that the POWER2 is always connected to the POWER supply, C XP Switch between POWER3 and POWER 4.
The digital logic circuit is used for controlling the 4 buffers and finally controlling the on and off states of the 4 POWER POWER tubes.
Fig. 4 is a digital logic circuit.
In the boost heavy load case, the selection circuit MUX2 controls 4 power transistors with the X1023_ a46 signal.
When X1023_ a46 is "1", S _ output1 is "0", POWER1 is off; s _ output4 is "1", POWER4 is off; POWER2 and POWER3 are turned on. This process pertains to charge transfer at boost. Conversely, when X1023_ a46 is "0", this process pertains to charge up the charge at boosted voltage.
In the boost light load condition, the selection circuit MUX2 uses S _ input2 as a control signal.
In the buck mode, S _ input1 is "0", S _ output1 is "0", POWER1 is permanently turned off; POWER2 is turned on permanently. Power3 and Power4 are controlled by S _ input2 to turn on and off.
The 4 buffers are mainly used for providing high and large current for the grid electrode of the power tube, and the driving capability is improved.
The main role of the off-chip device capacitance Cx is to act as a carrier for storing and transferring charge.
FIG. 5 is a reference and adaptive mode switching circuit of the present invention.
The transistors NPN492, NPN491, resistor R42, and resistor R41 generate the reference voltage 1.2V, and the voltage value is also the feedback voltage FB. The NMOS31 and POWER transistor POWER1 in fig. 3 and NMOS46 and NMOS45 in fig. 4 constitute an adaptive mode switching circuit.
When the adaptive mode switching circuit is designed to detect that the load current is less than or equal to 20mA, the chip enters an energy-saving mode.
The POWER transistor POWER1 is in mirror image relation with the NMOS31, both devices are in saturation region, and the width-length ratio of the devices is in direct proportion to the current value. Since the width w of the POWER tube POWER1 is 22000um, the width w of the NMOS31 is 7um, and the length L of both is 1um, the relational expression between the POWER tube POWER1 and the NMOS31 is as follows.
Figure GDA0003676015270000091
Figure GDA0003676015270000092
I NMOS31 ＝6uA
I NMOS31 That is the current value of nmos45 in fig. 4. Under light load, when the load is less than 20mA, the current value of the nmos45 is less than 6uA, the voltage value of the line name R55_ PLUS is greater than that of the line name R55_ MINUS, and the voltage values of the two lines areAs an input voltage of the comparator 1, the comparator 1 outputs a high level "1", which disables the 1MHz frequency generated by the oscillator from being transferred to the 4 buffer circuits. In this case, the whole loop works on the principle that a small signal on the feedback voltage FB generates a gain g by using nmos43 and pmos46 common sources m43 ·r pmos46 The signal is amplified, and then the signal passes through a source follower generated by nmos46, and the buffer1 circuit is controlled by the line name N583_ D, so that the on-resistance of the POWER tube POWER1 is adjusted, and finally the charge quantity of the external capacitor Cx is adjusted.
Under the heavy load condition, when the load is greater than 20mA, the current value of the nmos45 is greater than 6uA, the comparator 1 outputs low level '0', the 1MHz frequency generated by the oscillator is transmitted to 4 buffer circuits, and the fixed working frequency of the chip is 1 MHz.
Fig. 6 is a periodic simulation waveform of the input current and the output voltage under light load condition (fig. 6, 8, 12 are screenshots of simulation software interfaces, only the waveform state needs to be concerned, and the key value information in the screenshots will be described in detail below).
The chip adopts a voltage control mode and a self-adaptive mode switching circuit, so that the conversion frequency is reduced, the conversion period is increased, and the power consumption is reduced. Under the condition of light load, the conversion period of the chip reaches 233 us.
Fig. 7 is a graph of efficiency values at different load conditions.
Fig. 8 is a simulated waveform of output ripple under heavy load conditions.
The invention adopts a voltage control mode and a formula of output ripples thereof
Figure GDA0003676015270000101
The load current is 75mA, f OSC ＝1MHz，C out The output ripple voltage was calculated by the formula theory to be 37.5mV at 1 uf.
Simulation results the waveforms are shown with the output voltage ripple on the first graph and the load current 75mA on the second graph.
The waveform of the simulation result is that the output ripple voltage is 38.5 mV. The theoretical value is very close to the simulation result.
Fig. 9 is a charging process in the boost mode.
In the boost mode, the POWER1 and POWER4 are mainly conducted in the charging process, so that a path from the POWER Vin to the ground is formed, and the capacitor Cx is charged.
Fig. 10 is a charge transfer process in the boost mode.
The charge transfer process in boost mode is mainly POWCXPSURER 2 and POWER3 turning on, forming a path from the POWER source Vin to OUTPUT.
Fig. 11 is a schematic diagram of operation in the buck mode.
When the POWER voltage Vin is greater than the OUTPUT voltage, the comparator 2 controls the digital logic circuit according to the comparison result, so that the POWER2 is always connected with the POWER Vin, the port Cxp is switched between the POWER3 and the POWER4, the capacitor Cx is charged, and the current is supplied to the load.
Fig. 12 is a simulation waveform in the step-down mode.
The first waveform is the power voltage Vin equal to 5V, the second waveform is the OUTPUT voltage waveform OUTPUT equal to 3.331V, and the third waveform is the load current 75mA (Rload equal to 44.41 Ω). The whole circuit realizes the voltage reduction function.
The whole circuit realizes the voltage reduction function.

Claims (5)

1. An adaptive mode switching charge pump comprising:
a second POWER tube (POWER2), the source terminal of which is connected with the voltage input point Vin, the gate terminal of which is connected with the output terminal of the second Buffer (Buffer2), and the drain terminal of which is connected with the third external connection point;
the drain terminal of the first POWER tube (POWER1) is connected with the drain terminal of the second POWER tube, the grid terminal is connected with the output terminal of the first Buffer (Buffer1), and the source terminal is grounded;
a thirty-first MOS tube, wherein the grid end of the thirty-first MOS tube is connected with the output end of the first Buffer (Buffer1), the source end of the thirty-first MOS tube is grounded, and the drain end of the thirty-first MOS tube is connected with the first output end of the reference and self-adaptive mode switching circuit;
A second output end of the reference and self-adaptive mode switching circuit is connected with a second input end of a first Buffer (Buffer1), a third output end and a fourth output end are respectively connected with two input ends of a first comparator, an input end (FB) of the reference and self-adaptive mode switching circuit is grounded through a first feedback resistor, and is also connected with a fourth external connection point through a second feedback resistor;
the output end of the first comparator is connected with the input end of the oscillator, and the output end of the oscillator is connected with the control end of the digital logic circuit;
a digital logic circuit, a first input of which is connected with the output end of the second comparator, a second input of which is connected with the output end of the first Buffer (Buffer1), a first output of which is connected with the first input end of the first Buffer (Buffer1), a second output of which is connected with the input end of the second Buffer (Buffer2), a third output of which is connected with the input end of the third Buffer (Buffer3), and a fourth output of which is connected with the input end of the fourth Buffer (Buffer 4);
a second comparator, the negative input end of which is connected with the voltage input point Vin, and the positive input end of which is connected with the first external connection point;
the source end of the third power tube is connected with the first external connection point, the grid end of the third power tube is connected with the output end of the third buffer, and the drain end of the third power tube is connected with the second external connection point and the source end of the fourth power tube;
and the grid end of the fourth power tube is connected with the output end of the fourth buffer, and the drain end of the fourth power tube is connected with the voltage input point Vin.
2. The adaptive mode-switching charge pump of claim 1, wherein the second external connection point and the third external connection point are connected by a capacitor.
3. The adaptive mode-switching charge pump of claim 1, wherein the first external connection point, the fourth external connection point, and the final output point are connected to a final output point, the final output point being connected to ground through a capacitor.
4. The adaptive mode-switching charge pump of claim 1, wherein the reference and adaptive mode switching circuit comprises:
a forty-first NMOS transistor, wherein the drain end and the gate end of the forty-third NMOS transistor are connected with the drain end of the forty-third PMOS transistor, and the source end of the forty-first NMOS transistor is grounded through a resistor;
a gate end of the forty-second NMOS transistor is connected with a drain end of the forty-third PMOS transistor, a source end of the forty-second NMOS transistor is grounded through a resistor, and a drain end of the forty-fifth NMOS transistor is connected with a drain end of the forty-fifth PMOS transistor;
a gate end of the forty-third NMOS transistor is connected with a drain end of the forty-fifth PMOS transistor, a source end of the forty-third NMOS transistor is grounded through a resistor, and a drain end of the forty-sixth NMOS transistor is connected with a drain end of the forty-sixth PMOS transistor;
a forty-fifth NMOS transistor, wherein the drain terminal and the gate terminal of the forty-fifth NMOS transistor are connected with the fourth output terminal of the reference and adaptive mode switching circuit, and the source terminal of the forty-fifth NMOS transistor is connected with the first output terminal of the reference and adaptive mode switching circuit;
a forty-sixth NMOS transistor, the source terminal of which is connected with the second output terminal of the reference and adaptive mode switching circuit, the drain terminal of which is connected with the voltage input point Vin, the gate terminal of which is connected with the third output terminal of the reference and adaptive mode switching circuit, and the gate terminal of which is also connected with the fourth output terminal of the reference and adaptive mode switching circuit through a forty-sixth resistor;
A forty-seventh NMOS transistor, the drain terminal of which is connected with the second output terminal of the reference and adaptive mode switching circuit, the source terminal of which is grounded, and the gate terminal of which is connected with the third bias signal input terminal;
a forty-first PMOS transistor having a source terminal connected to the voltage input point Vin, a gate terminal connected to the first bias signal input terminal,
a forty-second PMOS transistor having a source terminal connected to the voltage input point Vin, a gate terminal connected to the first bias signal input terminal,
a forty-third PMOS tube, the source end of which is connected with the drain end of the forty-first PMOS tube, and the gate end of which is connected with the input end (FB) of the reference and self-adaptive mode switching circuit;
a forty-fifth PMOS tube, the source end of which is connected with the drain end of the forty-second PMOS tube, and the gate end of which is connected with the input end (FB) of the reference and self-adaptive mode switching circuit;
a forty-sixth PMOS tube, the source end of which is connected with the voltage input point Vin, the gate end of which is connected with the first bias signal input end, and the drain end of which is connected with the third output end of the reference and adaptive mode switching circuit;
a forty-seventh PMOS tube, the gate end of which is connected with the second bias signal input end, and the source end of which is connected with the voltage input point Vin;
a forty-eighth PMOS tube, the grid end of which is connected with the second bias signal input end, the source end of which is connected with the voltage input point Vin, and the drain end of which is connected with the third output end of the reference and self-adaptive mode switching circuit;
a collector of the first triode (491) is connected with a drain end of a forty-second PMOS tube, an emitter of the first triode is connected with an emitter of the second triode (492) through a resistor, and a base of the first triode is connected with an input end (FB) of the reference and self-adaptive mode switching circuit;
And a second triode (492), the collector of which is connected with the drain of the forty first PMOS tube, the emitter of which is grounded through a resistor, and the base of which is connected with the input end (FB) of the reference and self-adaptive mode switching circuit.
5. The adaptive mode-switching charge pump of claim 1, wherein the digital logic circuit comprises:
the first selector branch circuit is composed of a first selector, an eleventh inverter, a first NAND gate and a twelfth inverter which are sequentially connected in series according to the signal transmission direction, two input ends of the first selector are respectively connected with the control end and the second input end of the digital logic circuit, the other input end of the first NAND gate is connected with the first input end of the digital logic circuit, and the output end of the twelfth inverter is connected with the first output end of the digital logic circuit;
the second selector branch circuit is composed of a second selector, a twenty-first inverter and a twenty-second inverter which are sequentially connected in series according to the signal transmission direction, two input ends of the second selector are respectively connected with the control end and a second input end of the digital logic circuit, and the output end of the twenty-second inverter is connected with a fourth output end of the digital logic circuit;
the third selector branch circuit is composed of a third selector, a thirty-first inverter, a second NAND gate and a thirty-second inverter which are sequentially connected in series according to the signal transmission direction, two input ends of the third selector are respectively connected with the control end and the second input end of the digital logic circuit, the other input end of the second NAND gate is connected with the first input end of the digital logic circuit, and the output end of the thirty-second inverter is connected with the second output end of the digital logic circuit;
And the fourth selector branch circuit is composed of a fourth selector and a forty-first inverter which are sequentially connected in series according to the signal transmission direction, two input ends of the fourth selector are respectively connected with the control end and the second input end of the digital logic circuit, and the output end of the forty-first inverter is connected with the third output end of the digital logic circuit.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050046489A1 (en) * 2003-08-28 2005-03-03 International Business Machines Corporation Self-adaptive voltage regulator for a phase-locked loop
US20060197583A1 (en) * 2005-03-03 2006-09-07 Chih-Jen Yen Method of enhancing efficiency of charge pump circuit and charge pump selector circuit
CN102684481A (en) * 2012-05-24 2012-09-19 苏州脉科库博环保科技有限公司 Wide-input range and low-ripple step-down circuit for charge pump
CN105915046A (en) * 2016-04-27 2016-08-31 北京宏力尼科科技有限公司 Charge pump control circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050046489A1 (en) * 2003-08-28 2005-03-03 International Business Machines Corporation Self-adaptive voltage regulator for a phase-locked loop
US20060197583A1 (en) * 2005-03-03 2006-09-07 Chih-Jen Yen Method of enhancing efficiency of charge pump circuit and charge pump selector circuit
CN102684481A (en) * 2012-05-24 2012-09-19 苏州脉科库博环保科技有限公司 Wide-input range and low-ripple step-down circuit for charge pump
CN105915046A (en) * 2016-04-27 2016-08-31 北京宏力尼科科技有限公司 Charge pump control circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Current mode charge pump: topology, modeling and control;G. Thiele et al.;《2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551)》;20040625;全文 *
一种用于LED驱动的高效电荷泵电路的设计;尚林林等;《固体电子学研究与进展》;20100331;第30卷(第1期);全文 *

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