CN113671880A - Financial data acceleration system and method - Google Patents
Financial data acceleration system and method Download PDFInfo
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- CN113671880A CN113671880A CN202110975032.3A CN202110975032A CN113671880A CN 113671880 A CN113671880 A CN 113671880A CN 202110975032 A CN202110975032 A CN 202110975032A CN 113671880 A CN113671880 A CN 113671880A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
Abstract
A financial data acceleration system, carry on the parameter configuration to the financial acceleration processor through the PC end of configuration of the acceleration system, receive and discern the market data from exchange through the network port receiving module of the trillion, the network port receiving module of the trillion transmits the data received to the financial data acceleration processor, the financial data acceleration processor analyzes and processes the data at a high speed, then analyze and process the data after processing at a high speed and send to the customer PC end through the network port sending module of the trillion, and then finish the data acceleration function; the financial data acceleration system also comprises a domestic FPGA monitoring chip; the domestic FPGA monitoring chip monitors the working state of the financial data acceleration processor in real time and sends the current working state to the acceleration system configuration PC terminal; and the acceleration system configuration PC end monitors that the financial data acceleration processor is clamped or controlled, and informs the domestic FPGA monitoring chip to reset the financial data acceleration processor. There are also methods.
Description
Technical Field
The invention relates to the technical field of a programmable logic device FPGA, in particular to a financial data acceleration system and a financial data acceleration method.
Background
In the face of the stock market with opportunities and risks coexisting, stock quotations become a necessary course for each stockman, quotation information becomes a profit stone, and only by rapidly and comprehensively grasping the quotation and judging the trend, the proper time for buying and selling the stocks can be found out, and larger profits are earned.
The fusion and expansion of the economic market put higher demands on stock market spreading, the stock market is known in the first step, and stock trading in the first step becomes a success point of the stock market, so that the economic benefit can be increased, and the stock disaster loss can be reduced. At present, the financial industry uses and realizes the innovation with higher speed, adopts the acceleration integrated circuit board as the acceleration processor.
Currently, the mainstream acceleration board card adopts a foreign CPU or an FPGA (Field Programmable Gate Array) as an acceleration processor. A system block diagram is shown in fig. 1.
In the acceleration board system shown in fig. 1, the acceleration system configures the PC end to perform parameter configuration on the financial acceleration processor, including login, setting of market data source, system start and stop, and the like. After the system configuration is completed and the data acceleration is started, the acceleration system receives and identifies market data from a trading exchange through the gigabit network port receiving module, transmits the data received by a TCP/IP protocol to the financial data acceleration processor through the gigabit network port receiving module, further analyzes and processes the data at a high speed, and then transmits the data analyzed and processed at the high speed to a client PC (personal computer) end through the gigabit network port transmitting module, thereby completing the data acceleration function.
Based on the system, the system can basically meet the requirement that the client analyzes the data of the exchange in the shortest time, and provides the current market data for the client to make corresponding decision of buying or selling.
In general, after the customer configures the financial data acceleration system, the customer does not monitor the financial data acceleration system, and the system works automatically in the following. However, for a financial system with high security requirement, once the acceleration processor is bound abroad, the data which is not available to the client or the false data is available, and the client PC cannot detect that the financial acceleration system is controlled externally, which will bring huge financial loss to the client and even bring unpredictable effect to the whole financial industry.
Disclosure of Invention
In order to overcome the defects of the prior art, the technical problem to be solved by the invention is to provide a financial data acceleration system which can monitor the safe operation of a financial data acceleration processor in real time and avoid the problem that the financial data acceleration processor is controlled externally to bring huge financial loss to a client or bring unpredictable results to the whole financial industry.
The financial data acceleration system carries out parameter configuration on a financial acceleration processor through an acceleration system configuration PC end, market data from a trading exchange are received and identified through a tera network port receiving module, the received data are transmitted to the financial data acceleration processor through the tera network port receiving module, the financial data acceleration processor carries out high-speed analysis and processing on the data, and then the data after high-speed analysis and processing are sent to a client PC end through a tera network port sending module, so that a data acceleration function is completed;
the financial data acceleration system also comprises a domestic FPGA monitoring chip;
the domestic FPGA monitoring chip monitors the working state of the financial data acceleration processor in real time and sends the current working state to the acceleration system configuration PC terminal;
and the acceleration system configuration PC end monitors that the financial data acceleration processor is clamped or controlled, and informs the domestic FPGA monitoring chip to reset the financial data acceleration processor.
The working state of the financial data acceleration processor is monitored in real time through the domestic FPGA monitoring chip, the current working state is sent to the acceleration system configuration PC end, the acceleration system configuration PC end monitors that the financial data acceleration processor is clamped or controlled, and the domestic FPGA monitoring chip is informed to reset the financial data acceleration processor, so that the safe operation of the financial data acceleration processor can be monitored in real time, and huge financial loss caused by external control to a client or unpredictable results caused by the whole financial industry are avoided.
Also provided is a financial data acceleration method, comprising the steps of:
(1) configuring parameters of the financial acceleration processor by a PC (personal computer) end through an acceleration system;
(2) after configuration is completed and data acceleration is started, market data from a trading exchange is received and identified through the tera network port receiving module, and the received data are transmitted to the financial data acceleration processor through the tera network port receiving module;
(3) the financial data acceleration processor analyzes and processes the data at a high speed, and then sends the data analyzed and processed at the high speed to a client PC (personal computer) end through a gigabit network port sending module;
the following steps are added between the steps (2) and (3):
(I) the domestic FPGA monitoring chip monitors the working state of the financial data acceleration processor in real time and sends the current working state to the acceleration system configuration PC terminal;
and (II) the acceleration system configures the PC terminal to monitor that the financial data acceleration processor is clamped or controlled, and informs the domestic FPGA monitoring chip to reset the financial data acceleration processor.
Drawings
FIG. 1 shows a schematic block diagram of a prior art financial data acceleration system.
FIG. 2 illustrates a functional block diagram of a financial data acceleration system according to the present invention.
Detailed Description
As shown in fig. 2, in the financial data acceleration system, a PC terminal is configured through an acceleration system to perform parameter configuration on a financial acceleration processor, market data from a exchange is received and identified through a gigabit internet access receiving module, the received data is transmitted to the financial data acceleration processor through the gigabit internet access receiving module, the financial data acceleration processor analyzes and processes the data at a high speed, and then the data analyzed and processed at the high speed is transmitted to the PC terminal of a client through a gigabit internet access transmitting module, thereby completing a data acceleration function;
the financial data acceleration system also comprises a domestic FPGA monitoring chip;
the domestic FPGA monitoring chip monitors the working state of the financial data acceleration processor in real time and sends the current working state to the acceleration system configuration PC terminal;
and the acceleration system configuration PC end monitors that the financial data acceleration processor is clamped or controlled, and informs the domestic FPGA monitoring chip to reset the financial data acceleration processor.
The working state of the financial data acceleration processor is monitored in real time through the domestic FPGA monitoring chip, the current working state is sent to the acceleration system configuration PC end, the acceleration system configuration PC end monitors that the financial data acceleration processor is clamped or controlled, and the domestic FPGA monitoring chip is informed to reset the financial data acceleration processor, so that the safe operation of the financial data acceleration processor can be monitored in real time, and huge financial loss caused by external control to a client or unpredictable results caused by the whole financial industry are avoided.
Preferably, when the domestic FPGA monitoring chip detects that the financial data acceleration processor is not reset, the financial data acceleration processor is forcibly in a power-down state, and meanwhile, an abnormal state is fed back to the acceleration system configuration PC terminal to inform a client that data in the time period is unavailable. This ensures that the financial data acceleration processor is taken out of service when an anomaly occurs.
Preferably, the domestic FPGA monitoring chip is an FPGA EQ6HL130 series chip, and a domestic company monitoring program runs inside the chip to realize a monitoring function of the financial acceleration system. The parameters are as follows:
based on a standard 40nm CMOS process, the effective gate capacity reaches 1360 ten thousand gates;
the core voltage is 1.1V, the I/O standard voltage is 3.3V, and various I/O standards are supported;
the embedded memory unit is provided with 1200 embedded memory units, and 5.4Mbit can be realized at most;
192 high-speed 18bit by 18bit multipliers;
with 8 programmable PLLs, the highest clock management frequency can reach 500 MHz;
a maximum of 16 global clock signals can be provided;
338 programmable user I/O, 169 pairs of LVDS differential ports may be provided;
supporting on-chip digital control terminal resistance DCT;
the active serial, passive serial, active parallel, passive parallel, JTAG and SPI configuration modes are supported;
the ESD withstand voltage is more than 2000V;
packaging form: FG484/CSG484/FG676 (plastic package), minimum size 19 mm. Also provided is a financial data acceleration method, comprising the steps of:
(1) configuring parameters of the financial acceleration processor by a PC (personal computer) end through an acceleration system;
(2) after configuration is completed and data acceleration is started, market data from a trading exchange is received and identified through the tera network port receiving module, and the received data are transmitted to the financial data acceleration processor through the tera network port receiving module;
(3) the financial data acceleration processor analyzes and processes the data at a high speed, and then sends the data analyzed and processed at the high speed to a client PC (personal computer) end through a gigabit network port sending module;
the following steps are added between the steps (2) and (3):
(I) the domestic FPGA monitoring chip monitors the working state of the financial data acceleration processor in real time and sends the current working state to the acceleration system configuration PC terminal;
and (II) the acceleration system configures the PC terminal to monitor that the financial data acceleration processor is clamped or controlled, and informs the domestic FPGA monitoring chip to reset the financial data acceleration processor.
Preferably, in the step (II), when the domestic FPGA monitoring chip detects that the financial data acceleration processor is not reset, the financial data acceleration processor is forced to be in a power-down state, and an abnormal state is fed back to the acceleration system configuration PC terminal to notify the client that the data in the time period is unavailable.
Preferably, in the step (2), the tera-network-port receiving module receives market data from the exchange through a TCP/IP protocol.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and all simple modifications, equivalent variations and modifications made to the above embodiment according to the technical spirit of the present invention still belong to the protection scope of the technical solution of the present invention.
Claims (6)
1. A financial data acceleration system, carry on the parameter configuration to the financial acceleration processor through the PC end of configuration of the acceleration system, receive and discern the market data from exchange through the network port receiving module of the trillion, the network port receiving module of the trillion transmits the data received to the financial data acceleration processor, the financial data acceleration processor analyzes and processes the data at a high speed, then analyze and process the data after processing at a high speed and send to the customer PC end through the network port sending module of the trillion, and then finish the data acceleration function; the method is characterized in that:
the financial data acceleration system also comprises a domestic FPGA monitoring chip;
the domestic FPGA monitoring chip monitors the working state of the financial data acceleration processor in real time and sends the current working state to the acceleration system configuration PC terminal;
and the acceleration system configuration PC end monitors that the financial data acceleration processor is clamped or controlled, and informs the domestic FPGA monitoring chip to reset the financial data acceleration processor.
2. The financial data acceleration system of claim 1, wherein: when the domestic FPGA monitoring chip detects that the financial data acceleration processor is not reset, the financial data acceleration processor is forcibly in a power-down state, and meanwhile, an abnormal state is fed back to the acceleration system configuration PC end to inform a client that data in the time period is unavailable.
3. The financial data acceleration system of claim 2, wherein: the domestic FPGA monitoring chip is an FPGA EQ6HL130 series chip.
4. A financial data acceleration method, comprising the steps of:
(1) configuring parameters of the financial acceleration processor by a PC (personal computer) end through an acceleration system;
(2) after configuration is completed and data acceleration is started, market data from a trading exchange is received and identified through the tera network port receiving module, and the received data are transmitted to the financial data acceleration processor through the tera network port receiving module;
(3) the financial data acceleration processor analyzes and processes the data at a high speed, and then sends the data analyzed and processed at the high speed to a client PC (personal computer) end through a gigabit network port sending module;
the method is characterized in that: the following steps are added between the steps (2) and (3):
(I) the domestic FPGA monitoring chip monitors the working state of the financial data acceleration processor in real time and sends the current working state to the acceleration system configuration PC terminal;
and (II) the acceleration system configures the PC terminal to monitor that the financial data acceleration processor is clamped or controlled, and informs the domestic FPGA monitoring chip to reset the financial data acceleration processor.
5. The financial data acceleration method according to claim 4, characterized in that: in the step (II), when the domestic FPGA monitoring chip detects that the financial data acceleration processor is not reset, the financial data acceleration processor is forcibly in a power-down state, and meanwhile, an abnormal state is fed back to the acceleration system configuration PC end to inform a client that data in the time period is unavailable.
6. The financial data acceleration method according to claim 5, characterized in that: in the step (2), the tera network port receiving module receives market data from the exchange through a TCP/IP protocol.
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| CN202110975032.3A CN113671880A (en) | 2021-08-24 | 2021-08-24 | Financial data acceleration system and method |
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| CN202110975032.3A CN113671880A (en) | 2021-08-24 | 2021-08-24 | Financial data acceleration system and method |
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| US20130290163A1 (en) * | 2006-06-19 | 2013-10-31 | Ip Reservoir, Llc | High Speed Processing of Financial Information Using FPGA Devices |
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| CN109032987A (en) * | 2018-07-05 | 2018-12-18 | 山东超越数控电子股份有限公司 | A kind of computer system and method accelerating domestic processor based on FPGA |
| CN110517136A (en) * | 2019-07-30 | 2019-11-29 | 上海兮通信息科技有限公司 | A kind of quotation accelerated processing method and system |
| CN110610099A (en) * | 2018-06-15 | 2019-12-24 | 上海仪电（集团）有限公司中央研究院 | Financial risk intelligent early warning and wind control system based on FPGA hardware acceleration |
| CN110611624A (en) * | 2018-06-15 | 2019-12-24 | 上海仪电（集团）有限公司中央研究院 | Massive market quotation data acceleration system and acceleration method based on FPGA |
| CN112541822A (en) * | 2020-12-04 | 2021-03-23 | 深圳市瑞尚信息科技有限公司 | Financial wind control system based on FPGA accelerator card |
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2021
- 2021-08-24 CN CN202110975032.3A patent/CN113671880A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006163897A (en) * | 2004-12-08 | 2006-06-22 | Nec Corp | Financial transaction control system, its method, management apparatus, and program |
| US20130290163A1 (en) * | 2006-06-19 | 2013-10-31 | Ip Reservoir, Llc | High Speed Processing of Financial Information Using FPGA Devices |
| WO2015005877A1 (en) * | 2013-07-12 | 2015-01-15 | Duduoglu Tuncer | Device for the prevention of capturing customer cards and card information on atms and similar financial machines |
| CN110610099A (en) * | 2018-06-15 | 2019-12-24 | 上海仪电（集团）有限公司中央研究院 | Financial risk intelligent early warning and wind control system based on FPGA hardware acceleration |
| CN110611624A (en) * | 2018-06-15 | 2019-12-24 | 上海仪电（集团）有限公司中央研究院 | Massive market quotation data acceleration system and acceleration method based on FPGA |
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| CN112541822A (en) * | 2020-12-04 | 2021-03-23 | 深圳市瑞尚信息科技有限公司 | Financial wind control system based on FPGA accelerator card |
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Application publication date: 20211119 |
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