CN113661578A - 用于与焊盘的欧姆接触的氧化铟锡(ito)层的片上集成 - Google Patents

用于与焊盘的欧姆接触的氧化铟锡(ito)层的片上集成 Download PDF

Info

Publication number
CN113661578A
CN113661578A CN202080027234.9A CN202080027234A CN113661578A CN 113661578 A CN113661578 A CN 113661578A CN 202080027234 A CN202080027234 A CN 202080027234A CN 113661578 A CN113661578 A CN 113661578A
Authority
CN
China
Prior art keywords
layer
stack
ito
pad
ito layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202080027234.9A
Other languages
English (en)
Inventor
G.埃尔姆斯泰纳
汉尼斯.布兰德纳
帕特里克.波尔多
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram AG
Original Assignee
Ams AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ams AG filed Critical Ams AG
Publication of CN113661578A publication Critical patent/CN113661578A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
    • H01L31/022475—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers composed of indium tin oxide [ITO]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02162—Coatings for devices characterised by at least one potential jump barrier or surface barrier for filtering or shielding light, e.g. multicolour filters for photodetectors
    • H01L31/02165—Coatings for devices characterised by at least one potential jump barrier or surface barrier for filtering or shielding light, e.g. multicolour filters for photodetectors using interference filters, e.g. multilayer dielectric filters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0382—Applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05157—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/0518—Molybdenum [Mo] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05561—On the entire surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/053—Oxides composed of metals from groups of the periodic table
    • H01L2924/0534—4th Group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/053—Oxides composed of metals from groups of the periodic table
    • H01L2924/0549—Oxides composed of metals from groups of the periodic table being a combination of two or more materials provided in the groups H01L2924/0531 - H01L2924/0546

Abstract

一种设备包括光学装置(22)和导电焊盘(32)。导电材料的多层堆叠(42,44,46)设置在该焊盘(32)上。ITO层(48)至少部分设置在该光学装置(22)上并且与该多层堆叠(42,44,46)欧姆接触。

Description

用于与焊盘的欧姆接触的氧化铟锡(ITO)层的片上集成
技术领域
本公开涉及用于与互补金属氧化物半导体(CMOS)焊盘(bond pad)的欧姆接触的氧化铟锡(ITO)层。
背景技术
氧化铟锡(ITO)在可见光谱中可为透明的且也可为导电的。这些性质使ITO适用于许多光电应用。也已研究使用ITO薄膜层来连接至诸如铝的金属电极(例如，CMOS焊盘、金属总线或数据线)。不幸地，ITO与铝之间的接触形成会因界面的氧化而受损。例如，当界面曝露于空气时可发生氧化。界面氧化也可由(例如)在ITO的反应溅镀期间馈入至溅镀过程中的氧气、ITO溅镀靶本身的氧自由基或氧释放所致。即使可藉由修改ITO溅镀过程来避免形成薄氧化物层，接触电阻仍趋向于保持不可接受地高且随时间推移随热应力而增加。这种现象是基于氧原子自ITO薄膜扩散至铝中，因此产生绝缘氧化物层，其导致高接触电阻率。
发明内容
本公开描述用于与CMOS或其他导电焊盘的欧姆接触的ITO薄膜的片上集成。
例如，在一个方面中，本公开描述一种包括光学装置的设备。该设备进一步包括：导电焊盘；以及导电材料的多层堆叠，其在该焊盘上，其中该堆叠包括第一ITO层作为顶层。第二ITO层至少部分设置在该光学装置上并且在该第一ITO层上。
一些实施方式包括以下特征的一个或多个。例如，导电材料的该多层堆叠可包括与该焊盘直接接触的导电层以及与该导电层直接接触的至少一个扩散阻挡层或黏着层的子堆叠，其中该第一ITO层与至少一个扩散阻挡层或黏着层的该子堆叠直接接触。导电材料的该多层堆叠可形成与该焊盘的欧姆接触。作为具体示例，该多层堆叠可包括在与该焊盘直接接触的铝层上的钛层，其中该第一ITO层在该钛层上。在一些实施方式中可使用其他材料。
在一些情况下，该第一ITO层具有与该第二ITO层的组成不同的组成。在一些情况下，该第二ITO层覆盖该光学装置。例如，该光学装置可以是设置在集成半导体电路中的光检测元件上方的光学干涉滤波器。
在一些实施方式中，该光学装置是由该第二ITO层覆盖的光电检测器(例如有机红外光电检测器)。在一些情况下，该设备进一步包括：第二导电焊盘；不同导电材料的第二多层堆叠，其在该第二导电焊盘上，该第二堆叠包括顶层，该顶层包括第一ITO层；以及电极层，其设置在该光学装置的与第二ITO层相对的一侧上并且连接至该第二堆叠的该第一ITO层。在一些情况下，设置在该光学装置的与该第二ITO层相对的一侧上的该电极层由第三ITO层组成。
前述特征可被集成(例如)作为CMOS集成电路的一部分。
本公开还描述用于制造包括ITO薄膜的装置的方法，该ITO薄膜用于与CMOS或其他导电焊盘的欧姆接触。因此，在一个方面中，一种方法包括提供包括导电焊盘的基板，其中光学装置设置在该基板上。该方法包括：在该焊盘上提供导电材料的多层堆叠，该堆叠包括第一ITO层作为顶层；以及提供至少部分在该光学装置和该第一ITO层上的第二ITO层。
本公开进一步描述一种方法，其包括：提供包括第一导电焊盘和第二导电焊盘的基板；在该第一焊盘上提供导电材料的第一多层堆叠，并且在该第二焊盘上提供导电材料的第二多层堆叠，该堆叠的每一个包括相应的第一ITO层作为顶层；提供在该基板上并且连接至该第一多层堆叠的该第一ITO层的第二ITO层：在该第二ITO层上提供光学装置；以及提供至少部分在该光学装置上并且连接至该第二多层堆叠的该第一ITO层的第三ITO层。
该多层堆叠的每一个可包括在该相应的焊盘上的导电层、在该导电层上的至少一个黏着层或阻挡层的子堆叠以及在该子堆叠上的该第一ITO层。
在一些情况下，可省略该第一ITO层。例如，该焊盘上的导电材料的该多层堆叠可包括与该焊盘直接接触的至少一个扩散阻挡层或黏着层的子堆叠以及与该子堆叠直接接触的导电层。至少部分设置在该光学装置上的该ITO层与该多层堆叠电接触。在一些情况下，该多层堆叠的该层沿其中设置该导电焊盘的基板的表面延伸，并且该ITO层的一部分在该多层堆叠的一部分之下。
本公开可帮助克服金属(诸如铝)与ITO之间的氧化物界面层的问题，其趋向于对接触电阻产生有害影响。制造方法可基于用于层沉积和结构化的标准CMOS技术。因此，在一些情况下，可将(多个)ITO层作为附加件(add-on)集成至CMOS装置中，而无需提供该ITO电连接作为单独的子装备的一部分。具体地，可完成薄ITO层与CMOS焊盘的可靠接触，藉此允许将ITO的电光功能集成至CMOS晶圆上。该技术可帮助确保与CMOS焊盘的可靠接触并且可优化该ITO层的光学性能和/或为光学装置提供静电或RF屏蔽。
根据以下具体实施方式、附图以及权利要求书，其他方面、特征和优点将是显而易见的。
附图说明
图1至图3绘示用于与焊盘的欧姆接触的ITO薄膜的片上集成的第一示例过程中的各个步骤。
图4绘示用于与焊盘的欧姆接触的ITO薄膜的片上集成的另一示例。
图5绘示具有与焊盘的欧姆接触的ITO薄膜的片上集成的进一步示例。
具体实施方式
本公开描述用于与CMOS或其他导电焊盘的欧姆接触的ITO薄膜的片上集成。如下文更详细描述，本技术使用ITO至ITO接触以避免否则由于形成氧化物中间层而可发生的问题。
结合图1至图3描述示例，图1至图3绘示基板20，诸如CMOS半导体晶圆，其在n阱光电二极管24的顶部上具有干涉滤波器22。干涉滤波器是反射一个或多个光谱带或线并透射其他，使得其传递至可检测到其的光电二极管24的光学滤波器。图1至图3也显示后端堆叠，其包括多层金属结构26以及对应的导电通孔层。多层金属结构可由(例如)铝(Al)或一些其他导电金属组成。在所绘示的示例中，晶圆20包括其中设置有n阱光电二极管24的p型基板28。介电层(例如氧化物)30设置在基板28上并且围绕多层金属堆叠26。后端堆叠的一部分形成焊盘32。在一些情况下，可代替半导体晶圆来使用其他类型的基板(例如玻璃)。
取决于滤波器22的光谱特性，该配置可用于各种光学感测目的。对于一些应用，在干涉滤波器22上方提供导电屏蔽层是有益的。例如，可藉由提供电耦合至焊盘32的透明导电材料来形成干涉滤波器22上方的导电屏蔽层。ITO可为此目的提供合适材料，这是因为其在可见光谱中可为透明的并且可为导电的。在一些应用中，ITO层的厚度优选地在30nm至300nm的范围中以实现所期望的光学及电特性。焊盘32可用于向ITO层施加经精确限定的电压。然而，由于至少两个原因，将ITO层直接沉积至焊盘32上以及执行随后的剥离过程以图案化ITO可能是困难的。首先，如上文所提及，由于这些材料的化学性质，简单地藉由沉积ITO至铝上无法实现可靠的低欧姆接触，从而导致形成薄氧化物层。其次，如图1中所显示，对于典型CMOS制造过程，自钝化表面34向下至焊盘32将存在约2μm的步阶“h”。因此，步阶高度“h”超过ITO层厚度达约一个或两个数量级。因此，鉴于步阶覆盖问题，若非实际上不可能，则形成直接至焊盘32的可靠ITO接触是非常具挑战性的。
为解决前述问题，本公开描述一种方法，包括形成两个不同ITO层，该两个不同ITO层将焊盘电耦合至干涉滤波器以便形成用于滤波器的电极的至少一部分。ITO层中的第一ITO层在焊盘上形成分层堆叠的顶层。第二ITO层在干涉滤波器上方电延伸并接触第一ITO层。结合图2和图3描述根据一些实施方式的方法的细节。
如在图2的示例中所显示，导电材料的分层堆叠40以循序方式沉积在焊盘32上，使得材料不曝露于空气。堆叠40中的每一层应与其沉积在其上的下层形成良好欧姆接触。在所绘示的示例中，第一层42由铝组成并且具有在0.5μm至3μm的范围中的厚度。该层厚度帮助确保向下至焊盘32的步阶覆盖足以提供良好欧姆接触。尽管铝因其与现有CMOS技术兼容而是优选材料，但在一些实施方式中，其他导电材料(例如，金、银、铬和/或铜)可用于第一层42。
随后，在不将第一层42曝露于空气的情况下，将至少一个扩散阻挡层或黏着层44的子堆叠沉积于第一层42上。至少一个扩散阻挡层或黏着层44可由(例如)钛(Ti)组成。在一些实施方式中，至少一个扩散阻挡层或黏着层44包括钴、铬、镍-铬、镍铬合金、钼和/或亚氧化钛(titanium sub-oxide)。可调整该第二层44的厚度以便维持对随后沉积的第三层材料46的良好扩散阻挡。
第三层46是ITO层，其提供电功能，但无需提供任何特定光学功能。因此，可设定过程参数，使得优化ITO层46的性质用于与下面的扩散阻挡层44的低接触电阻。优选地，沉积技术(例如溅镀)应确保在ITO沉积之前，没有至少一个阻挡层或黏着层(例如Ti层44)的子堆叠的显著氧化。
堆叠40中的三个层42、44、46可展现并提供不同电功能。因此，例如，在一些实施方式中，相对较厚铝层42确保存在充分步阶覆盖和低电阻。Ti层44可充当铝层42与ITO层46之间的扩散阻挡以确保可靠和低接触电阻率。ITO层46可展现低电阻率并且还可充当盖层。因为用于层46的ITO材料已处于氧化状态中，所以其不易于进一步氧化。藉由提供ITO层46作为经氧化但导电的盖层，随后过程步骤将不藉由进一步氧化而损害ITO层46的表面。
在沉积用于堆叠40的层42、44、46之后，(例如)藉由剥离或其他技术来图案化(例如结构化)堆叠以确保周边没有栅栏或可不利地影响可靠性的其他剥离人为错误。
接下来，(例如)藉由剥离技术来沉积和图案化(例如结构化)第二ITO层48。第二ITO层48覆盖在光电二极管24上方的干涉滤波器32以及三层堆叠40的一部分。非导电氧化物层的形成不存在问题，因为接触形成发生在第一ITO层46(其已经氧化)与第二ITO层48之间。第二ITO层48可提供光学功能和电功能两者，并且因此可具有不同于第一ITO层46的组成的组成。因此，除经由堆叠40提供至焊盘32的电连接以便为光学滤波器22提供静电或RF屏蔽外，ITO层48也可具有指定光学性质(例如，在可见光谱的特定部分中的透明度)以允许可见光范围中的电磁辐射传递至滤波器32用于由光电二极管24检测。
在一些情况下，ITO层48覆盖有单层或多层抗反射涂层(anti-reflectioncoating，ARC)50以减少反射损耗。ARC 50也可充当用于防潮及抗氧化的下面的ITO层48的保护层。
类似技术也可用于其他类型的光电装置。例如，薄ITO层可集成在CMOS晶圆上以提供用于红外(IR)传感器的顶部电极和底部电极。图4绘示包括IR敏感有机层60的示例，该IR敏感有机层60用作用于感测IR范围中的光的有机光电检测器。该装置也包括顶部电极和底部电极，每个电极藉由在焊盘上的相应的堆叠40A、40B电耦合至相应的CMOS焊盘32A、32B。电极允许藉由调整所施加的电压来修改传感器的光电性质。
相应的堆叠40A、40B可以上文所描述的方式沉积在焊盘32A、32B中的每一个上。每个堆叠40A、40B包括在导电层42上的至少一个扩散阻挡层或黏着层44上的相应的第一ITO层46A、46B。如上文所提及，导电层42可由(例如)铝、金、银、铬和/或铜组成。每个堆叠40A、40B中的至少一个扩散阻挡层或黏着层44可包括(例如)钛、钴、铬、镍-铬、镍铬合金、钼和/或亚氧化钛。
接下来，沉积用作底部电极的第二ITO层48B。接着，沉积用作有机光电检测器的IR敏感有机层60，随后沉积用作顶部电极的第三ITO层48A。分别用作顶部电极和底部电极的两个ITO层48A、48B藉由先前沉积的多层堆叠40A、40B连接至相应的焊盘40A、40B。在一些情况下，沉积ARC层50以封装ITO层48A、48B并改善光学效能。
如结合图2和图3的示例所解释，形成在焊盘32A、32B上的多层堆叠40A、40B的一部分的ITO层46A、46B无需具有任何特定光学特性。相反，其可经定制以优化其电特性。另一方面，用作顶部电极和底部电极的ITO层48A、48B也可针对所期望光学特性优化。因此，ITO层48A、48B可具有与ITO层46A、46B的组成不同的组成。进一步地，ITO层48A、48B的组成可彼此不同。
顶部电极48A应具有对红外光的相对低的吸收和对检测器材料60的相对低的接触电阻。底部电极48B对IR光不应是透明的，但应对检测器材料60具有相对低的接触电阻。尽管ITO层因此适用于底部电极48B，但在一些情况下，可代替地使用在与检测器材料60的界面处不形成原生氧化物(native oxide)的贵金属。
藉由改变施加至焊盘32A、32B的电压信号，可改变施加至干涉滤波器32的电压以便实现特定光学滤波特性，并且藉此影响由光电二极管24感测的光的(多个)波长。
图5绘示替代实现方式，其中焊盘32上的导电材料的分层堆叠不包括ITO层46。而是，分层堆叠140包括设置在在焊盘32上设置的至少一个扩散阻挡层或黏着层144的子堆叠上的导电层142。至少一个扩散阻挡层或黏着层144可由(例如)钛(Ti)组成。在一些实施方式中，至少一个扩散阻挡层或黏着层144包括钴、铬、镍-铬、镍铬合金、钼和/或亚氧化钛。导电层142可由(例如)铝、金、银、铬和/或铜组成。
在图5的实施方式中，在沉积堆叠140的层144、142之前，沉积和图案化覆盖干涉滤波器32的ITO层148。堆叠的层144、142设置在焊盘32上方并且在晶圆20的表面上方延伸，使得其与ITO层148电接触。
如在图3的实施方式中，ITO层148可提供光学功能和电功能两者。因此，除经由堆叠140提供至焊盘32的电连接以便为光学滤波器22提供静电或RF屏蔽外，ITO层148也可具有指定光学性质(例如，可见光谱的特定部分中的透明度)以允许可见范围中的电磁辐射传递至滤波器32用于由光电二极管24检测。
在一些情况下，ITO层148覆盖有单层或多层抗反射涂层(anti-reflectioncoating，ARC)150以减少反射损耗。ARC 150也可充当下面的ITO层148的保护层。
前述技术实现直接在CMOS装置的顶部上制造连接至电路的ITO层并且可实现将ITO片上集成到CMOS过程中。此处所描述的技术可更一般地与至少部分在光学装置上形成的任何ITO电极结合使用，并且具体地在ITO电极需要对待由光学装置感测或透射通过光学装置的(多个)波长的光透明的情况下使用。因此，除上文所述的干涉滤波器和有机IR光电二极管的示例外，该技术也可与其他光学装置(诸如光谱仪，其中提供呈压电元件形式的弗雷比-珀罗(Fraby-Perot)干涉仪以调节光谱仪的腔厚度)结合使用。同样，该技术可与其中施加电压以便调整装置的透明度或不透明度的电光装置结合使用。进一步地，该前述技术可用于调整(例如)液晶的偏振态。
可在本公开的精神内做出各种修改。在一些情况下，结合不同实施例所描述的特征可在相同实施方式中组合。据此，其他实施方式在权利要求的范围内。

Claims (32)

1.一种设备，包括：
光学装置；
导电焊盘；
导电材料的多层堆叠，其在该焊盘上，该堆叠包括第一ITO层作为顶层；以及
第二ITO层，其至少部分设置在该光学装置上并且在该第一ITO层上。
2.根据权利要求1所述的设备，其中该第一ITO层具有与该第二ITO层的组成不同的组成。
3.根据权利要求1或2所述的设备，其中该第二ITO层覆盖该光学装置。
4.根据前述权利要求中任一项所述的设备，其中导电材料的该多层堆叠形成与该焊盘的欧姆接触。
5.根据前述权利要求中任一项所述的设备，其中导电材料的该多层堆叠包括与该焊盘直接接触的导电层，且至少一个扩散阻挡层或黏着层的子堆叠与该导电层直接接触，其中该第一ITO层与至少一个扩散阻挡层或黏着层的该子堆叠直接接触。
6.根据前述权利要求中任一项所述的设备，其中该多层堆叠包括在与该焊盘直接接触的铝层上的钛层，其中该第一ITO层在该钛层上。
7.根据前述权利要求中任一项所述的设备，其中该光学装置是光学干涉滤波器。
8.根据权利要求7所述的设备，其中该光学干涉滤波器设置在集成半导体电路中的光检测元件上方。
9.根据前述权利要求中任一项所述的设备，其中该光学装置是光电检测器并且其中该第二ITO层覆盖该光电检测器，该设备进一步包括：
第二导电焊盘；
不同导电材料的第二多层堆叠，其在该第二导电焊盘上，该第二堆叠包括顶层，该顶层包括第一ITO层；
电极层，其设置在该光学装置的与第二ITO层相对的一侧上并且连接至该第二堆叠的该第一ITO层。
10.根据权利要求9所述的设备，其中该光电检测器是有机红外光电检测器。
11.根据权利要求9或10所述的设备，其中设置在该光学装置的与该第二ITO层相对的一侧上的该电极层由第三ITO层组成。
12.根据前述权利要求中任一项所述的设备，其中该第一ITO层和该第二ITO层被集成为CMOS集成电路的一部分。
13.一种方法，包括：
提供包括导电焊盘的基板，光学装置设置在该基板上；
在该焊盘上提供导电材料的多层堆叠，该堆叠包括第一ITO层作为顶层；以及
提供至少部分在该光学装置和该第一ITO层上的第二ITO层。
14.根据权利要求13所述的方法，其中该第一ITO层具有与该第二ITO层的组成不同的组成。
15.根据权利要求13或14所述的方法，包括提供该第二ITO层，使得其覆盖该光学装置。
16.根据前述权利要求13-15中任一项所述的方法，其中导电材料的该多层堆叠形成与该焊盘的欧姆接触。
17.根据前述权利要求13-16中任一项所述的方法，其中提供多层堆叠包括：
沉积与该焊盘直接接触的导电层；
沉积与该导电层直接接触的至少一个扩散阻挡层或黏着层的子堆叠；以及
沉积与至少一个扩散阻挡层或黏着层的该子堆叠直接接触的该第一ITO层。
18.根据前述权利要求13-17中任一项所述的方法，其中提供多层堆叠包括：
在该焊盘上沉积铝层；
在该铝层上沉积钛层；以及
在该钛层上沉积该第一ITO层。
19.根据前述权利要求13-18中任一项所述的方法，其中该光学装置是光学干涉滤波器。
20.根据权利要求19所述的方法，其中该光学干涉滤波器设置在该基板中的集成半导体电路中的光检测元件上方。
21.根据前述权利要求13-20中任一项所述的方法，其中根据CMOS制造技术来处理该基板。
22.一种方法，包括：
提供包括第一导电焊盘和第二导电焊盘的基板；
在该第一焊盘上提供导电材料的第一多层堆叠，并且在该第二焊盘上提供导电材料的第二多层堆叠，该堆叠的每一个包括相应的第一ITO层作为顶层；
提供在该基板上并且连接至该第一多层堆叠的该第一ITO层的第二ITO层；
在该第二ITO层上提供光学装置；以及
提供至少部分在该光学装置上并且连接至该第二多层堆叠的该第一ITO层的第三ITO层。
23.根据权利要求22所述的方法，其中提供导电材料的该第一多层堆叠包括：
在该第一焊盘上沉积第一导电层；
在该第一导电层上沉积至少一个扩散层或阻挡层的第一子堆叠；以及
在至少一个扩散层或阻挡层的该第一子堆叠上沉积用于该第一堆叠的该第一ITO层，以及
其中提供导电材料的该第二多层堆叠包括：
在该第二焊盘上沉积第二导电层；
在该第二导电层上沉积至少一个扩散层或阻挡层的第二子堆叠；以及
在至少一个扩散层或阻挡层的该第二子堆叠上沉积用于该第二堆叠的该第一ITO层。
24.根据权利要求22或23所述的方法，其中提供该光学装置包括在该第二ITO层上提供有机红外光电检测器。
25.根据前述权利要求22-24中任一项所述的方法，其中根据CMOS制造技术来处理该基板。
26.一种设备，包括：
光学装置；
导电焊盘；
导电材料的多层堆叠，其在该焊盘上，该多层堆叠包括与该焊盘直接接触的至少一个扩散阻挡层或黏着层的子堆叠以及与该子堆叠直接接触的导电层；以及
ITO层，其至少部分设置在该光学装置上且与该多层堆叠电接触。
27.根据权利要求26所述的设备，其中该多层堆叠的该层沿其中设置该导电焊盘的基板的表面延伸，并且其中该ITO层的一部分在该多层堆叠的一部分之下。
28.根据权利要求26或27所述的设备，其中该ITO层覆盖该光学装置。
29.根据前述权利要求26-28中任一项所述的设备，其中导电材料的该多层堆叠形成与该焊盘的欧姆接触。
30.根据前述权利要求26-29中任一项所述的设备，其中该子堆叠包括钛层。
31.根据前述权利要求26-30中任一项所述的设备，其中该光学装置是设置在集成半导体电路中的光检测元件上方的光学干涉滤波器。
32.一种方法，其包括：
提供包括导电焊盘的基板，光学装置设置在该基板上；
提供至少部分在该光学装置上的ITO层，该ITO层沿该基板的表面延伸；以及
随后在该焊盘上提供导电材料的多层堆叠，该多层堆叠包括与该焊盘直接接触的至少一个扩散阻挡层或黏着层的子堆叠以及与该子堆叠直接接触的导电层，以及
其中该多层堆叠的该层沿该基板的表面延伸并且在该ITO层的一部分之上。
CN202080027234.9A 2019-04-09 2020-04-04 用于与焊盘的欧姆接触的氧化铟锡(ito)层的片上集成 Pending CN113661578A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201962831289P 2019-04-09 2019-04-09
US62/831,289 2019-04-09
PCT/EP2020/059697 WO2020207935A1 (en) 2019-04-09 2020-04-04 On-chip integration of indium tin oxide (ito) layers for ohmic contact to bond pads

Publications (1)

Publication Number Publication Date
CN113661578A true CN113661578A (zh) 2021-11-16

Family

ID=70483084

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080027234.9A Pending CN113661578A (zh) 2019-04-09 2020-04-04 用于与焊盘的欧姆接触的氧化铟锡(ito)层的片上集成

Country Status (5)

Country Link
US (1) US20220216244A1 (zh)
CN (1) CN113661578A (zh)
DE (1) DE112020001856T5 (zh)
TW (1) TW202105753A (zh)
WO (1) WO2020207935A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080265759A1 (en) * 2005-12-19 2008-10-30 Koninklijke Philips Electronics, N.V. Organic Led Device
US20130240923A1 (en) * 2012-03-16 2013-09-19 Epistar Corporation High brightness light emitting diode structure and the manufacturing method thereof
US20130284889A1 (en) * 2010-11-03 2013-10-31 Commissariat A L'energie Atomique Et Aux Energies Alternatives Monolithic multispectral visible and infrared imager
US20160020422A1 (en) * 2014-07-16 2016-01-21 Lg Display Co., Ltd. Organic light emitting display device and method of manufacturing the same
CN107783690A (zh) * 2016-08-31 2018-03-09 乐金显示有限公司 有机发光显示器及其制造方法、以及显示装置
CN108206198A (zh) * 2016-12-16 2018-06-26 乐金显示有限公司 具有集成触摸传感器的显示装置及其制造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4254681B2 (ja) * 2004-09-30 2009-04-15 豊田合成株式会社 電極形成方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080265759A1 (en) * 2005-12-19 2008-10-30 Koninklijke Philips Electronics, N.V. Organic Led Device
US20130284889A1 (en) * 2010-11-03 2013-10-31 Commissariat A L'energie Atomique Et Aux Energies Alternatives Monolithic multispectral visible and infrared imager
US20130240923A1 (en) * 2012-03-16 2013-09-19 Epistar Corporation High brightness light emitting diode structure and the manufacturing method thereof
US20160020422A1 (en) * 2014-07-16 2016-01-21 Lg Display Co., Ltd. Organic light emitting display device and method of manufacturing the same
CN107783690A (zh) * 2016-08-31 2018-03-09 乐金显示有限公司 有机发光显示器及其制造方法、以及显示装置
CN108206198A (zh) * 2016-12-16 2018-06-26 乐金显示有限公司 具有集成触摸传感器的显示装置及其制造方法

Also Published As

Publication number Publication date
TW202105753A (zh) 2021-02-01
US20220216244A1 (en) 2022-07-07
WO2020207935A1 (en) 2020-10-15
DE112020001856T5 (de) 2021-12-23

Similar Documents

Publication Publication Date Title
US11194152B2 (en) Electrically tunable fabry-perot interferometer, an intermediate product an electrode arrangement and a method for producing an electrically tunable fabry-perot interferometer
CN101728402A (zh) 光传感器
US5233181A (en) Photosensitive element with two layer passivation coating
EP2772939B1 (en) Semiconductor device for detection of radiation and method of producing a semiconductor device for detection of radiation
US9163984B2 (en) Spectroscopic sensor and angle limiting filter
KR101619186B1 (ko) 터치 스크린 패널 및 그 제조 방법
US4347436A (en) Photoelectric transducing element with high polymer substrate
EP0649517B1 (en) Microstructure design for high ir sensitivity
JPH04116986A (ja) 集積化太陽電池
KR20150017678A (ko) 광 필터, 광학 모듈, 전자 기기 및 광 필터의 제조 방법
JPH0421353B2 (zh)
US7382034B2 (en) Optoelectronic component having a conductive contact structure
CN102446018B (zh) 触控面板制造方法
CN102446019A (zh) 触控面板的制造方法
US10224449B2 (en) Photoresistors on silicon-on-insulator substrate and photodetectors incorporating same
CN113661578A (zh) 用于与焊盘的欧姆接触的氧化铟锡(ito)层的片上集成
US20210134886A1 (en) Optical sensor and thin film photodiode
US11728444B2 (en) Arrangement for an optoelectronic component, manufacturing process and optoelectronic component
JP2002299594A (ja) 赤外線反射膜を有する固体撮像素子及びその製造方法
CN107039474B (zh) 光电转换元件及其制造方法以及光电转换装置
US20210286109A1 (en) Liquid lenses and articles with contact pads for corrosion protection
KR20160111671A (ko) 이미지센서 및 이의 제조방법
CN110634892B (zh) 光电探测器及其制造方法、图像传感器
TW202043841A (zh) 液體透鏡及具有低反射率電極結構之液體透鏡製品
CN116469943A (zh) 光敏元件及光电部件

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination