CN113660052B - Precise clock synchronization device and method based on endogenous security mechanism - Google Patents
Precise clock synchronization device and method based on endogenous security mechanism Download PDFInfo
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- CN113660052B CN113660052B CN202111227438.XA CN202111227438A CN113660052B CN 113660052 B CN113660052 B CN 113660052B CN 202111227438 A CN202111227438 A CN 202111227438A CN 113660052 B CN113660052 B CN 113660052B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
- H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
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Abstract
The invention relates to the technical field of Ethernet clock synchronization, in particular to a precision clock synchronization device and a method based on an endogenous safety mechanism, wherein the device adopts pure hardware logic and comprises a master clock and a slave clock, the interaction of synchronous messages between the master clock and the slave clock physically uses the same channel, namely a synchronous message transmission channel, and the master clock comprises: the master clock synchronization module and the encryption sending module, wherein the slave clock comprises: the encryption sending module receives a synchronous message with a timestamp sent by the master clock synchronization module, carries out encryption identification processing on the message, then sends the message to the decryption receiving module through a synchronous message transmission channel for decryption judgment processing, and then outputs the message to the slave clock synchronization module to calculate clock synchronization deviation and carry out synchronization feedback so as to complete clock synchronization. The invention can effectively solve the potential safety hazard existing in the clock synchronization system and improve the safety of clock synchronization in the time sensitive system.
Description
Technical Field
The invention relates to the technical field of Ethernet clock synchronization, in particular to a precise clock synchronization device and method based on an endogenous safety mechanism.
Background
With the continuous improvement of the technology level of human beings, the clock synchronization of the system is required in many fields such as telecommunications, data centers, finance, automobiles and industry. The traditional improvement of clock synchronization technology mainly reflects in the improvement of clock synchronization precision, but the safety of clock synchronization is not considered enough. At present, the security problem of the network space is increasingly prominent, various uncertain threats are generated on the network space by the problems of unknown bugs, unknown backdoors, unknown attacks and the like, if the time synchronization messages in the system are maliciously tampered and cannot be identified by a clock and the time synchronization is performed by taking the time synchronization messages as a standard, disastrous consequences are generated on some systems, and higher requirements are provided for the security of the clock synchronization in the network system.
In view of such problems, a highly secure and precise clock synchronization method and apparatus are needed to protect the apparatus from internal or external time delay attacks.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides a precise clock synchronization device and method based on an intrinsic safety mechanism, and the specific technical scheme is as follows:
a precision clock synchronization device based on an intrinsic safety mechanism adopts pure hardware logic and comprises: the interaction of the synchronous messages between the master clock and the slave clock physically uses the same channel, namely a synchronous message transmission channel, and the master clock comprises: the master clock synchronization module and the encryption sending module, wherein the slave clock comprises: the encryption sending module receives a synchronous message with a timestamp sent by the master clock synchronization module, carries out encryption identification processing on the message, then sends the message to the decryption receiving module through a synchronous message transmission channel for decryption judgment processing, and then outputs the message to the slave clock synchronization module to calculate clock synchronization deviation and carry out synchronization feedback so as to complete clock synchronization.
Further, the encryption sending module includes: the master clock synchronization module sends a synchronization message with a timestamp to the synchronization message copying and distributing module for copying and distributing, and the synchronization message with the timestamp is sent to the delay compensation computing modules corresponding to the encryption algorithm modules respectively, the delay compensation computing module is used for performing delay computing, accumulating the computing result and the timestamp data in the synchronization message, sending the accumulated timestamp data to the corresponding encryption algorithm modules respectively for encryption, writing the encrypted result back to the timestamp field in the synchronization message, and then marking the synchronization message through the encryption identification modules respectively and sending the synchronization message to a slave clock.
Further, the delay compensation calculating module performs delay calculation, specifically: and calculating the time delay of the synchronous message copying and distributing module, the compensation calculation module, the encryption algorithm module and the encryption identification module.
Further, the decryption receiving module comprises: the synchronous message filtering and distributing module receives, filters and identifies the encrypted synchronous message and then sends the synchronous message to the corresponding decryption algorithm module, the decryption algorithm module takes out and decrypts the corresponding timestamp data in the synchronous message, the output arbitration algorithm module arbitrates the decrypted timestamp data, and outputs an arbitration result to the slave clock synchronization module and the feedback controller for clock synchronization deviation calculation and synchronous feedback respectively.
Further, the encryption sending module further includes: the decryption receiving module further comprises a master clock key controller and a master clock key pool, and the decryption receiving module further comprises: a slave clock key controller and a slave clock key pool.
Further, the outputting the arbitration result output by the arbitration algorithm module includes: the method comprises the steps of judging generated timestamp data and state information sent to a feedback controller, wherein the state information indicates whether an judging result is abnormal or not, if the state information shows that the judging result is abnormal, the feedback controller feeds the abnormal state information back to a master clock through a message, the master clock key controller selects a new key from a master clock key pool to replace an existing key according to a set rule after receiving the abnormal feedback message, meanwhile, broadcasts and sends a key replacement notification message to a slave clock, and after receiving the notification message, the slave clock key controller selects a new key from the slave clock key pool to replace the existing key according to the same rule as the master clock.
Further, the encryption algorithm module and the decryption algorithm module respectively comprise a plurality of different encryption algorithms and corresponding decryption algorithms, and the number of the encryption algorithms is not less than three, including AES, SM4 and Camellia.
A precision clock synchronization method based on an endogenous safety mechanism is based on a ping-pong time synchronization principle and specifically comprises the following steps:
1. the master clock sends a plurality of synchronous messages at the same time, and records the local time T1 sent by the master clock synchronization module and the accumulated value T1a of the encryption channel delay Ta of the message in the timestamp field of the synchronous message;
2. receiving a synchronous message from a clock, and recording the local time T2 when the synchronous message is received;
3. taking out the T1 +. Δ Ta value T1a from the timestamp field in the synchronous message after the clock is arbitrated by analysis;
4. the slave clock sends a delay request message to the master clock, and the sending time T3 is recorded;
5. the master clock receives the delay request message and records the arrival time T4 of the message;
6. the master clock sends a delay response message carrying a T4 value to inform the slave clock of the T4 value;
7. the four times are utilized: t1 Δ Ta, T2, T3, T4, calculate the offset compensation value between the slave clock and the master clock and the average delay MeanPathDelay value between the two clocks, and the expression is:
the slave clock accurately compensates and synchronizes its time according to the calculated offset and MeanPathDelay values.
The invention has the advantages that:
the precision clock synchronization device based on the endogenous safety mechanism can effectively solve the potential safety hazard existing in a clock synchronization system and improve the safety of clock synchronization in a time sensitive system;
the invention integrates various different encryption and decryption algorithms and a clock synchronization method based on a ping-pong time synchronization mechanism into a unified hardware system, and can provide an integrated solution for precise time synchronization in systems such as telecommunications, industry, automobiles and the like.
Drawings
FIG. 1 is a system block diagram of a precision clock synchronization apparatus based on an intrinsic safety mechanism according to the present invention;
fig. 2 is a schematic diagram of an encryption clock synchronization message interaction process based on the ping-pong time synchronization principle.
Detailed Description
In order to make the objects, technical solutions and technical effects of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings.
As shown in fig. 1, a precision clock synchronization apparatus based on an intrinsic safety mechanism is implemented by using pure hardware logic, and includes a master clock and a slave clock, where the interaction of a synchronization packet between the master clock and the slave clock physically uses the same channel, i.e., a synchronization packet transmission channel, and the master clock includes: the system comprises a master clock synchronization module and an encryption sending module, wherein the master clock synchronization module is responsible for the functions of calculation and selection of an optimal master clock, sending and receiving of clock synchronization messages, insertion of timestamps and the like; the slave clock includes: the slave clock synchronization module is responsible for receiving and sending clock synchronization messages, inserting timestamps, calculating clock deviation and the like. The slave clock corrects the clock by the interaction and calculation of the encrypted synchronous message between the slave clock and the master clock, so as to achieve precise time synchronization.
The encryption sending module comprises: the synchronous message copying and distributing module uses a hardware circuit to copy the same synchronous message in parallel and distribute the synchronous message to different encryption channels, the adoption of the hardware circuit ensures the consistency and the certainty of message input time delay of each encryption algorithm module, and each synchronous message is respectively subjected to delay calculation, timestamp encryption and message identification and then is sent to a slave clock aiming at different encryption channels, and the process of sending the synchronous message is specifically as follows: firstly, a main clock synchronization module sends out a synchronous message with a time stamp, a synchronous message copying and distributing module copies and distributes the message, the message is divided into three parts and respectively sent to time delay compensation calculation modules corresponding to three encryption algorithm modules, then, the time delay compensation calculation modules calculate the time delay of respective encryption steps, namely, the time delay of the synchronous message copying and distributing module, the self compensation calculation module, the encryption algorithm modules and the encryption identification module is calculated, the calculation result and the time stamp in the synchronous message are accumulated, the time sent out by a sending interface of the synchronous message is consistent with the time stamp in the synchronous message, the added result is real time stamp data after compensation, the accumulated time stamp data is sent to the respective encryption algorithm modules for encryption, the encrypted result is written in a time stamp field in a report message, and finally, marking the synchronous messages encrypted by different encryption algorithm modules respectively through an encryption identification module and then sending the synchronous messages to a slave clock. Because the time stamp data is encrypted and all modules are implemented by hardware, the time delay generated by the encryption algorithm and the addition of the encryption identifier needs to be accumulated in the encrypted time stamp data before encryption, and the time delay of each message after encryption is deterministic.
The decryption receiving module comprises: the synchronous message filtering and distributing module, the decryption algorithm module, the output arbitration algorithm module, the feedback controller, the slave clock key controller and the slave clock key pool adopt a hardware circuit to filter, identify and distribute decryption channels of the received synchronous message, so that the message can be correspondingly decrypted aiming at the corresponding encryption algorithm, timestamp data in the decrypted message is arbitrated by the arbitration algorithm module through a specific strategy, and the generated final arbitration result is used for calculating clock synchronization deviation. Specifically, the process of receiving the synchronization packet is as follows: firstly, a synchronous message filtering and distributing module filters and identifies a received message, an identification encryption identification module corresponds to the message encrypted by different encryption algorithm modules aiming at identification identifications added by different encryption algorithms, distributes the filtered and identified message to the corresponding decryption algorithm module, and then the decryption algorithm module takes out and decrypts corresponding timestamp data in the synchronous message; and finally, the output arbitration algorithm module compares and selects the three decrypted timestamp data, then the comparison result is output to a received slave clock synchronization module for calculation, namely, the output arbitration algorithm module judges the message output result in a mode of multi-selection, consistency comparison, weight arbitration and the like on the decrypted data of the same message subjected to three different encryption algorithms, sends the arbitrated state information to a feedback controller, and the slave clock synchronization module synchronizes according to the relevant arbitration result and the state information.
More specifically, the output result output by the output arbitration algorithm module includes the timestamp data generated by arbitration and the state information sent to the feedback controller, if the state information shows that the state information is abnormal, the feedback controller feeds the abnormal state information back to the master clock through a message, after receiving the abnormal feedback message, the master clock key controller selects a new key from the master clock key pool according to a set rule to replace the existing key, and simultaneously broadcasts and sends a key replacement notification message to the slave clocks, and after receiving the notification message, each slave clock key controller replaces the key according to the same rule as the master clock.
The encryption algorithm module and the decryption algorithm module respectively comprise several different encryption algorithms and corresponding decryption algorithms, but the encryption algorithms are not less than three according to a mimicry decision mechanism of an endogenous safety theory. During implementation, comprehensive balance can be carried out according to factors such as speed, area, complexity and the like of various algorithms, and then a proper algorithm, such as AES, SM4, Camellia and the like, is selected.
The encryption identification module is responsible for identifying the encrypted synchronous message, and the identification comprises identification of different encryption algorithms of the same message. Because the messages encrypted by a plurality of different encryption algorithm modules are sent in the same channel, the messages encrypted by the different encryption algorithm modules need to be identified, and the messages encrypted by the different encryption algorithms are represented as the same message.
The clock synchronization mechanism of the invention is based on the ping-pong time synchronization principle, and achieves the purpose of clock synchronization through three times of message interaction. Fig. 2 shows an encrypted clock synchronization packet interaction process based on the ping-pong clock synchronization principle, which specifically comprises the following steps:
1. the master clock sends three Sync messages at the same time, and records the local time T1 sent by the master clock synchronization module and the accumulated value T1a of the encryption channel delay Ta of the message in the timestamp field of the Sync message;
2. receiving a Sync message from a clock, and recording the local time T2 when the Sync message is received;
3. taking out the T1 +. Δ Ta value T1a from the timestamp field in the arbitrated Sync message through the analysis of the slave clock;
4. sending a Delay _ Req message to a master clock from the slave clock, and recording the sending time T3;
5. the main clock receives a Delay _ Req message and records the arrival time T4 of the message;
6. the master clock sends a Delay _ Resp message carrying a T4 value to inform a slave clock of the T4 value;
in the above steps, since the Sync is a Sync message, which carries the sending time of the Sync message from the sending port and needs to pass through the encrypted transmission channel, the encryption delay needs to be accumulated in the timestamp field before encryption. The Delay _ Req is a Delay request message, does not carry timestamp data, does not need encryption processing, and only needs a master clock and a slave clock to record sending and arrival time. While Delay _ Resp is a message corresponding to the Delay request, although the message is also encrypted by an encryption transmission channel, the Delay _ Req message carrying the arrival time of the Delay _ Req message, so that the time stamp field in the Delay _ Req message does not need to accumulate the encryption Delay.
The four times are utilized: t1 Δ Ta, T2, T3, T4, the offset compensation value between the slave and master clocks and the average delay MeanPathDelay value between the two clocks can be calculated:
therefore, the slave clock can accurately compensate and synchronize the time according to the calculated offset and the MeanPathDelay value.
Finally, it should also be noted that the above-mentioned list is only a specific embodiment of the invention. Obviously, the present invention is not limited to the above embodiments, and many variations are possible, for example, other more suitable algorithms may be adopted according to the requirements of the system on the amount of logic resources, time delay and speed required for encryption and decryption, or more than 3 encryption and decryption algorithms may be adopted to further ensure the security of the synchronized clock. In this embodiment, a one-step mode is adopted, and if a simpler two-step clock synchronization mode is adopted, a delay compensation calculation module can be omitted. Or similar methods for boundary clocks and transparent clocks, except for master and slave clocks, are within the scope of this patent. All modifications which can be derived or suggested by a person skilled in the art from the disclosure of the invention are considered to be within the scope of the invention.
Claims (7)
1. A precision clock synchronization device based on an endogenous safety mechanism adopts pure hardware logic and comprises a master clock and a slave clock, and the interaction of synchronous messages between the master clock and the slave clock physically uses the same channel, namely a synchronous message transmission channel, and is characterized in that the master clock comprises: the master clock synchronization module and the encryption sending module, wherein the slave clock comprises: the encryption sending module receives a synchronous message with a timestamp sent by the master clock synchronization module, encrypts the message to be identified, sends the message to the decryption receiving module through a synchronous message transmission channel to be decrypted and judged, and then outputs the message to the slave clock synchronization module to calculate clock synchronization deviation and perform synchronization feedback so as to complete clock synchronization;
the encryption sending module comprises: the master clock synchronization module sends a synchronization message with a timestamp to the synchronization message copying and distributing module for copying and distributing, and the synchronization message with the timestamp is sent to the delay compensation computing modules corresponding to the encryption algorithm modules respectively, the delay compensation computing module is used for performing delay computing, accumulating the computing result and the timestamp data in the synchronization message, sending the accumulated timestamp data to the corresponding encryption algorithm modules respectively for encryption, writing the encrypted result back to the timestamp field in the synchronization message, and then marking the synchronization message through the encryption identification modules respectively and sending the synchronization message to a slave clock.
2. The precision clock synchronization device based on the intrinsic safety mechanism as claimed in claim 1, wherein the delay compensation calculation module performs delay calculation, specifically: and calculating the time delay of the synchronous message copying and distributing module, the compensation calculation module, the encryption algorithm module and the encryption identification module.
3. The apparatus for fine clock synchronization based on intrinsic safety mechanism as claimed in claim 1, wherein the decryption receiving module comprises: the synchronous message filtering and distributing module receives, filters and identifies the encrypted synchronous message and then sends the synchronous message to the corresponding decryption algorithm module, the decryption algorithm module takes out and decrypts the corresponding timestamp data in the synchronous message, the output arbitration algorithm module arbitrates the decrypted timestamp data, and outputs an arbitration result to the slave clock synchronization module and the feedback controller for clock synchronization deviation calculation and synchronous feedback respectively.
4. The apparatus for fine clock synchronization based on intrinsic safety mechanism as claimed in claim 3, wherein the encryption transmission module further comprises: the decryption receiving module further comprises a master clock key controller and a master clock key pool, and the decryption receiving module further comprises: a slave clock key controller and a slave clock key pool.
5. The apparatus for precision clock synchronization based on intrinsic safety mechanism as claimed in claim 4, wherein the output arbitration algorithm module outputs the arbitration result comprising: the method comprises the steps of judging generated timestamp data and state information sent to a feedback controller, wherein the state information indicates whether an judging result is abnormal or not, if the state information shows that the judging result is abnormal, the feedback controller feeds the abnormal state information back to a master clock through a message, the master clock key controller selects a new key from a master clock key pool to replace an existing key according to a set rule after receiving the abnormal feedback message, meanwhile, broadcasts and sends a key replacement notification message to a slave clock, and after receiving the notification message, the slave clock key controller selects a new key from the slave clock key pool to replace the existing key according to the same rule as the master clock.
6. The apparatus of claim 3, wherein the encryption algorithm module and the decryption algorithm module respectively comprise a plurality of different encryption algorithms and corresponding decryption algorithms, and the number of the encryption algorithms is not less than three, including AES, SM4 and Camellia.
7. A method for clock synchronization by using the precision clock synchronization device based on the intrinsic safety mechanism as claimed in any one of claims 1 to 6, wherein the method specifically comprises the following steps based on the ping-pong time synchronization principle:
1. the master clock sends a plurality of synchronous messages at the same time, and records the local time T1 sent by the master clock synchronization module and the accumulated value T1a of the encryption channel delay Ta of the message in the timestamp field of the synchronous message;
2. receiving a synchronous message from a clock, and recording the local time T2 when the synchronous message is received;
3. taking out the T1 +. Δ Ta value T1a from the timestamp field in the synchronous message after the clock is arbitrated by analysis;
4. the slave clock sends a delay request message to the master clock, and the sending time T3 is recorded;
5. the master clock receives the delay request message and records the arrival time T4 of the message;
6. the master clock sends a delay response message carrying a T4 value to inform the slave clock of the T4 value;
7. the four times are utilized: t1 Δ Ta, T2, T3, T4, calculate the offset compensation value between the slave clock and the master clock and the average delay MeanPathDelay value between the two clocks, and the expression is:
the slave clock accurately compensates and synchronizes its time according to the calculated offset and MeanPathDelay values.
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| CN114389735A (en) * | 2021-12-06 | 2022-04-22 | 重庆邮电大学 | Clock synchronization method based on IEEE802.1AS redundant master clock |
| CN115426070B (en) * | 2022-11-02 | 2023-03-10 | 浙江国利信安科技有限公司 | Method, apparatus and storage medium for clock resynchronization |
| CN115941182B (en) * | 2023-02-21 | 2024-01-30 | 浙江国利信安科技有限公司 | Method, computing device, and storage medium for network key update |
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| CN112398567A (en) * | 2020-11-17 | 2021-02-23 | 珠海格力电器股份有限公司 | Clock synchronization method and device in encryption communication process and multi-device system |
| CN112769559A (en) * | 2020-12-31 | 2021-05-07 | 无锡艾立德智能科技有限公司 | Symmetric key synchronization method based on multiple keys |
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| CN109286460A (en) * | 2017-07-21 | 2019-01-29 | 北京智云芯科技有限公司 | A kind of method for synchronizing time and system based on wireless communication |
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