CN113658948B - MOSFET chip manufacturing method for improving turn-off characteristic - Google Patents
MOSFET chip manufacturing method for improving turn-off characteristic Download PDFInfo
- Publication number
- CN113658948B CN113658948B CN202110925732.1A CN202110925732A CN113658948B CN 113658948 B CN113658948 B CN 113658948B CN 202110925732 A CN202110925732 A CN 202110925732A CN 113658948 B CN113658948 B CN 113658948B
- Authority
- CN
- China
- Prior art keywords
- doped polysilicon
- oxide layer
- region
- forming
- lightly doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 96
- 229920005591 polysilicon Polymers 0.000 claims abstract description 82
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 238000002955 isolation Methods 0.000 claims abstract description 26
- 238000004080 punching Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 48
- 210000000746 body region Anatomy 0.000 claims description 22
- 238000005468 ion implantation Methods 0.000 claims description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 11
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 125000004437 phosphorous atom Chemical group 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 125000004429 atom Chemical group 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 239000003990 capacitor Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- High Energy & Nuclear Physics (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a MOSFET chip manufacturing method for improving turn-off characteristics, which comprises the following steps: and punching holes at two ends of the isolation oxide layer to obtain two resistance contact holes, wherein the resistance contact holes sequentially penetrate through the dielectric layer, the isolation oxide layer and the lightly doped polysilicon, and punching holes in the groove area to obtain a source area contact hole, and the source area contact hole sequentially penetrates through the dielectric layer, the gate oxide layer, the source area and the body area. And forming a first metal connecting wire and a second metal connecting wire in the resistor contact hole, forming a third metal connecting wire in the source region contact hole, connecting the first metal connecting wire with the third metal connecting wire, and connecting the second metal connecting wire with the grid. The invention integrates the polysilicon resistor in the chip, and the two ends of the resistor are respectively connected with the grid and the source, thereby ensuring that the charges stored in the grid parasitic capacitor are quickly discharged through the resistor when the chip is switched off, ensuring that the chip is completely cut off, and avoiding the phenomenon that the chip can not be completely switched off.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of an MOSFET chip with improved turn-off characteristics.
Background
The MOSFET chip is a discrete device, belongs to the field of semiconductor power devices, and belongs to the field of semiconductor chips with integrated circuits, wherein the integrated circuits integrate thousands of transistors in one chip through a process method, and the MOSFET is a single transistor formed by paralleling thousands of cells with the same structure.
The key index parameters of the MOSFET include breakdown voltage (specifically, drain-source breakdown voltage), on-resistance, threshold voltage, and avalanche current, and generally, the larger the breakdown voltage and avalanche current, the better the on-resistance. In order to realize the nominal breakdown voltage, an epitaxial layer with specific resistivity and specific thickness is adopted in the internal structure of the MOSFET chip to bear pressure, and the higher the breakdown voltage to be realized, the larger the resistivity or (and) thickness of the epitaxial layer is, the larger the on-resistance of the chip in unit area is, so that the breakdown voltage and the on-resistance of the chip in unit area are a pair of contradictory parameters; on the premise of ensuring the set breakdown voltage, the on-resistance of the unit area is reduced to the maximum extent, which is the responsibility of a chip engineer.
The MOSFET chip comprises three ports of a grid electrode, a source electrode and a drain electrode, and the three ports are respectively connected with a polysilicon gate, a drain region and a source region in the chip by adopting metal connecting wires and contact holes. The MOSFET is a voltage control device, that is, a driving circuit controls a potential difference between a gate and a source, thereby controlling on (on) and off (off) of the MOSFET. As shown in fig. 1, which is an equivalent circuit diagram of a MOSFET, parasitic capacitances Cgs, Cgd, and Cds exist between three ports of a gate, a source, and a drain.
In practical applications, when the MOSFET is required to be turned off, the pull-down circuit is arranged in the driving circuit to pull down the potential of the gate of the MOSFET, otherwise the gate of the MOSFET is floating, and the charge stored in the parasitic capacitance Cgs still exists, so that the gate still has a certain potential, that is, the MOSFET is not completely turned off. Just because parasitic capacitance Cgs exists in the MOSFET, the turn-off characteristic of the MOSFET is not perfect, and the phenomenon that the turn-off is not timely or complete often occurs.
Disclosure of Invention
The invention provides a manufacturing method of an MOSFET chip with improved turn-off characteristics, and aims to solve the problem that the existing MOSFET chip is not turned off in time or not turned off completely.
According to an embodiment of the present application, there is provided a MOSFET chip manufacturing method for improving turn-off characteristics, characterized in that: the method comprises the following steps: step S1: growing an epitaxial layer on the surface of a substrate, forming a groove in the epitaxial layer, and forming a gate oxide layer on the surface of the groove; step S2: forming lightly doped polysilicon in the trench; step S3: growing an isolation oxide layer on the surface of the lightly doped polycrystalline silicon, and removing the isolation oxide layer corresponding to the groove region; step S4: converting the lightly doped polysilicon in the trench region into heavily doped polysilicon; step S5: adjusting the height of the heavily doped polysilicon to be lower than that of the gate oxide layer, sequentially forming a body region and a source region in the region outside the trench, and forming a dielectric layer on the surfaces of the heavily doped polysilicon and the isolation oxide layer; step S6: punching holes at two ends of the isolation oxide layer to obtain two resistance contact holes, wherein the resistance contact holes sequentially penetrate through the dielectric layer, the isolation oxide layer and the lightly doped polysilicon, and punching holes in the groove region to obtain a source region contact hole, and the source region contact hole sequentially penetrates through the dielectric layer, the gate oxide layer, the source region and the body region; and step S7: and forming a first metal connecting wire and a second metal connecting wire in the resistor contact hole, forming a third metal connecting wire in the source region contact hole, connecting the first metal connecting wire with the third metal connecting wire, and connecting the second metal connecting wire with the grid.
Preferably, between step S6 and step S7, further comprising: step S100: and forming heavily doped silicon regions at the bottoms of the two resistor contact holes and the source region contact hole respectively.
Preferably, the doping type of the heavily doped silicon region in step S100 is the same as the doping type of the lightly doped polysilicon.
Preferably, step S2 mainly includes the steps of:
step S21: depositing initial polysilicon on the surface of the gate oxide layer in the trench region; step S22: and lightly doping the polycrystalline silicon by adopting an ion implantation process method to obtain the lightly doped polycrystalline silicon.
Preferably, in step S22, lightly doped polysilicon is formed by implanting boron atoms, or implanting phosphorus atoms and/or arsenic atoms; the type of the lightly doped polysilicon is opposite to that of the MOSFET chip; the dose of the atom implantation is 2E 13-6E 14 atoms/square centimeter.
Preferably, in step S4, implanting boron atoms or implanting phosphorus atoms and/or arsenic atoms into the lightly doped polysilicon to form heavily doped polysilicon; the type of the heavily doped polysilicon is opposite to that of the lightly doped polysilicon; the dose of the atomic implantation is 1E 15-2E 16 atoms/square centimeter.
Preferably, the step of forming the body region and the source region in step S5 specifically includes: step S51: forming a body region by adopting a process method of ion implantation and annealing, wherein the type of the body region is opposite to that of the MOSFET chip; step S52: and forming a source region by adopting the technological methods of photoetching, ion implantation and annealing, wherein the type of the source region is the same as that of the MOSFET chip.
Compared with the prior art, the manufacturing method of the MOSFET chip with the improved turn-off characteristic has the following beneficial effects:
1. according to the manufacturing method of the MOSFET chip, the polycrystalline silicon resistor is integrated in the MOSFET chip, and two ends of the polycrystalline silicon resistor are respectively connected to the grid electrode and the source electrode of the MOSFET, so that the electric charge stored in the grid parasitic capacitor can be rapidly discharged through the resistor when the MOSFET is turned off, the MOSFET is completely cut off, the phenomenon that the MOSFET cannot be completely turned off is avoided, meanwhile, the turn-off characteristic of the MOSFET chip is improved, and the driving circuit of the MOSFET chip can be greatly simplified. Particularly, the process method only needs to grow the polysilicon once, thereby saving the productivity of the polysilicon deposition process and having lower corresponding process cost. Furthermore, the grown isolation oxide layer can be used as a barrier layer for heavily doping the polysilicon in the trench region (to block the resistor region from being doped in this step), and can also be used as a barrier layer for etching the heavily doped polysilicon from top to bottom (to block the resistor region from being etched away).
2. The polysilicon resistor integrated in the MOSFET chip can adjust the resistance value by adjusting the ion implantation dosage, and the process is simple.
3. The integrated resistor is positioned in the MOSFET chip, and the resistor connected with the grid electrode and the source electrode of the MOSFET does not need to be designed on the periphery of the MOSFET chip, so that the space of a PCB (printed circuit board) can be saved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of an equivalent circuit of a MOSFET chip in the prior art.
Fig. 2 is a schematic equivalent circuit diagram of a MOSFET chip manufactured by the method for manufacturing a MOSFET chip with improved turn-off characteristics according to the first embodiment of the present invention.
Fig. 3 is a flowchart of a method for manufacturing a MOSFET chip with improved turn-off characteristics according to a first embodiment of the present invention.
Fig. 4 is a flowchart of step S2 in the MOSFET chip manufacturing method for improving the turn-off characteristic according to the first embodiment of the present invention.
Fig. 5 is a flowchart illustrating a process of forming the body region and the source region in step S5 in the MOSFET chip manufacturing method for improving turn-off characteristics according to the first embodiment of the present invention.
Fig. 6 is a schematic structural view of an epitaxial layer grown on the surface of a substrate.
Fig. 7 is a schematic structural diagram of a gate oxide layer formed by an oxidation process after a trench is etched to form a trench.
Fig. 8 is a schematic diagram of a structure for depositing and forming lightly doped polysilicon.
Fig. 9 is a schematic structural diagram of growing an isolation oxide layer.
Fig. 10 is a schematic structural diagram of etching to remove the isolation oxide layer in the trench region and converting the lightly doped polysilicon in the trench region into heavily doped polysilicon.
Fig. 11 is a schematic diagram of a structure for adjusting the height of heavily doped polysilicon.
Fig. 12 is a schematic structural view of the body region and the source region.
Fig. 13 is a schematic view of a structure in which a dielectric layer is formed and then perforated.
Fig. 14 is a schematic diagram of a structure for forming heavily doped silicon regions at the bottom of contact holes.
Fig. 15 is a schematic structural view of forming a metal wiring in a contact hole.
Description of reference numerals:
1. a substrate; 2. an epitaxial layer; 3. a groove, 4 and a gate oxide layer; 5. lightly doping polycrystalline silicon; 5.1, heavily doping polysilicon; 6. isolating the oxide layer; 7. a body region; 8. a source region; 9. a dielectric layer; 10.1, a source region contact hole; 10.2/10.3 resistance contact hole; 11. a heavily doped silicon region; 12.1, a third metal connecting line; 12.2, a first metal connecting line; 12.3, second metal connecting lines.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
Referring to fig. 3, a first embodiment of the present invention discloses a method for manufacturing a MOSFET chip with improved turn-off characteristics, comprising the following steps:
step S1: growing an epitaxial layer on the surface of a substrate, forming a groove in the epitaxial layer, and forming a gate oxide layer on the surface of the groove.
Step S2: and forming lightly doped polysilicon in the groove.
Step S3: and growing an isolation oxide layer on the surface of the lightly doped polycrystalline silicon, and removing the isolation oxide layer corresponding to the groove region.
Step S4: and converting the lightly doped polysilicon in the groove area into heavily doped polysilicon.
Step S5: and adjusting the height of the heavily doped polysilicon to be lower than that of the gate oxide layer, sequentially forming a body region and a source region in the region outside the trench, and forming a dielectric layer on the surfaces of the heavily doped polysilicon and the isolation oxide layer.
Step S6: and punching holes at two ends of the isolation oxide layer to obtain two resistance contact holes, wherein the resistance contact holes sequentially penetrate through the dielectric layer, the isolation oxide layer and the lightly doped polysilicon, and punching holes in the groove area to obtain a source area contact hole, and the source area contact hole sequentially penetrates through the dielectric layer, the gate oxide layer, the source area and the body area.
And
step S7: and forming a first metal connecting wire and a second metal connecting wire in the resistor contact hole, forming a third metal connecting wire in the source region contact hole, connecting the first metal connecting wire with the third metal connecting wire, and connecting the second metal connecting wire with the grid.
It is to be understood that in step S1, epitaxial layer 2 is grown on the surface of substrate 1, and trenches 3 and gate oxide layer 4 are formed in epitaxial layer 2 by photolithography, etching, and oxidation processes, as shown in detail in fig. 6 and 7.
It is to be understood that in step S3, the isolation oxide layer 6 is grown on the surface of the lightly doped polysilicon 5, and the isolation oxide layer at the position of the trench region is removed by using a photolithography and etching process. See figures 9 and 10 for details.
It is understood that in step S4, the region where the isolation oxide layer 6 is removed is processed to perform ion implantation heavy doping on the lightly doped polysilicon 5, and then high temperature annealing is performed to form the heavily doped polysilicon 5.1. See figure 10 for details.
Specifically, in step S4, boron atoms or phosphorus atoms and/or arsenic atoms are implanted into the lightly doped polysilicon 5 to form heavily doped polysilicon, the type of the heavily doped polysilicon is opposite to that of the lightly doped polysilicon, and the dose of the atom implantation is 1E 15-2E 16 atoms/cm. For example, when the MOSFET is an N-type MOSFET, implanting phosphorus atoms or (and) arsenic atoms forms N-type heavily doped polysilicon, and when the MOSFET is a P-type MOSFET, implanting boron atoms forms P-type heavily doped polysilicon.
It can be understood that in step S5, the heavily doped polysilicon 5.1 is etched from top to bottom by using a dry etching process, so that the height of the upper surface of the heavily doped polysilicon 5.1 is not higher than the height of the gate oxide layer 4. Due to the blocking effect of the isolation oxide layer 6, the polysilicon (i.e., the lightly doped polysilicon 5) in the region covered by the isolation oxide layer 6 is not etched away. Then, a process method of ion implantation and annealing is adopted to form the body region 7, a process method of photoetching, ion implantation and annealing is adopted to form the source region 8, and then the dielectric layer 9 is deposited. See figures 11 and 12 for details.
It is understood that, in step S5, the type of the heavy doping is opposite to the type of the light doping in step S2, but since the dose of the ion implantation at this step is much larger than that in step S2, the lightly doped polysilicon 5 in the trench region is inverted to the heavily doped polysilicon 5.1 after the ion implantation of the heavy doping in step S5.
It is understood that in step S6, contact holes 10.1, 10.2 and 10.3 are formed by using photolithography and etching processes, where contact hole 10.1 is a source region contact hole, and contact holes 10.2 and 10.3 are resistance contact holes. Contact holes 10.2 and 10.3 are made at two ends of the lightly doped polysilicon 5, and metal is led out, so that the complete polysilicon resistor is formed. See figure 13 for details.
It can be understood that, in step S7, metal is deposited and removed from the set region to form a third metal line 12.1, the first metal line 12.2 and the second metal line 12.3 at two ends of the polysilicon resistor connect the first metal line 12.2 and the third metal line 12.1, and the second metal line 12.3 connects the gate, so as to form the novel MOSFET chip as shown in fig. 2. See figure 15 for details.
It can be understood that, in the present embodiment, since the schematic diagram only shows a certain cross section of the MOSFET chip, the gate contact hole and the gate metal line of the MOSFET are not shown in the schematic diagram. The passivation layer and the backside processing of the MOSFET are conventional and will not be described herein.
Optionally, as an embodiment, between the step S6 and the step S7, the method further includes:
step S100: and forming heavily doped silicon regions at the bottoms of the two resistor contact holes and the source region contact hole respectively.
It is to be understood that in step S100, when the MOSFET is an N-type MOSFET, boron atoms are implanted and then annealed to form a P-type bottom heavily doped silicon region 11. When the MOSFET is a P-type MOSFET, phosphorus or (and) arsenic atoms are implanted and then annealed to form an N-type bottom of hole heavily doped silicon region 11. See figure 14 for details.
In the present embodiment, the doping type of the heavily doped silicon region 11 at the bottom of the hole is the same as the doping type of the lightly doped polysilicon 5 and the doping type of the body region 7, so that the contact hole resistance of the body region 7 can be reduced, and the resistance value of the resistance contact hole corresponding to the lightly doped polysilicon 5 can be reduced.
Referring to fig. 2, step S2 specifically includes:
step S21: and depositing initial polysilicon on the surface of the gate oxide layer in the trench area.
Step S22: and lightly doping the polycrystalline silicon by adopting an ion implantation process method to obtain the lightly doped polycrystalline silicon.
In step S21, undoped polysilicon is first deposited (chemical vapor deposition process), and the polysilicon is lightly doped by ion implantation process based on step S22 to form lightly doped polysilicon 5.
It is understood that in step S22, lightly doped polysilicon is formed by implanting boron atoms, or implanting phosphorus atoms and/or arsenic atoms, the type of the lightly doped polysilicon is opposite to that of the MOSFET chip, and the dose of the atomic implantation is 2E 13-6E 14 atoms/cm. Specifically, when the MOSFET is an N-type MOSFET, boron atoms are implanted to form P-type lightly doped polysilicon. When the MOSFET is a P-type MOSFET, phosphorus atoms or (and) arsenic atoms are implanted to form N-type lightly doped polysilicon.
Referring to fig. 3, the step of forming the body region and the source region in step S5 includes:
step S51: and forming a body region by adopting a process method of ion implantation and annealing, wherein the type of the body region is opposite to that of the MOSFET chip.
Step S52: and forming a source region by adopting the technological methods of photoetching, ion implantation and annealing, wherein the type of the source region is the same as that of the MOSFET chip.
It is to be understood that in step S51, for example, when the MOSFET is an N-type MOSFET, boron atoms are implanted and then annealed to form a P-type body region, and when the MOSFET is a P-type MOSFET, phosphorus atoms or (and) arsenic atoms are implanted and then annealed to form an N-type body region.
It is to be understood that in step S52, for example, when the MOSFET is an N-type MOSFET, the N-type source region is formed by photolithography, implantation of phosphorus atoms or (and) arsenic atoms and then annealing, and when the MOSFET is a P-type MOSFET, the P-type source region is formed by photolithography, implantation of boron atoms and then annealing.
It can be understood that, by the method for manufacturing the MOSFET chip with improved turn-off characteristics provided by the present invention, a (or several) resistor is integrated inside the MOSFET chip, and two ends of the resistor are respectively connected to the gate and the source of the MOSFET (as shown in the equivalent circuit diagram of fig. 2). The resistor is a polysilicon resistor and is positioned inside the MOSFET chip, and is not connected with and combined with the MOSFET by a packaging method or a PCB circuit layout method.
Compared with the prior art, the manufacturing method of the MOSFET chip with the improved turn-off characteristic has the following beneficial effects:
1. according to the manufacturing method of the MOSFET chip, the polycrystalline silicon resistor is integrated in the MOSFET chip, and two ends of the polycrystalline silicon resistor are respectively connected to the grid electrode and the source electrode of the MOSFET, so that the electric charges stored in the grid parasitic capacitor can be rapidly discharged through the resistor when the MOSFET is turned off, the MOSFET is completely cut off, the phenomenon that the MOSFET cannot be completely turned off is avoided, meanwhile, the turn-off characteristic of the MOSFET chip is improved, and the driving circuit of the MOSFET chip can be greatly simplified. Particularly, the process method only needs to grow the polysilicon once, thereby saving the productivity of the polysilicon deposition process and having lower corresponding process cost. Furthermore, the grown isolation oxide layer can be used as a barrier layer for heavily doping the polysilicon in the trench region (to block the resistor region from being doped in this step), and can also be used as a barrier layer for etching the heavily doped polysilicon from top to bottom (to block the resistor region from being etched away).
2. The polysilicon resistor integrated in the MOSFET chip can adjust the resistance value by adjusting the ion implantation dosage, and the process is simple.
3. The integrated resistor is positioned in the MOSFET chip, and the resistor connected with the grid electrode and the source electrode of the MOSFET does not need to be designed on the periphery of the MOSFET chip, so that the space of a PCB (printed circuit board) can be saved.
While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (7)
1. A method for manufacturing a MOSFET chip with improved turn-off characteristics, comprising: the method comprises the following steps:
step S1: growing an epitaxial layer on the surface of a substrate, forming a groove in the epitaxial layer, and forming a gate oxide layer on the surface of the groove;
step S2: depositing lightly doped polysilicon on the gate oxide layer;
step S3: growing an isolation oxide layer on the surface of the lightly doped polycrystalline silicon, and removing the isolation oxide layer corresponding to the groove region;
step S4: converting the lightly doped polysilicon in the trench region into heavily doped polysilicon;
step S5: adjusting the height of the heavily doped polysilicon to be lower than that of the gate oxide layer, sequentially forming a body region and a source region in the region outside the trench, and forming a dielectric layer on the surfaces of the heavily doped polysilicon and the isolation oxide layer;
step S6: punching holes at two ends of the isolation oxide layer to obtain two resistance contact holes, wherein the resistance contact holes sequentially penetrate through the dielectric layer, the isolation oxide layer and the lightly doped polysilicon, and punching holes in the groove region to obtain a source region contact hole, and the source region contact hole sequentially penetrates through the dielectric layer, the gate oxide layer, the source region and the body region;
step S7: and forming a first metal connecting wire and a second metal connecting wire in the resistor contact hole, forming a third metal connecting wire in the source region contact hole, connecting the first metal connecting wire with the third metal connecting wire, and connecting the second metal connecting wire with the grid.
2. The method of manufacturing a MOSFET chip with improved turn-off characteristics according to claim 1, wherein: between the step S6 and the step S7, the method further comprises:
step S100: and forming heavily doped silicon regions at the bottoms of the two resistor contact holes and the source region contact hole respectively.
3. The method of manufacturing a MOSFET chip with improved turn-off characteristics according to claim 2, wherein: the doping type of the heavily doped silicon region in step S100 is the same as the doping type of the lightly doped polysilicon.
4. The method of manufacturing a MOSFET chip with improved turn-off characteristics according to claim 1, wherein: step S2 mainly includes the following steps:
step S21: depositing initial polysilicon on the surface of the gate oxide layer in the trench region;
step S22: and lightly doping the polycrystalline silicon by adopting an ion implantation process method to obtain the lightly doped polycrystalline silicon.
5. The method of manufacturing a MOSFET chip with improved turn-off characteristics according to claim 4, wherein: in step S22, lightly doped polysilicon is formed by implanting boron atoms, or implanting phosphorus atoms and/or arsenic atoms;
the type of the lightly doped polysilicon is opposite to that of the MOSFET chip;
the dose of the atom implantation is 2E 13-6E 14 atoms/square centimeter.
6. The method of manufacturing a MOSFET chip with improved turn-off characteristics according to claim 5, wherein: in step S4, boron atoms are implanted into the lightly doped polysilicon, or phosphorus atoms and/or arsenic atoms are implanted into the lightly doped polysilicon to form heavily doped polysilicon;
the type of the heavily doped polysilicon is opposite to that of the lightly doped polysilicon;
the dose of the atomic implantation is 1E 15-2E 16 atoms/square centimeter.
7. The method of manufacturing a MOSFET chip with improved turn-off characteristics according to claim 1, wherein: the step of forming the body region and the source region in step S5 specifically includes:
step S51: forming a body region by adopting a process method of ion implantation and annealing, wherein the type of the body region is opposite to that of the MOSFET chip;
step S52: and forming a source region by adopting the technological methods of photoetching, ion implantation and annealing, wherein the type of the source region is the same as that of the MOSFET chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110925732.1A CN113658948B (en) | 2021-08-12 | 2021-08-12 | MOSFET chip manufacturing method for improving turn-off characteristic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110925732.1A CN113658948B (en) | 2021-08-12 | 2021-08-12 | MOSFET chip manufacturing method for improving turn-off characteristic |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113658948A CN113658948A (en) | 2021-11-16 |
| CN113658948B true CN113658948B (en) | 2022-06-07 |
Family
ID=78491559
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110925732.1A Active CN113658948B (en) | 2021-08-12 | 2021-08-12 | MOSFET chip manufacturing method for improving turn-off characteristic |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113658948B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6027964A (en) * | 1997-08-04 | 2000-02-22 | Advanced Micro Devices, Inc. | Method of making an IGFET with a selectively doped gate in combination with a protected resistor |
| CN106816433A (en) * | 2015-12-01 | 2017-06-09 | 无锡华润上华半导体有限公司 | A kind of manufacture method of polysilicon high-ohmic |
| CN109273533A (en) * | 2018-09-26 | 2019-01-25 | 中国电子科技集团公司第二十四研究所 | A kind of VDMOS device structure and preparation method thereof with self-switching-off capability |
| CN112103186A (en) * | 2020-09-22 | 2020-12-18 | 深圳市芯电元科技有限公司 | Process method for improving cell density of trench MOSFET and trench MOSFET structure |
| CN112510093A (en) * | 2020-12-01 | 2021-03-16 | 无锡先瞳半导体科技有限公司 | Method for producing NLDMOS device and NLDMOS device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7846783B2 (en) * | 2008-01-31 | 2010-12-07 | Texas Instruments Incorporated | Use of poly resistor implant to dope poly gates |
| US8164162B2 (en) * | 2009-06-11 | 2012-04-24 | Force Mos Technology Co., Ltd. | Power semiconductor devices integrated with clamp diodes sharing same gate metal pad |
| JP5479245B2 (en) * | 2010-07-01 | 2014-04-23 | 株式会社東芝 | Semiconductor device |
-
2021
- 2021-08-12 CN CN202110925732.1A patent/CN113658948B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6027964A (en) * | 1997-08-04 | 2000-02-22 | Advanced Micro Devices, Inc. | Method of making an IGFET with a selectively doped gate in combination with a protected resistor |
| CN106816433A (en) * | 2015-12-01 | 2017-06-09 | 无锡华润上华半导体有限公司 | A kind of manufacture method of polysilicon high-ohmic |
| CN109273533A (en) * | 2018-09-26 | 2019-01-25 | 中国电子科技集团公司第二十四研究所 | A kind of VDMOS device structure and preparation method thereof with self-switching-off capability |
| CN112103186A (en) * | 2020-09-22 | 2020-12-18 | 深圳市芯电元科技有限公司 | Process method for improving cell density of trench MOSFET and trench MOSFET structure |
| CN112510093A (en) * | 2020-12-01 | 2021-03-16 | 无锡先瞳半导体科技有限公司 | Method for producing NLDMOS device and NLDMOS device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113658948A (en) | 2021-11-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101900843B1 (en) | Trench power MOSFET with reduced on-resistance | |
| US7566931B2 (en) | Monolithically-integrated buck converter | |
| US7417266B1 (en) | MOSFET having a JFET embedded as a body diode | |
| GB2318685A (en) | MOS gated device with self aligned cells | |
| US8093661B2 (en) | Integrated circuit device with single crystal silicon on silicide and manufacturing method | |
| TW201906177A (en) | High voltage resistor device and method of forming the same | |
| EP1846953A2 (en) | Integrated circuit including power diode | |
| US9899377B2 (en) | Insulated gate semiconductor device with soft switching behavior | |
| WO2006107564A2 (en) | Semiconductor power deviceand corrisponding manufacturing process | |
| US11264269B1 (en) | Method of manufacturing trench type semiconductor device | |
| CN114361250A (en) | Mosfet with enhanced high frequency performance | |
| CN113658949B (en) | MOSFET chip manufacturing process capable of improving turn-off characteristic | |
| CN113764407B (en) | MOSFET chip manufacturing process for improving gate characteristics | |
| US20200303539A1 (en) | Transistor Having at Least One Transistor Cell with a Field Electrode | |
| US8525256B2 (en) | Power semiconductor structure with schottky diode | |
| CN116913780A (en) | Shielding gate groove type MOS device structure and preparation method thereof | |
| CN113658948B (en) | MOSFET chip manufacturing method for improving turn-off characteristic | |
| CN108091695B (en) | Vertical double-diffused field effect transistor and manufacturing method thereof | |
| CN107910271B (en) | Power semiconductor device and method of manufacturing the same | |
| US20220384594A1 (en) | Metal-oxide-semiconductor field-effect transistor having enhanced high-frequency performance | |
| CN113643982B (en) | MOSFET chip manufacturing method for improving grid characteristics | |
| US11444167B2 (en) | Method of manufacturing trench type semiconductor device | |
| CN114005789A (en) | Manufacturing method of MOSFET (metal-oxide-semiconductor field effect transistor) of shielded gate trench | |
| US20220157988A1 (en) | Power semiconductor device and fabrication method thereof | |
| TWI606519B (en) | Trench power semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |