CN113658561B - Gate drive circuit and display device - Google Patents
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- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
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- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
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Abstract
The invention relates to a gate driving circuit and a display device, comprising a plurality of cascaded gate driving units, wherein each gate driving unit is used for driving a corresponding gate line on a display panel, and each gate driving unit comprises: the output module is connected with the first node, generates a current-level grid driving signal according to a second clock signal and provides the current-level grid driving signal at an output end, the stabilizing module comprises a first capacitor and a second node, the first capacitor is connected between the first node and the second node, and the stabilizing module adjusts the voltage of the second node according to the first clock signal and the second clock signal so that the voltage difference between the first node and the output end is smaller than 0. The grid driving circuit disclosed by the invention is simple in structure, beneficial to realization of a narrow frame, compatible with a thin film transistor using amorphous silicon and a metal oxide material, and capable of effectively solving the leakage current phenomenon of the grid driving circuit at a low-voltage stable stage.
Description
Technical Field
The invention relates to the technical field of display, in particular to a gate driving circuit and a display device.
Background
Liquid Crystal Display (LCD) devices have many advantages of being light, thin, energy-saving, and radiation-free, and have been widely used to replace conventional Cathode Ray Tube (CRT) displays, and are widely applied to electronic devices such as digital televisions, desktop computers, notebook computers, personal digital assistants, mobile terminals, and digital cameras.
Taking a Thin Film Transistor (TFT) liquid crystal display device as an example, it includes: the liquid crystal display panel comprises a plurality of gate lines and a plurality of data lines, two adjacent gate lines and two adjacent data lines are crossed to form a pixel unit, and each pixel unit at least comprises a thin film transistor. And the driving circuit includes: the gate driving circuit includes a plurality of gate driving units, and the source driving circuit includes a source driver and a drain driver. And as the display technology is developed, the display panel tends to have high integration and low cost, and the Gate driving circuit is integrated on the Array substrate (GIA) of the display panel, thereby simplifying the manufacturing process of the liquid crystal display device, reducing the production cost, and improving the integration.
The gate driving unit includes a plurality of switching elements, and applies a positive voltage or a negative voltage to gates of the plurality of switching elements using a timing signal to control on and off of the plurality of switching elements, thereby outputting an ideal gate driving signal. Referring to fig. 1, fig. 1 shows a circuit configuration diagram of a gate driving unit, as shown in fig. 1, the gate driving unit includes a plurality of switching transistors T1-T8 and a bootstrap capacitor C1, and the gate driving unit receives a plurality of input signals (including a positive polarity voltage DC, a plurality of clock signals CLK 1-CLK 4, a low level signal VGL, a four-stage previous gate driving signal Gn +4, a four-stage next gate driving signal Gn +4, and a start signal STV additionally provided, of course) to generate a present stage gate driving signal Gn.
The substrate materials used by the current TFT-LCD display field products are mainly divided into three types: amorphous silicon (a-Si), metal Oxide (Oxide), and Low Temperature Polysilicon (LTPS), wherein the amorphous silicon (a-Si) technology is mature, low cost, and is the mainstream material in the market at present, but the IGZO metal Oxide (one of the metal oxides) technology has the advantages of both. But it is difficult for the silicon material based GIA design to meet the performance of the TFT switch of the metal oxide material. For example, in the GIA circuit of 8T1C shown in fig. 1, when the TFT of the transistor is switched using the metal oxide material, since the threshold voltage Vth is negative, in the low voltage maintaining stage of the gate driving unit, the voltages of the gate and the source of the switching transistor T2 are the same and are both VGL, that is, the gate-source voltage Vgs of T2 is 0V, Vgs is much larger than Vth, and at this time, the leakage current is large, and the TFT using the IGZO metal oxide material cannot normally operate, specifically referring to fig. 2, fig. 2 shows a graph illustrating a relationship between the gate-source voltage and the leakage current of the transistor, as shown in fig. 2, when the gate-source voltage Vgs of the transistor is 0V, the leakage current Ids can reach 10 -7 A～10 -8 Between A, the switching performance requirements of the TFT cannot be met.
With respect to the above problem, in the prior art, many of the GIA designs based on metal oxide materials solve the problem of large leakage current by using two VGLs, namely VGL1 and VGL2, and setting the gate of the TFT outputting the gate driving signal Gn as VGL1, the source as VGL2, and VGL1 < VGL2 during the low voltage stabilization phase, so that the gate-source voltage Vgs is less than 0. However, the GIA circuit is complex, uses a large number of signals, occupies a large area, and is not favorable for narrow-frame design.
Disclosure of Invention
In view of this, an object of the present invention is to provide a gate driving circuit and a display device, which are compatible with amorphous silicon and metal oxide thin film transistors, and effectively solve the leakage current phenomenon of the gate driving circuit at the low-voltage stable stage, and the circuit structure is simple, and is beneficial to the implementation of a narrow frame.
To achieve the above object, a first aspect of embodiments of the present invention provides a gate driving circuit, which as an implementation manner includes a plurality of gate driving units connected in cascade, each gate driving unit being configured to drive a corresponding gate line on a display panel, and each gate driving unit includes:
the input module is connected with a first node and charges the first node according to a first clock signal and a first starting signal;
the output module is connected with the first node, generates a current-stage grid driving signal according to a second clock signal and provides the current-stage grid driving signal at an output end;
the pull-down module is connected with the first node, the output end and the low level signal end, and is used for pulling down the potential of the first node to a low level according to a second starting signal and pulling down the current-stage grid driving signal to a low level according to the first clock signal;
the stabilizing module comprises a first capacitor and a second node, the first capacitor is connected between the first node and the second node, and the stabilizing module adjusts the voltage of the second node according to the first clock signal and the second clock signal, so that the voltage difference between the first node and the output end is smaller than 0.
As one embodiment, the gate driving circuit includes N cascaded gate driving units, a first start signal of a first stage gate driving unit in the gate driving circuit is a first pulse signal provided outside the gate driving circuit, and a second start signal of the first stage gate driving unit is a gate driving signal provided by a second stage gate driving unit;
a first start signal of a last stage gate driving unit in the gate driving circuit is a gate driving signal provided by a previous stage gate driving unit, and a second start signal of the last stage gate driving unit is a second pulse signal provided outside the gate driving circuit;
the first starting signal of the nth level gate driving unit in the gate driving circuit is a gate driving signal provided by the (N-1) th level gate driving unit, the second starting signal of the nth level gate driving unit is a gate driving signal provided by the (N + 1) th level gate driving unit, wherein N is more than 1 and less than N, and N is a positive integer.
As one embodiment, the input module includes: a control end of the first switch tube receives the first clock signal, a first path end of the first switch tube receives the first start signal, and a second path end of the first switch tube is connected with the first node.
As one embodiment, the output module includes:
a control end of the second switching tube is connected with the first node, a first path end of the second switching tube receives the second clock signal, and a second path end of the second switching tube is connected with the output end;
and the second capacitor is connected between the control end of the second switch tube and the second path end of the second switch tube.
In one embodiment, the capacitance of the second capacitor is greater than the capacitance of the first capacitor.
As one embodiment, the pull-down module includes:
a control end of the third switch tube receives the first clock signal, a first pass end of the third switch tube is connected with the output end, and a second pass end of the third switch tube is connected with the low-level signal end;
and the control end of the fourth switching tube receives the second starting signal, the first path end of the fourth switching tube is connected with the first node, and the second path end of the fourth switching tube is connected with the low-level signal end.
As one embodiment, the stabilizing module further comprises:
a control end of the fifth switching tube is connected with a first path end of the fifth switching tube and receives the first clock signal, and a second path end of the fifth switching tube is connected with the second node;
and the control end of the sixth switching tube receives the second clock signal, the first path end of the sixth switching tube is connected with the second node, and the second path end of the sixth switching tube receives the first clock signal.
In one embodiment, the switching transistor in the gate driving circuit is a metal oxide thin film transistor or an amorphous silicon thin film transistor.
In one embodiment, the switching tube in the gate driving circuit is an N-type transistor.
In order to achieve the above object, another aspect of the embodiments of the present invention provides a display device, which includes as one embodiment:
a gate drive circuit, the gate drive circuit being one of the gate drive circuits described in any of the above embodiments, configured to provide a plurality of gate drive signals;
a source driver circuit for providing a plurality of gray scale data; and
a display panel including a plurality of pixel units arranged in an array, and a plurality of gate lines and a plurality of data lines; wherein,
the display panel receives the gate driving signals through the gate lines to select the pixel units according to the row, and receives the gray scale data through the data lines to provide the gray scale data to the selected pixel units to realize image display.
To sum up, the gate driving circuit and the display device provided by the embodiment of the present invention include a plurality of gate driving units connected in cascade, each gate driving unit is configured to drive a corresponding gate line on a display panel, and each gate driving unit includes: the input module is connected with the first node and charges the first node according to the first clock signal and the first starting signal; the output module is connected with the first node, generates a current-stage grid driving signal according to the second clock signal and provides the current-stage grid driving signal at an output end; the pull-down module is connected with the first node, the output end and the low level signal end, and is used for pulling down the electric potential of the first node to a low level according to a second starting signal and pulling down the grid driving signal of the current stage to the low level according to a first clock signal; and the stabilizing module comprises a first capacitor and a second node, the first capacitor is connected between the first node and the second node, and the stabilizing module adjusts the voltage of the second node according to the first clock signal and the second clock signal so that the voltage difference between the first node and the output end is less than 0. The invention can be compatible with the thin film transistor using amorphous silicon and metal oxide materials, effectively solves the leakage current phenomenon of the grid drive circuit in the low-voltage stable stage, has stable circuit and simple circuit structure, and is beneficial to the realization of narrow frames.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
fig. 1 is a schematic circuit diagram of a gate driving unit;
FIG. 2 is a graph showing the relationship between the gate-source voltage and the drain current of a transistor;
fig. 3 is a block diagram illustrating a display device according to an embodiment of the present invention;
fig. 4 is a block diagram illustrating a structure of a gate driving unit according to an embodiment of the invention;
fig. 5 is a schematic circuit diagram of a gate driving unit according to an embodiment of the invention;
FIG. 6 is a timing diagram of signals of the gate driving unit in FIG. 5;
fig. 7 is a diagram illustrating simulation results of a gate driving circuit according to an embodiment of the invention;
fig. 8 is a schematic diagram illustrating a relationship between the present-stage gate driving signal and the potential of the first node in the gate driving unit in the low-voltage stable stage according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of a portion of the invention and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, shall fall within the scope of protection of the present invention.
It should be noted that the terms "first," "second," and the like in the description, the claims, and the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As used herein, an element, port, component or section "connected" to another element, port, component or section may be understood as a direct electrical connection, or may be understood as an indirect electrical connection with an intervening element. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention will be described in detail below with reference to the accompanying drawings. Fig. 3 is a block diagram illustrating a structure of a display device according to an embodiment of the present invention. As shown in fig. 3, in the present embodiment, the display device 100 includes a display panel 10, a timing control circuit 20, a source driving circuit 30, and a gate driving circuit 40.
The display panel 1 includes a plurality of data lines S1 to Sn, a plurality of gate lines G1 to Gm, and a plurality of pixels disposed at positions where the respective data lines and gate lines intersect. Any of the pixels includes a TFT (thin film transistor), a pixel electrode, and a common electrode for applying a common voltage Vcom disposed opposite to the pixel electrode. Wherein m and n are both natural numbers.
Further, the display panel 10 includes, but is not limited to: any one of a cathode ray tube display panel, a digital light processing display panel, a liquid crystal display panel, a light emitting diode display panel, an organic light emitting diode display panel, a quantum dot display panel, a Mirco-LED display panel, a Mini-LED display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, or an electrowetting display panel.
The timing control circuit 20 is respectively connected to the source driving circuit 30 and the gate driving circuit 40 to provide the source driving circuit 30 with a plurality of switching signals SWn and the gate driving circuit 40 with a start signal STV and a plurality of clock signals CLKm.
The source driving circuit 30 is coupled to the data lines S1 to Sn for providing gray scale data.
The gate driving circuit 40 includes a plurality of gate driving units connected in series, each gate driving unit is coupled to one gate line of the display panel 10 for providing a gate driving signal to sequentially drive a plurality of gate lines G1 to Gm on the display panel 10.
Further, when the plurality of data lines S1 to Sn are driven in a state where the gate lines G1 to Gm are activated, gray-scale voltages corresponding to pixel data are written in pixels connected to the activated plurality of gate lines G1 to Gm through the plurality of data lines S1 to Sn, and thus the pixels are driven, charging the pixels.
The gate driving circuit 40 includes N cascaded gate driving units as an example.
Referring to fig. 4, fig. 4 is a block diagram illustrating a gate driving unit according to an embodiment of the invention. As shown in fig. 4, the gate driving unit 400 includes: an input module 410, an output module 420, a pull-down module 430, and a stabilization module 440.
The output terminal of the input module 410 is connected to the first node Q, the input terminal of the input module 410 receives the first start signal Gn-1 and the first clock signal CLK1, and the input module 410 precharges the first node Q by the first start signal Gn-1 under the control of the first clock signal CLK 1.
The output module 420 is connected to the signal terminals of the first node Q and the second clock signal CLK2, and is configured to generate the present-stage gate driving signal Gn according to the voltage of the first node Q and the second clock signal CLK2, and provide the present-stage gate driving signal Gn at the output terminal of the present-stage gate driving unit, that is, the output module 420 outputs the received second clock signal CLK2 as the present-stage gate driving signal Gn under the control of the voltage of the first node.
The pull-down module 430 is connected to the first node Q, the output terminal of the present stage gate driving unit, the signal terminal of the low level signal VGL, the signal terminal of the first clock signal CLK1, and the signal terminal of the second start signal Gn +1, and is configured to pull down the potential of the first node Q to a low level, i.e., the level of the low level signal VGL, according to the received second start signal Gn +1, and pull down the present stage gate driving signal Gn to a low level, i.e., the level of the low level signal VGL, according to the first clock signal CLK 1.
The stabilizing module 440 includes a first capacitor C1 and a second node QB (not shown in fig. 4, please refer to fig. 5), the first capacitor C1 is connected between the first node Q and the second node QB, and the stabilizing module 440 adjusts a voltage of the second node QB according to the first clock signal CLK1 and the second clock signal CLK2, so that a voltage difference between the first node Q and the output terminal is less than 0. That is, the stabilizing module 440 makes the voltage of the first node Q lower than the level of the low level signal VGL through the coupling effect of the first capacitor C1 during the low voltage stabilizing period, so that the voltage difference between the first node Q and the output terminal is less than 0.
In one embodiment, the first start signal Gn-1 of the first stage gate driving unit in the gate driving circuit 40 is the first pulse signal STV1 provided outside the gate driving circuit, and the second start signal Gn +1 of the first stage gate driving unit is the gate driving signal G2 provided by the second stage gate driving unit, that is, when n is 1, that is, the first stage gate driving unit has no previous stage gate driving unit, and the first start signal Gn-1 thereof needs to be additionally set.
The first start signal Gn-1 of the last stage gate driving unit in the gate driving circuit is the gate driving signal Gn-1 provided by the previous stage gate driving unit, and the second start signal Gn +1 of the last stage gate driving unit is the second pulse signal STV2 provided outside the gate driving circuit, that is, when N is equal to N, that is, the last stage gate driving unit does not have a subsequent stage gate driving unit, the second start signal Gn +1 thereof needs to be additionally set.
The first starting signal of the nth stage gate driving unit in the gate driving circuit is a gate driving signal Gn-1 provided by the nth-1 stage gate driving unit, the second starting signal of the nth stage gate driving unit is a gate driving signal Gn +1 provided by the nth +1 stage gate driving unit, wherein 1 < N < N, and N is a positive integer.
Referring to fig. 5, fig. 5 is a schematic circuit diagram of a gate driving unit according to an embodiment of the invention. As shown in fig. 5, in one embodiment, the input module 410 includes: a first switch tube M1, a control terminal of the first switch tube M1 receives the first clock signal CLK1, a first path terminal of the first switch tube receives the first start signal Gn-1, and a second path terminal of the first switch tube is connected to the first node Q.
Note that, in describing the circuit connection method, the description is given by using the signals as they are, and for the sake of brevity, the signal terminals are not illustrated, for example, the signal terminal of the first clock signal CLK1, the signal terminal of the second clock signal CLK2, the signal terminal of the first start signal Gn-1, and the like.
In one embodiment, the output module 420 includes a second switch tube M2 and a second capacitor C2. The control terminal of the second switch M2 is connected to the first node Q, the first path terminal of the second switch M2 receives the second clock signal CLK2, and the second path terminal of the second switch M2 is connected to the output terminal. The second capacitor C2 is connected between the control terminal of the second switch M2 and the second path terminal of the second switch M2.
In one embodiment, the capacitance of the second capacitor C2 is greater than the capacitance of the first capacitor C1.
In an embodiment, the pull-down module 430 includes a third switching tube M3 and a fourth switching tube M4. The control terminal of the third switch M3 receives the first clock signal CLK1, the first path terminal of the third switch M3 is connected to the output terminal, and the second path terminal of the third switch M3 is connected to the low level signal terminal to receive the low level signal VGL. A control terminal of the fourth switching transistor M4 receives the second start signal Gn +1, a first pass terminal of the fourth switching transistor M4 is connected to the first node Q, and a second pass terminal of the fourth switching transistor M4 is connected to the low level signal terminal to receive the low level signal VGL.
In one embodiment, the stabilizing module 440 further includes a fifth switch tube M5 and a sixth switch tube M6. The control terminal of the fifth switch transistor M5 is connected to the first path terminal of the fifth switch transistor M5 and receives the first clock signal CLK1, and the second path terminal of the fifth switch transistor M5 is connected to the second node QB. The control terminal of the sixth switch M6 receives the second clock signal CLK2, the first path terminal of the sixth switch M6 is connected to the second node QB, and the second path terminal of the sixth switch M6 receives the first clock signal CLK 1.
In one embodiment, the switching transistor in the gate driving circuit is a metal oxide thin film transistor or an amorphous silicon thin film transistor.
Specifically, when the switching tube in the gate driving circuit 40 is a metal oxide thin film transistor or an amorphous silicon thin film transistor, the first path end of the switching tube is a drain, the second path end of the switching tube is a source, and the control end of the switching tube is a gate.
In one embodiment, the switch transistor in the gate driving circuit 40 is an N-type transistor.
Referring to fig. 6, fig. 6 is a timing diagram illustrating signals of the gate driving unit shown in fig. 5. Referring to fig. 5, the operation principle of the gate driving unit according to the embodiment of the present invention is described in detail by taking the nth stage gate driving unit (1 < N, N is a positive integer) in the gate driving circuit 40 as an example. The first start signal of the nth stage gate driving unit 400 in the gate driving circuit is the gate driving signal Gn-1 provided by the nth-1 stage gate driving unit, and the second start signal of the nth stage gate driving unit is the gate driving signal Gn +1 provided by the (n + 1) th stage gate driving unit. As shown in fig. 6, one duty cycle of the gate driving unit 400 includes four phases.
In the first stage, i.e., the section of (r) in the figure, the first clock signal CLK1 changes from low level to high level, the first switch tube M1 is turned on, the first switch tube M1 supplies the gate driving signal Gn-1 of the (n-1) th stage gate driving unit to the first node Q, the first node Q is pre-charged, and the potential of the first node Q changes from low level to high level. At the same time, the first clock signal CLK1 also turns on the third switching transistor M3, pulling the gate driving signal Gn down to the level state of the low level signal VGL. Meanwhile, it is worth mentioning that the fifth switch M5 is turned on under the control of the first clock signal CLK1, the first clock signal CLK1 charges the second node QB, and the coupling effect of the first capacitor C1 and the small size of the fifth switch M5 cannot timely transmit the coupled high level, so that the potential of the second node QB is slightly higher than the potential of the first node Q.
In the second stage, i.e. the range of —, in the figure, the second clock signal CLK2 changes from low level to high level, the first clock signal CLK1 changes from high level to low level, at this time, the second switch tube M2 is already turned on by the precharge in the first stage, the third switch tube M3 is turned off, when the second clock signal CLK2 changes from low level to high level, due to the bootstrap effect of the second capacitor C2, the potential of the first node Q is further pulled high, the second switch tube M2 is fully turned on, and the second clock signal CLK2 is output as the valid present-stage gate driving signal Gn through the second switch tube M2, i.e. is output as a high-level signal. Meanwhile, the second node QB is pulled low to a low level state due to the conduction of the sixth switch transistor M6, it should be noted that, since the second capacitor C2 is larger than the first capacitor C1, the capacitor of the first node Q is still pulled high by bootstrap.
In the third stage, namely, the third section in the figure, at this time, the first clock signal CLK1 changes from low level to high level, the second clock signal CLK2 changes from high level to low level, and the gate driving signal Gn +1 of the (n + 1) th stage gate driving unit is a high level signal, so that under the combined action of the second clock signal CLK2 and the gate driving signal Gn +1, the third switching tube M3 and the fourth switching tube M4 are turned on, and the potential of the gate driving signal Gn and the first node Q of the present stage is pulled down to the level state of the low level signal VGL. In addition, the second node QB is charged to the high state by the first clock signal CLK1 due to the conduction of the fifth switch M5.
In the fourth stage, i.e. the fourth interval in the figure, the first clock signal CLK1 and the second clock signal CLK2 work together, on one hand, it is ensured that the output of the present gate driving signal Gn is a low level signal, i.e. the third switching tube M3 is turned on when the first clock signal CLK1 is high, so that the present gate driving signal Gn is maintained at the potential of the low level signal VGL, on the other hand, by varying the voltage of the second node QB, i.e. coupling the first node Q through the second node QB, the potential of the first node Q is lower than the voltage of the low level signal VGL, so that when the first clock signal CLK1 is low, the gate-source voltage Vgs of the second switching tube M2 is less than 0, and the second switching tube M2 is turned off better, thereby effectively solving the leakage current phenomenon of the gate driving circuit in the low voltage stabilization stage and ensuring the stability of the circuit.
Specifically, in the first timing interval of the fourth stage, that is, when the first clock signal CLK1 is at a low level and the second clock signal CLK2 is at a high level, at this time, the third switching tube M3 and the fourth switching tube M4 are turned off to be in an off state, the first node Q is at a low level and in a floating state, the sixth switching tube M6 is turned on to pull down the potential of the second node QB, and further pull down the potential of the first node Q through the coupling effect of the first capacitor C1, so that the potential of the first node Q is lower than the potential of the low level signal VGL, that is, the gate voltage of the second switching tube M2 is lower than the source voltage, that is, Vgs < 0.
Referring to fig. 7 and 8, fig. 7 is a schematic diagram illustrating simulation results of a gate driving circuit according to an embodiment of the invention. Fig. 8 is a schematic diagram illustrating a relationship between the present-stage gate driving signal and the potential of the first node in the gate driving unit in the low-voltage stable stage according to an embodiment of the present invention. As shown in fig. 7, it can be seen that there is no obvious difference in the waveforms of the multi-stage gate driving signals output by the gate driving circuit, and the gate driving signal G167 of the 167 th stage gate driving unit in the figure is equivalent to the gate driving signal G1 of the first stage gate driving unit, and has a good stage transfer effect. As shown in fig. 8, during the turn-off period of the third switching transistor M3, the voltage of the first node Q is lower than the voltage of the output terminal (i.e., the output terminal of the gate driving signal Gn), i.e., the gate-source voltage Vgs < 0 of the second switching transistor M2.
To sum up, the gate driving circuit provided by the embodiment of the present invention includes a plurality of gate driving units connected in cascade, each gate driving unit is configured to drive a corresponding gate line on a display panel, and each gate driving unit includes: the input module is connected with the first node and charges the first node according to the first clock signal and the first starting signal; the output module is connected with the first node, generates a current-stage grid driving signal according to the second clock signal and provides the current-stage grid driving signal at an output end; the pull-down module is connected with the first node, the output end and the low level signal end, and is used for pulling down the electric potential of the first node to a low level according to a second starting signal and pulling down the grid driving signal of the current stage to the low level according to a first clock signal; and the stabilizing module comprises a first capacitor and a second node, the first capacitor is connected between the first node and the second node, and the stabilizing module regulates the voltage of the second node according to the first clock signal and the second clock signal so that the voltage difference between the first node and the output end is less than 0. The invention can compatibly use amorphous silicon and a metal oxide material thin film transistor, effectively solves the leakage current phenomenon of the grid drive circuit in the low-voltage stable stage, has stable circuit and simple circuit structure, and is beneficial to the realization of a narrow frame.
In order to achieve the above object, another aspect of the embodiments of the present invention provides a display device, which includes, as one embodiment:
a gate driving circuit, which is the gate driving circuit of any one of the above embodiments, for providing a plurality of gate driving signals;
the source electrode driving circuit is used for providing a plurality of gray scale data; and
the display panel comprises a plurality of pixel units arranged in an array, a plurality of gate lines and a plurality of data lines; wherein,
the display panel receives a plurality of gate driving signals through a plurality of gate lines to select a plurality of pixel units by rows, and receives a plurality of gray scale data through a plurality of data lines to provide the gray scale data to the selected pixel units to realize image display.
It should be noted that, for the parts of the display device that are not illustrated or described in detail, reference is made to the foregoing embodiments of the gate driving circuit for description, and details are not repeated here.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures.
Claims (9)
1. A gate driving circuit comprising a plurality of gate driving units connected in cascade, each gate driving unit for driving a corresponding gate line on a display panel, wherein each gate driving unit comprises:
the input module is connected with a first node and charges the first node according to a first clock signal and a first starting signal;
the output module is connected with the first node, generates a current-stage grid driving signal according to a second clock signal and provides the current-stage grid driving signal at an output end;
the pull-down module is connected with the first node, the output end and the low level signal end, and is used for pulling down the potential of the first node to a low level according to a second starting signal and pulling down the current-stage grid driving signal to a low level according to the first clock signal;
the stabilizing module comprises a first capacitor, a second node, a fifth switching tube and a sixth switching tube;
the control end of the fifth switching tube is connected with the first path end of the fifth switching tube and receives the first clock signal, and the second path end of the fifth switching tube is connected with the second node;
a control end of the sixth switching tube receives the second clock signal, a first path end of the sixth switching tube is connected with the second node, and a second path end of the sixth switching tube receives the first clock signal;
the first capacitor is connected between the first node and the second node, and the stabilizing module adjusts the voltage of the second node according to the first clock signal and the second clock signal, so that the voltage difference between the first node and the output end is smaller than 0.
2. The gate driving circuit according to claim 1, wherein the gate driving circuit comprises N cascaded gate driving units, a first start signal of a first stage gate driving unit in the gate driving circuit is a first pulse signal provided outside the gate driving circuit, and a second start signal of the first stage gate driving unit is a gate driving signal provided by a second stage gate driving unit;
a first start signal of a last stage gate driving unit in the gate driving circuit is a gate driving signal provided by a previous stage gate driving unit, and a second start signal of the last stage gate driving unit is a second pulse signal provided outside the gate driving circuit;
the first starting signal of the nth level gate driving unit in the gate driving circuit is a gate driving signal provided by the (N-1) th level gate driving unit, the second starting signal of the nth level gate driving unit is a gate driving signal provided by the (N + 1) th level gate driving unit, wherein N is more than 1 and less than N, and N is a positive integer.
3. A gate drive circuit as claimed in claim 1, wherein the input module comprises: a control end of the first switch tube receives the first clock signal, a first path end of the first switch tube receives the first start signal, and a second path end of the first switch tube is connected with the first node.
4. A gate drive circuit as claimed in claim 1, wherein the output module comprises:
a control end of the second switching tube is connected with the first node, a first path end of the second switching tube receives the second clock signal, and a second path end of the second switching tube is connected with the output end;
and the second capacitor is connected between the control end of the second switch tube and the second path end of the second switch tube.
5. A gate drive circuit as claimed in claim 4, wherein the capacitance of the second capacitor is greater than the capacitance of the first capacitor.
6. The gate drive circuit of claim 1, wherein the pull-down module comprises:
a control end of the third switch tube receives the first clock signal, a first pass end of the third switch tube is connected with the output end, and a second pass end of the third switch tube is connected with the low-level signal end;
and the control end of the fourth switch tube receives the second starting signal, the first path end of the fourth switch tube is connected with the first node, and the second path end of the fourth switch tube is connected with the low-level signal end.
7. The gate driving circuit according to claim 1, wherein the switching transistor in the gate driving circuit is a metal oxide thin film transistor or an amorphous silicon thin film transistor.
8. The gate driving circuit according to claim 1, wherein the switching tube in the gate driving circuit is an N-type transistor.
9. A display device, comprising:
a gate drive circuit as claimed in any one of claims 1 to 8 for providing a plurality of gate drive signals;
a source driver circuit for providing a plurality of gray scale data; and
a display panel including a plurality of pixel units arranged in an array, and a plurality of gate lines and a plurality of data lines; wherein,
the display panel receives the plurality of gate driving signals through the plurality of gate lines to select the plurality of pixel units by rows, and receives the plurality of gray scale data through the plurality of data lines by columns to provide the selected pixel units with image display.
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