CN113644631A - Processing method for half bus short circuit - Google Patents
Processing method for half bus short circuit Download PDFInfo
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- CN113644631A CN113644631A CN202111094590.5A CN202111094590A CN113644631A CN 113644631 A CN113644631 A CN 113644631A CN 202111094590 A CN202111094590 A CN 202111094590A CN 113644631 A CN113644631 A CN 113644631A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
- H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
- H02H7/122—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for inverters, i.e. dc/ac converters
- H02H7/1227—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for inverters, i.e. dc/ac converters responsive to abnormalities in the output circuit, e.g. short circuit
Abstract
The invention relates to the technical field of inverters, and discloses a half-bus short circuit processing method which is characterized in that the half-bus short circuit processing method is applied to a three-phase photovoltaic inverter circuit, a control circuit is arranged in the three-phase photovoltaic inverter circuit, whether the judgment is carried out through whether U1 or U2 is larger than Um or not is carried out, whether a short circuit situation occurs from a positive bus to a neutral point through V1, V3 and V4 or from a negative bus to a neutral point through V2, V3 and V4 is judged, the relay is normally closed in a normal working state, and when the short circuit situation occurs, the relay is disconnected, a capacitor C2, a capacitor C3, a capacitor C4 and a capacitor C5 are protected to prevent the situations of overvoltage, damage, fire and the like from occurring, a fault alarm is sent according to different values of U1 or U2, and fault isolation measures are taken.
Description
Technical Field
The invention relates to the technical field of inverters, in particular to a method for processing half-bus short circuit.
Background
The photovoltaic inverter is an inverter capable of converting variable direct-current voltage generated by a photovoltaic solar panel into alternating current with commercial power frequency, and can be fed back to a commercial power transmission system or used for an off-grid power grid;
photovoltaic inverter is in the use, and the switch tube in its inverter circuit need bear high pressure and frequent switch, and is ageing comparatively easily, and when the switch tube became invalid, it will be in and continuously switched on the state probably, causes the short circuit phenomenon, leads to whole circuit to damage.
Disclosure of Invention
In view of the defects in the prior art, the invention aims to provide a method for processing half-bus short circuit, which is used for preventing the circuit damage and deterioration caused by the failure of a switch tube.
In order to achieve the purpose, the invention provides the following technical scheme: a half-bus short circuit processing method is applied to a three-phase photovoltaic inverter circuit, a control circuit is arranged in the three-phase photovoltaic inverter circuit, and the method comprises the following sampling steps: the method comprises the steps that a first detection unit is controlled to collect the voltage U1 of a first group of bus capacitors in a three-phase photovoltaic inverter circuit, and a second detection unit is controlled to collect the voltage U2 of a second group of bus capacitors in the three-phase photovoltaic inverter circuit;
the control steps are as follows: a threshold voltage Um is preset in the control circuit, and when the U1 or the U2 is larger than the Um, the control circuit controls the neutral line to be disconnected.
As a further improvement of the present invention, the three-phase photovoltaic inverter circuit includes a three-level inverter circuit and a Boost circuit, the first group of bus capacitors and the second group of bus capacitors are both located in the Boost circuit and are serially connected, the three-level inverter circuit includes a first bridge arm, a second bridge arm and a third bridge arm, the second bridge arm is connected with an output end of the Boost circuit to form a positive bus, the third bridge arm is connected with an input end of the Boost circuit to form a negative bus, the first group of bus capacitors and the second group of bus capacitors are connected with the first bridge arm to form a neutral line, and the control circuit includes a relay, and the relay is located on the neutral line.
As a further improvement of the present invention, the control circuit includes a first detection point, a second detection point and a third detection point, the first detection unit is formed between the first detection point and the second detection point, the second detection unit is formed between the second detection point and the third detection point, the first detection point is located on the positive bus, the second detection point is located on the neutral line, and the third detection point is located on the negative bus.
As a further improvement of the present invention, the first bridge arm includes a first switching tube and a second switching tube connected in series, the second bridge arm includes a third switching tube, and the third bridge arm includes a fourth switching tube, and the processing method further includes a signal sending step: when the relay is disconnected, the first detection unit or/and the second detection unit sends a fault signal, and the three-level inverter circuit closes the first switch tube, the second switch tube, the third switch tube and the fourth switch tube according to the fault signal.
As a further development of the invention, the Um is greater than 0.5 times the bus voltage and ranges from 0.6 to 0.8 times the bus voltage.
As a further improvement of the invention, the method also comprises the following fault isolation steps: and the central console receives the fault signal and displays a fault isolation scheme according to the fault signal.
As a further improvement of the present invention, a control module is disposed in the console, the control module includes a maintenance unit and an execution unit, a fault isolation table is configured in the maintenance unit, a differential pressure and a fault isolation policy corresponding to the differential pressure are recorded in the fault isolation table, the execution unit receives the values of the U1 and the U2, and the fault isolation table uses the values of the U1 or/and the U2 as an index, executes the fault isolation policy under the corresponding differential pressure, issues a fault alarm, and displays the fault alarm on the console.
As a further development of the invention, the pressure difference comprises a first difference and a second difference, the fault isolation strategy comprises a first strategy and a second strategy, the first difference corresponds to the first strategy and the second difference corresponds to the second strategy, and the execution unit compares the U1 with the first difference and the U2 with the second difference.
As a further improvement of the present invention, the fault isolation table records a first flag value, a second flag value, a third flag value and a third policy, the third flag value corresponds to the third policy, the first flag value corresponds to the first policy, the second flag value corresponds to the second policy, and if both U1 and U2 are greater than Um, the fault isolation table uses the sum of the first flag value and the second flag value as an index and executes the corresponding third policy under the third flag value.
The invention has the beneficial effects that: in the invention, whether U1 or U2 is larger than Um is judged, whether a short circuit condition occurs from a positive bus passing V1 and V3, and from V4 to a neutral point or from a negative bus passing V2 and V3, and from V4 to the neutral point is judged, if U1 is larger than Um, a short circuit between V1 and V3 is determined, if U2 is larger than Um, a short circuit between V4 and V3 is determined, in a normal working state, a relay is normally closed, when the short circuit condition occurs, the relay is opened, a capacitor C2, a capacitor C3, a capacitor C4 and a capacitor C5 are protected to prevent the situations of overvoltage, damage, fire and the like from occurring, and according to different values of U1 or U2, a fault warning is sent out, and a fault isolation measure is taken.
Drawings
FIG. 1 is a circuit diagram of a three-phase photovoltaic inverter circuit of the present invention;
fig. 2 is a block flow diagram of the present invention.
Reference numerals: 1. a first set of bus capacitors; 2. and a second set of bus capacitors.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. In which like parts are designated by like reference numerals. It should be noted that the terms "front," "back," "left," "right," "upper" and "lower" used in the following description refer to directions in the drawings, and the terms "bottom" and "top," "inner" and "outer" refer to directions toward and away from, respectively, the geometric center of a particular component.
Referring to fig. 1, the method for processing a half-bus short circuit according to the embodiment includes applying the method to a three-phase photovoltaic inverter circuit, where a control circuit is disposed in the three-phase photovoltaic inverter circuit, and includes: the control circuit controls the first detection unit to collect the voltage U1 of a first group of bus capacitors 1 in the three-phase photovoltaic inverter circuit, and controls the second detection unit to collect the voltage U2 of a second group of bus capacitors 2 in the three-phase photovoltaic inverter circuit; the control steps are as follows: a threshold voltage Um is preset in the control circuit, and when U1 or U2 is larger than Um, the control circuit controls the neutral line to be disconnected. The three-phase photovoltaic inverter circuit comprises a three-level inverter circuit and a Boost circuit, wherein a first group of bus capacitors 1 and a second group of bus capacitors 2 are both positioned in the Boost circuit and are arranged in series, a series point between the first group of bus capacitors 1 and the second group of bus capacitors 2 is a neutral point, and the Boost circuit is a Boost circuit and can enable output voltage to be higher than input voltage; the first group of bus capacitors 1 comprises a capacitor C2 and a capacitor C3 which are connected in parallel, the second group of bus capacitors 2 comprises a capacitor C4 and a capacitor C5 which are connected in parallel, V3 is a first switching tube, V2 is a second switching tube, V3 is a third switching tube, V4 is a fourth switching tube, the three-level inverter circuit comprises a first bridge arm, a second bridge arm and a third bridge arm, the second bridge arm is connected with the output end of the Boost circuit to form a positive bus, the third bridge arm is connected with the input end of the Boost circuit to form a negative bus, the first group of bus capacitors 1 and the second group of bus capacitors 2 are connected with the first bridge arm to form a neutral line, the control circuit comprises a relay which is positioned on the neutral line, so that the relay does not influence the work of the first group of bus capacitors 1, the second group of bus capacitors 2, the first bridge arm, the second bridge arm and the third bridge arm in a normally closed state, and has a simple structure, whether U1 or U2 is larger than Um is judged, whether a short circuit condition occurs between a positive bus passing V1 and V3 and between a positive bus passing V4 and a neutral point or between a negative bus passing V2 and V3 and between a negative bus passing V4 and a neutral point is judged, if U1 is larger than Um, the positive bus is determined to be short-circuited between V1 and V3 and between V4 and the neutral point, if U2 is larger than Um, the negative bus is determined to be short-circuited between V2 and V3 and between V4 and the neutral point, half-bus short circuit conditions are formed, in a normal working state, the relay is normally closed, when the short circuit condition occurs, the relay is disconnected, the capacitor C2, the capacitor C3, the capacitor C4 and the capacitor C5 are protected from overvoltage, damage and fire and the like are prevented, the control circuit comprises a first detection point, a second detection point and a third detection point, a first detection unit is formed between the first detection point and a second detection point, the first detection point is located on the positive bus, the second detection point is located on the neutral line, and the third detection point is located on the negative bus, so that the voltage between the first detection point and the second detection point is ensured to be the voltage of the first group of bus capacitors 1, and the voltage between the second detection point and the third detection point is ensured to be the voltage of the second group of bus capacitors 2.
Referring to fig. 1, the first bridge arm includes a first switching tube and a second switching tube connected in series, the second bridge arm includes a third switching tube, the third bridge arm includes a fourth switching tube, and the processing method further includes a signal sending step: when the relay is disconnected, the first detection unit or/and the second detection unit sends a fault signal, the three-level inverter circuit closes the first switch tube, the second switch tube, the third switch tube and the fourth switch tube according to the fault signal, and when a short circuit condition between V1 and V3 or between V3 and V4 occurs, V1, V2, V3 and V4 are closed, so that the safety of the control circuit and the relay can be ensured, and the control circuit and the relay are prevented from being damaged.
Um is greater than 0.5 times the bus voltage and ranges from 0.6 to 0.8 times the bus voltage. Since the capacitance parameters of the C2, the C3, the C4 and the C5 may change after long-term use, so that the voltage of the capacitors is unbalanced, the Um is set to be more than one half of the bus voltage, a fluctuation range is given, and the reason that the overvoltage of the U1 and the U2 is caused by short circuit of V1 and V4 or short circuit of V2 and V3 is ensured.
The method also comprises the following fault isolation steps: the central console receives the fault signal, displays the fault isolation scheme according to the fault signal, provides the fault isolation scheme, prevents the fault from further expanding, and is convenient for maintenance personnel to maintain, the central console is provided with a screen which can display a first strategy, a second strategy and a third strategy on the screen, a control module is arranged in the central console, the control module comprises a maintenance unit and an execution unit, a fault isolation table is arranged in the maintenance unit, a differential pressure and a fault isolation strategy corresponding to the differential pressure are recorded in the fault isolation table, the execution unit receives values of U1 and U2, the fault isolation table takes the values of U1 or/and U2 as indexes to execute the fault isolation strategy under the corresponding differential pressure, different fault isolation strategies correspond to different fault isolation and maintenance modes, and different fault isolation modes are performed on the circuit according to different values of U1 or U2, make maintainer can more audio-visual understanding problem place and isolation mode to quick completion is overhauld, and the damage degree that different pressure differentials caused components and parts such as electric capacity is different, can work out optimal isolation and maintenance scheme, and can keep track of the total scheme after isolation and maintenance, so that follow-up looks over.
The differential pressure comprises a first differential value and a second differential value, the fault isolation strategy comprises a first strategy and a second strategy, the first differential value corresponds to the first strategy, the second differential value corresponds to the second strategy, the execution unit compares the U1 with the first differential value and compares the U2 with the second differential value, different strategies are selected for isolation according to overvoltage of the first group of bus capacitors 1 or overvoltage of the second group of bus capacitors 2, the isolation and maintenance scheme can be more accurate in solving the problem, and the range of the isolation and maintenance scheme is reduced.
The fault isolation table is recorded with a first mark value, a second mark value, a third mark value and a third strategy, the third mark value corresponds to the third strategy, the first mark value corresponds to the first strategy, the second mark value corresponds to the second strategy, if both U1 and U2 are greater than Um, the fault isolation table takes the sum of the first mark value and the second mark value as an index, and executes the third strategy corresponding to the third mark value, under the condition that both the first group bus capacitor 1 and the second group bus capacitor 2 are overvoltage, namely both U1 and U2 are greater than Um, a short circuit condition between V1 and V4 is generated, under the condition, fixed isolation and maintenance are carried out by setting an additional third strategy, different conditions of overvoltage are refined, and the fault isolation and maintenance modes are more accurate.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (9)
1. A half-bus short circuit processing method is applied to a three-phase photovoltaic inverter circuit, a control circuit is arranged in the three-phase photovoltaic inverter circuit, and the method is characterized in that: the method comprises the following steps: the method comprises the steps that a first detection unit is controlled to collect the voltage U1 of a first group of bus capacitors (1) in a three-phase photovoltaic inverter circuit, and a second detection unit is controlled to collect the voltage U2 of a second group of bus capacitors (2) in the three-phase photovoltaic inverter circuit;
the control steps are as follows: a threshold voltage Um is preset in the control circuit, and when the U1 or the U2 is larger than the Um, the control circuit controls the neutral line to be disconnected.
2. The method for processing the half bus short circuit according to claim 1, wherein: the three-phase photovoltaic inverter circuit comprises a three-level inverter circuit and a Boost circuit, wherein a first group of bus capacitors and a second group of bus capacitors are arranged in the Boost circuit and are connected in series, the three-level inverter circuit comprises a first bridge arm, a second bridge arm and a third bridge arm, the second bridge arm is connected with the output end of the Boost circuit to form a positive bus, the third bridge arm is connected with the input end of the Boost circuit to form a negative bus, the first group of bus capacitors (1) and the second group of bus capacitors (2) are connected with the first bridge arm to form a neutral line, the control circuit comprises a relay, and the relay is positioned on the neutral line.
3. The method for processing the half bus short circuit according to claim 2, wherein: the control circuit comprises a first detection point, a second detection point and a third detection point, wherein a first detection unit is formed between the first detection point and the second detection point, a second detection unit is formed between the second detection point and the third detection point, the first detection point is positioned on the positive bus, the second detection point is positioned on the neutral line, and the third detection point is positioned on the negative bus.
4. The method for processing the half bus short circuit according to claim 2, wherein: the first bridge arm comprises a first switching tube and a second switching tube which are connected in series, the second bridge arm comprises a third switching tube, the third bridge arm comprises a fourth switching tube, and the processing method further comprises the step of sending signals: when the relay is disconnected, the first detection unit or/and the second detection unit sends a fault signal, and the three-level inverter circuit closes the first switch tube, the second switch tube, the third switch tube and the fourth switch tube according to the fault signal.
5. The method for processing the half bus short circuit according to claim 4, wherein: the Um is greater than 0.5 times the bus voltage and ranges from 0.6 to 0.8 times the bus voltage.
6. The method for processing the half bus short circuit according to claim 4, wherein: the method also comprises the following fault isolation steps: and the central console receives the fault signal and displays a fault isolation scheme according to the fault signal.
7. The method for processing the half bus short circuit according to claim 6, wherein: the central control console is internally provided with a control module, the control module comprises an overhaul unit and an execution unit, a fault isolation table is configured in the overhaul unit, the fault isolation table is internally recorded with pressure difference and fault isolation strategies corresponding to the pressure difference, the execution unit receives the U1 and the U2 values, the fault isolation table takes the U1 or/and the U2 values as indexes, executes the corresponding fault isolation strategies under the pressure difference, sends out fault alarms and displays the fault alarms on the central control console.
8. The method for processing the half bus short circuit according to claim 7, wherein: the differential pressure comprises a first difference value and a second difference value, the fault isolation strategy comprises a first strategy and a second strategy, the first difference value corresponds to the first strategy, the second difference value corresponds to the second strategy, and the execution unit compares the U1 with the first difference value and compares the U2 with the second difference value.
9. The method for processing the half bus short circuit according to claim 8, wherein: the fault isolation table records a first flag value, a second flag value, a third flag value and a third policy, the third flag value corresponds to the third policy, the first flag value corresponds to the first policy, the second flag value corresponds to the second policy, if both U1 and U2 are greater than Um, the fault isolation table uses the sum of the first flag value and the second flag value as an index, and executes the corresponding third policy under the third flag value.
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| CN113644631B (en) | 2022-04-26 |
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