CN113644139A

CN113644139A - Chip packaging structure, electronic equipment and preparation method of chip packaging structure

Info

Publication number: CN113644139A
Application number: CN202010327845.7A
Authority: CN
Inventors: 贾文平; 吴冰; 潘平; 魏文雄
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-04-23
Filing date: 2020-04-23
Publication date: 2021-11-12

Abstract

The application provides a chip packaging structure, electronic equipment and a preparation method of the chip packaging structure, and relates to the technical field of semiconductors. The chip packaging structure comprises a bare chip and a base body, wherein the bare chip is embedded into the base body. Wherein: a die is embedded within the base, the die having a first electrode assembly and a second electrode assembly. The first electrode assembly is provided with a first interface, the second electrode assembly is provided with a second interface, and the first interface and the second interface are positioned on the same surface of the base body and are used for being connected with external equipment. In addition, interfaces of all electrode assemblies of the bare chip are arranged on the surface of the same side of the base body, so that the occupied area of the chip packaging structure is small, and the thinning and miniaturization design of the chip packaging structure is facilitated.

Description

Chip packaging structure, electronic equipment and preparation method of chip packaging structure

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a chip package structure, an electronic device, and a method for manufacturing the chip package structure.

Background

Due to the need for human-computer interaction, a large number of sensors are typically used in electronic devices. In recent years, the development of electronic devices is changing day by day, and the market demand is large, which promotes the rapid development of sensor devices. In addition, as people pay more and more attention to their health conditions and their family health conditions, the measurement of heart rate and blood oxygen is also very important. Currently, heart rate detection sensors and blood oxygen detection sensors have become indispensable parts of electronic devices.

The detection of heart rate and blood oxygen is usually achieved by a scheme of photoplethysmography (PPG). The PPG scheme is a non-invasive detection method for detecting blood volume change in living body tissues by utilizing a PPG sensor and a photoelectric means. When a light beam with a certain wavelength emitted by a light emitting device of the PPG sensor irradiates the skin surface, the light beam is transmitted to a photoelectric receiver of the PPG sensor in a transmission or reflection mode.

At present, the electronic equipment has higher and higher requirements on miniaturization and thinning design, and the miniaturization and thinning design of various sensors is realized, so that the volume of the electronic equipment can be effectively reduced. The volume of the chip package structure has a great influence on the volume of the sensor, and therefore how to implement the miniaturization and thinning design of the chip package structure becomes a technical problem to be solved in the field.

Disclosure of Invention

The application provides a chip packaging structure to realize the miniaturized design of the chip packaging structure.

In a first aspect, the present application provides a chip package structure that may include a die and a substrate, wherein the die is embedded within the substrate, and the die has a first electrode assembly and a second electrode assembly. The first electrode assembly is provided with a first interface, the second electrode assembly is provided with a second interface, and the first interface and the second interface are positioned on the same surface of the base body and are used for being connected with external equipment. Adopt the chip package structure of this application, can effectually avoid the thickness of bare chip to cause the influence to chip package structure's whole thickness, in addition, set up the interface of each electrode subassembly with the bare chip in the same one side surface of base member, also can make chip package structure account for the face board design less to be favorable to realizing chip package structure's slimming, miniaturized design.

In one possible implementation, in particular disposing the first electrode assembly, the first electrode assembly includes a first electrode and a first electrode line electrically connected; correspondingly, the second electrode assembly may include a second electrode and a second electrode line electrically connected. The first electrode and the second electrode are respectively arranged on two end faces of the bare chip, the two end faces are oppositely arranged, and at least one of the two end faces the first surface of the base body.

When the first electrode and the second electrode are respectively led out to the same surface of the substrate through the first electrode line and the second electrode line, the specific arrangement mode of the first electrode line and the second electrode line needs to be considered. In one possible implementation manner, the first electrode line may include, but is not limited to, a first redistribution layer and a connection line, the first redistribution layer is disposed on the first surface of the substrate, the connection line penetrates through the substrate, the first electrode is electrically connected to the connection line through the first redistribution layer, and the first interface is disposed at an end of the connection line away from the first redistribution layer; the second electrode wire comprises a second rewiring layer arranged on the second surface of the base body, and one end, far away from the second electrode, of the second rewiring layer serves as a second interface. The mode that the adoption runs through the base member utilizes the electrode line to draw forth the electrode, can effectually reduce the electrode line and set up the area on the base member surface to be favorable to realizing chip package structure's miniaturized design.

In a possible implementation manner, when the connection line is specifically provided, the connection line may be, but is not limited to, a through hole opened in the substrate, and the through hole may be provided with a conductive material therein to meet the requirement of electrical connection. In addition, the connection line may be a bonding line provided through the base, and the bonding line may be used for electrical connection with the first rewiring layer.

In one possible implementation, the first electrode line may further include a third redistribution layer disposed on the second surface of the base, the third redistribution layer being electrically connected to the connection line. By providing the third rewiring layer, the first electrode can be further led out to the surface of the base, and thus the first interface can be provided in the third rewiring layer so as to connect the first interface to an external device.

In one possible implementation manner, the chip packaging structure further includes a protection layer covering the first redistribution layer, the second redistribution layer and the triple wiring layer. To achieve protection for the respective electrode lines.

In addition, the chip packaging structure further comprises a first lead connected with the second re-wiring, and a second lead connected with the third re-wiring, wherein the first lead and the second lead extend to the surface of the side, far away from the base, of the protective layer. Through setting up first lead and second lead, can further draw forth the surface to the protective layer with first electrode and second electrode, can make first lead and second lead as the interface of being connected with the external equipment electricity like this, it is favorable to improving the stability of electric connection.

In a possible implementation manner, a pad may be further disposed at each of the first interface and the second interface, and a solder layer may be further coated on the pad to improve the reliability of the connection between the die of the chip packaging structure and the external device.

In one possible implementation, the chip package structure includes two dies, namely a light emitting device die and a photoelectric receiver die, and a light emitting surface of the light emitting device die and a light receiving surface of the photoelectric receiver die are arranged towards the first surface of the substrate.

In order to avoid crosstalk between light emitted by the light emitting device bare chip and light received by the photoelectric receiver bare chip, a light retaining wall can be arranged on the first surface of the base body, and the light retaining wall is arranged between the light emitting device bare chip and the photoelectric receiver bare chip. In addition, the light blocking wall can be made of but not limited to black glue or light-shielding materials such as liquid crystal high molecular polymer.

In one possible implementation, a window may be opened on the substrate to expose the light emitting surface of the light emitting device die and the light receiving surface of the photoreceiver die, so as to reduce the loss of light.

In a second aspect, the present application further provides an electronic device, which includes a printed circuit board, and the chip package structure of the first aspect, which is electrically connected to the printed circuit board. Because the chip packaging structure has small volume, when the chip packaging structure is applied to electronic equipment, the miniaturization and thinning design of the electronic equipment can be favorably realized.

In a third aspect, the present application further provides a method for manufacturing a chip package structure, where the method includes:

bonding a bare chip on a first supporting plate, wherein the end face of the bare chip, provided with a first electrode, is attached to the supporting plate;

forming a matrix around the die such that the die is embedded in the matrix;

forming a through substrate through hole on the substrate on the periphery side of the bare chip;

forming a first rewiring layer and a second rewiring layer on the surface of the base body far away from the first supporting plate, wherein the first rewiring layer is electrically connected with the through hole, and the second rewiring layer is electrically connected with the second electrode of the bare chip;

forming a first protective layer on the first rewiring layer and the second rewiring layer;

bonding a second supporting plate on the first protective layer, and stripping the first supporting plate;

forming a third redistribution layer on a surface of the base body away from the second support plate, the third redistribution layer electrically connecting the first electrode with the through hole;

a second protective layer is formed on the third redistribution layer.

According to the preparation method of the embodiment of the application, the bare chip is embedded into the base body, the first electrode and the second electrode of the bare chip are respectively provided with the through holes through the base body, the two opposite surfaces of the base body are respectively provided with the rewiring layers, so that the first electrode and the second electrode are led to the same side of the base body, and the first interface and the second interface for connecting the bare chip with external equipment such as a printed circuit board are formed. In addition, each electrode of the bare chip is led out in a mode of being connected with the through hole penetrating through the base body, so that the occupied area of the chip packaging structure is small, and the thin and small design of the chip packaging structure is facilitated.

In one possible implementation, a matrix is formed around the die such that the die is embedded in the matrix, after which the method further comprises: and grinding the base body to expose the second electrode of the bare chip, wherein the second electrode is arranged on the surface of the base body far away from the first supporting plate. The second electrode of the bare chip is exposed by adopting a grinding mode, and meanwhile, the base body can be thinned, so that the thickness of the whole chip packaging structure is smaller.

In one possible implementation, when the through-substrate via is formed on the substrate on the periphery side of the die, the preparation method further includes: and forming a through hole for exposing the second electrode of the bare chip on the substrate, wherein the second electrode is arranged on the end surface of the substrate far away from the first supporting plate. The second electrode is exposed in a through hole punching mode, so that the second electrode can be effectively prevented from being damaged.

In one possible implementation, after the first redistribution layer and the second redistribution layer are formed on the surface of the substrate away from the first support plate, the preparation method further includes: one pad is formed at each of the first and second redistribution layers. The pad can be used for electrical connection with an external device such as a printed circuit board.

In one possible implementation, the number of the dies is two, that is, a light emitting device die and a photoreceiver die, and a light emitting surface of the light emitting device die and a light receiving surface of the photoreceiver die are located on one side of the substrate for forming the third redistribution layer, and the method further includes: and opening windows on the second protective layer to expose the light-emitting surface of the light-emitting device bare chip and the light-receiving surface of the photoelectric receiver bare chip so as to reduce the loss of light.

In addition, in order to prevent crosstalk between light emitted by the light emitting device bare chip and light received by the photoelectric receiver bare chip, the method may further include forming a light blocking wall on the second protective layer, the light blocking wall being disposed between the light emitting device bare chip and the photoelectric receiver bare chip.

In a fourth aspect, the present application further provides a method for manufacturing a chip package structure, where the method includes:

forming a metal layer on the first support plate;

forming a first bonding wire on the metal layer, forming a second bonding wire on a second electrode of the bare chip, wherein the first bonding wire and the second bonding wire are both arranged perpendicular to the first supporting plate, and the second electrode is arranged on the end face of the bare chip far away from the first supporting plate;

forming a substrate around the die, the first bonding wire and the second bonding wire so that the die, the first bonding wire and the second bonding wire are embedded into the substrate;

grinding the substrate to expose the first bonding wire and the second bonding wire;

forming a first rewiring layer and a second rewiring layer on the surface of the base body, which is far away from the first supporting plate, wherein the first rewiring layer is electrically connected with the first bonding wire, and the second rewiring layer is electrically connected with the second bonding wire;

forming a third redistribution layer on an end face of the base body far away from the second support plate, wherein the third redistribution layer electrically connects the first electrode with the first bonding wire;

a second protective layer is formed on the third redistribution layer.

According to the preparation method of the embodiment of the application, the bare chip is embedded into the base body, the first electrode and the second electrode of the bare chip are respectively arranged on the base body through the bonding wires, the rewiring layers are respectively arranged on the two opposite surfaces of the base body, so that the first electrode and the second electrode are led to the same side of the base body, and the first interface and the second interface for connecting the bare chip with external equipment such as a printed circuit board are formed. In addition, each electrode of the bare chip is led out in a mode of being connected with a bonding wire penetrating through the base body, so that the occupied area of the chip packaging structure is small, and the thin and small design of the chip packaging structure is facilitated.

In a fifth aspect, the present application further provides a chip package structure, which includes a die and a substrate. The base body can comprise a rigid substrate, and the rigid substrate is provided with a containing groove so that the bare chip can be contained in the containing groove. The bare chip comprises a first electrode assembly and a second electrode assembly, wherein the first electrode assembly is provided with a first interface; and the second electrode assembly is provided with a second interface, and the first interface and the second interface are positioned on the first surface of the base body. Adopt the chip package structure of this application, can effectually avoid the thickness of bare chip to cause the influence to chip package structure's whole thickness, in addition, set up the interface of each electrode subassembly with the bare chip in the same one side surface of base member, also can make chip package structure account for the face board design less to be favorable to realizing chip package structure's slimming, miniaturized design.

In one possible implementation manner, a gap may exist between the bare chip and the wall of the accommodating groove, and the gap may be greater than or equal to 50 μm, so as to prevent the bare chip from being damaged by the wall of the accommodating groove when the bare chip is accommodated in the accommodating groove.

In a possible implementation manner, when the substrate is specifically disposed, the substrate may further include a filling layer, the filling layer is disposed on the rigid substrate, and fills a gap between the bare chip and a groove wall of the accommodating groove, so as to limit and fix the bare chip.

In one possible implementation, when the first electrode assembly is specifically provided, the first electrode assembly may include a first electrode and a first electrode line that are electrically connected; similarly, when the second electrode assembly is specifically provided, the second electrode assembly may include a second electrode and a second electrode line that are electrically connected; the first electrode and the second electrode are respectively arranged on two opposite end faces of the bare chip, and at least one of the two end faces is arranged towards the first surface of the base body.

When the first electrode and the second electrode are respectively led out to the same surface of the substrate through the first electrode line and the second electrode line, the specific arrangement mode of the first electrode line and the second electrode line needs to be considered. In one possible implementation manner, the first electrode line includes a redistribution layer, a through hole and a first pad, the redistribution layer is disposed on the first surface of the base, the through hole penetrates through the base, and the first electrode is electrically connected to the through hole through the redistribution layer; the first bonding pad is arranged on the second surface of the base body and is electrically connected with the through hole. In some embodiments, the first surface and the second surface of the rigid substrate are further provided with circuit traces, and in this case, the redistribution layer of the first electrode line and the first pad may be electrically connected to the through hole through the circuit trace on the corresponding surface of the rigid substrate.

In addition, when the second electrode line is specifically provided, the second electrode line has a second pad provided on the second surface of the base, and the second pad is electrically connected to the second electrode. In this application embodiment, the mode that the adoption runs through the base member is utilized the electrode line to draw forth the electrode, can effectually reduce the electrode line and set up the area on the base member surface to be favorable to realizing chip package structure's miniaturized design.

In a possible implementation manner, the chip packaging structure further includes a protection layer covering the first surface and the second surface of the substrate, and the protection layer covers the redistribution layer and exposes the first pad and the second pad to protect the electrode lines.

In a sixth aspect, the present application further provides an electronic device, which includes a printed circuit board, and the chip package structure of the fifth aspect, which is electrically connected to the printed circuit board. Because the chip packaging structure has small volume, when the chip packaging structure is applied to electronic equipment, the miniaturization and thinning design of the electronic equipment can be favorably realized.

In a seventh aspect, the present application further provides a method for manufacturing a chip package structure, where the method includes:

forming a containing groove on the hard substrate, and respectively forming circuit wiring on the first surface and the second surface of the hard substrate;

adhering an adhesive layer on the first surface of the rigid substrate, accommodating the bare chip in the accommodating groove, and adhering the end face of the bare chip, provided with the first electrode, to the adhesive layer;

bonding the filling layer on the substrate, and limiting and fixing the bare chip;

removing the adhesive layer on the rigid substrate;

forming a first via hole and a second via hole on the filling layer, wherein the first via hole exposes the circuit trace on the second surface of the rigid substrate, and the second via hole exposes the second electrode of the bare chip;

forming electroplated layers in the first via hole and the second via hole, and forming a first pad and a second pad on the surface of the filling layer, wherein the first pad is electrically connected with the first via hole, and the second pad is electrically connected with the second via hole;

forming a rewiring layer on the first surface of the rigid substrate, wherein the first electrode is electrically connected with the circuit wiring on the first surface of the rigid substrate through the rewiring layer;

a protective layer is formed on the rewiring layer.

By adopting the preparation method of the embodiment of the application, the bare chip is embedded into the base body, the first electrode and the second electrode of the bare chip are respectively led to the same side of the base body through the through holes penetrating through the base body, and the bonding pad for realizing the connection of the bare chip and external equipment such as a printed circuit board is formed. In addition, each electrode of the bare chip is led out in a mode of being connected with the through hole penetrating through the base body, so that the occupied area of the chip packaging structure is small in panel design, and the thin and small design of the chip packaging structure is facilitated.

Drawings

Fig. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the prior art;

fig. 2 is a schematic diagram of the working principle of the PPG sensor;

fig. 3 is a schematic structural diagram of a chip package structure according to an embodiment of the present application;

fig. 4 is a flowchart of a method for manufacturing a chip package structure according to an embodiment of the present disclosure;

fig. 5 to 13 are schematic structural diagrams illustrating a manufacturing process of a chip package structure according to an embodiment of the present application;

fig. 14 to 15 are schematic structural diagrams illustrating a manufacturing process of a chip package structure according to another embodiment of the present application;

fig. 16 to 19 are schematic structural diagrams illustrating a manufacturing process of a chip package structure according to another embodiment of the present application;

fig. 20 is a schematic structural diagram of a chip package structure according to another embodiment of the present application;

fig. 21 is a flowchart of a method for manufacturing a chip package structure according to another embodiment of the present disclosure;

fig. 22 to 28 are schematic structural diagrams illustrating a manufacturing process of a chip package structure according to another embodiment of the present application.

Reference numerals:

101-a die; 102-a substrate; 103-bonding wires; 201-a light emitting device die; 2011-first front side electrode;

2012-a first back electrode; 202-a photo-receiver die; 2021-a second front electrode; 2022-a second back electrode;

203-the skin surface; 301-first electrode lines; 3011-a through hole; 3012-RDL; 3013-a lead; 302-a second electrode line;

303-third electrode lines; 304-fourth electrode lines; 305-a protective layer; 306-a pad; 307-light retaining wall; 308-windowing;

501-a support plate; 502-an adhesive layer; 1601-a metal layer; 1701-bonding wire; 2001-rigid substrate;

20011-a first receiving groove; 20012-a second receiving groove; 2002-a filler layer; 2003-via holes.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail with reference to the accompanying drawings.

The terminology used in the following examples is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the present application and the appended claims, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, such as "one or more", unless the context clearly indicates otherwise.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.

For the convenience of understanding the chip package structure provided in the embodiments of the present application, an application scenario thereof is first described below. At present, in order to meet the increasing functional requirements of electronic devices, various sensors are required to be arranged in the electronic devices. For example, a photoplethysmography (PPG) sensor is disposed in some electronic devices such as smart bracelets or watches to detect heart rate and blood oxygen of a human body.

In addition, when a sensor is specifically arranged, a chip of the sensor generally needs to be packaged to form a chip package structure, so as to protect the chip. Referring to fig. 1, a conventional chip package structure is provided in which a die 101 is bonded to a base 102 to electrically and physically protect the die 101 by electrically and fixedly connecting the die 101 to the base 102. The front electrode of the die 101 is connected to the base 102 by bonding with a bonding wire 103, the back electrode of the die 101 is electrically connected to the base 102 by silver paste, and finally the input interface and the output interface of the die 101 are led out through the base 102. However, in the chip package structure, the thickness of the substrate 102 and the height of the bonding wires 103 occupy the space of the package height, and the bonding wires 103 occupy the space of the plane, which greatly affects the miniaturization design of the chip package structure, thereby resulting in a sensor, so that the electronic device has a larger volume, which is contrary to the development requirement of the miniaturization and thinning design of the electronic device.

In order to solve the above problem, the present application provides a chip package structure to achieve a miniaturized design of the chip package structure on the basis of meeting the requirement of package protection for a bare chip. In addition, based on the development trend of more and more electronic devices to provide a PPG sensor, in the following embodiments, a chip package structure in the PPG sensor is taken as an example, and the chip package structure of the present application is described in detail with reference to the accompanying drawings.

Referring to fig. 2, the working principle of the PPG sensor is first understood. The PPG sensor mainly includes a light emitting device die 201 and a photo-receiver die 202, where the light emitting device die 201 may be, but is not limited to, a Light Emitting Diode (LED) die, and the photo-receiver die 202 may be, but is not limited to, a photo-diode (PD) die. Thus, when a light beam of a certain wavelength emitted by the light emitting device die 201 is irradiated to the skin surface 203, the light beam will be transmitted to the photoelectric receiver die 202 by transmission or reflection. During this process, the light intensity detected by the photo-receiver die 202 will decrease due to absorption attenuation by skin muscles and blood. Where the absorption of light by skin, muscle, tissue, etc. remains constant throughout the blood circulation, being a DC (direct current) signal; the blood volume in the skin changes pulsatory under the action of the heart and belongs to an AC (alternating current) signal. When the heart contracts, the peripheral blood volume is the largest, the absorption amount of the blood to the light is the largest, and the detected light intensity is the smallest; at diastole, on the contrary, the detected light intensity is the largest, so that the light intensity received by the light receiver die pulsatory changes. Since the pulse wave is of the same frequency as the heart beat under normal conditions, the heart rate detection can be performed with PPG techniques. In addition, the difference of the absorption coefficients of oxyhemoglobin and reduced hemoglobin at different wavelengths can be used to measure the blood oxygen saturation.

As can be known from the above description of the operating principle of the PPG sensor, the chip package structure in the PPG sensor is mainly obtained by packaging the light emitting device die 201 and the photo-receiver die 202.

Referring to fig. 3, in one embodiment provided herein, a chip package structure may include a light emitting device die 201, a photoreceiver die 202, and a base 102. The shape of the chip package structure may be, but is not limited to, a rectangle, an arc or a circle. In the embodiment of the present application, a side where the light emitting surface of the light emitting device die 201 is located is referred to as a front surface of the chip package structure, and a side opposite to the front surface is referred to as a back surface of the chip package structure, it is understood that the light emitting surface of the light emitting device die 201 and the light receiving surface of the photoreceiver die 202 are located on the same side. The base 102 may be, but not limited to, made of a molding compound made of a composite material such as epoxy resin, the light-emitting device die 201 and the photoelectric receiver die 202 are embedded in the base 102, and in addition, the base 102 may also expose a light-emitting surface of the light-emitting device die 201 and a light-receiving surface of the photoelectric receiver die 202, so as to facilitate improvement of light emission and reception performance.

The front surface of the light-emitting device bare chip 201 is provided with a first front surface electrode 2011, the back surface of the light-emitting device bare chip 201 is provided with a first back surface electrode 2012, the first front surface electrode 2011 is connected with the first electrode wire 301, and the end part of the first electrode wire 301, which extends out of the back surface of the base body 102 after passing through the base body 102, is used as a first interface; the first backside electrode 2012 is connected to the second electrode line 302, and the second electrode line 302 extends to the backside of the substrate 102 as a second interface. Wherein the first interface and the second interface can be used as an input interface and an output interface of the light emitting device die 201, respectively.

The front surface of the photo-receiver die 202 has a second front electrode 2021, the back surface of the photo-receiver die 202 has a second back electrode 2022, the second front electrode 2021 is connected to a third electrode line 303, the third electrode line 303 extends to the back surface of the base 102 after passing through the base 102 to serve as a third interface, the second back electrode 2022 is connected to a fourth electrode line 304, and the fourth electrode line 304 extends to the back surface of the base 102 after passing through the base 102 to serve as a fourth interface. Wherein the third interface and the fourth interface can be used as an input interface and an output interface of the photo-receiver die 202, respectively.

In the embodiment of the present application, an input interface and an output interface of the light-emitting device die 201 and the printed circuit board are formed by embedding the light-emitting device die 201 and the photoreceiver die 202 into the base 102, and guiding the first front electrode 2011 and the first back electrode 2012 of the light-emitting device die 201 to the same side of the base 102 through the first electrode line 301 and the second electrode line 302 penetrating through the base 102, respectively; the second front electrode 2021 and the second back electrode 2022 of the photo-receiver die 202 are respectively led to the same side of the base 102 through the third electrode line 303 and the fourth electrode line 304 penetrating through the base 102 to form an input interface and an output interface for connecting the photo-receiver die 202 with a printed circuit board. In addition, each electrode of the bare chip is led out in a mode of being connected with an electrode wire penetrating through the base body 102, so that the board occupying design of the chip packaging structure is smaller, and the thinning and miniaturization design of the chip packaging structure is favorably realized.

Specifically, when the first electrode lines 301 are disposed, referring to fig. 3, the first electrode lines 301 may include a via 3011 opened on the substrate 102 and a redistribution layer (RDL 3012) disposed on the front surface of the substrate 102, where one end of the RDL 3012 on the front surface of the substrate 102 is connected to the first front electrode 2011 of the light emitting device die 201, and the other end is connected to the via 3011. The through holes 3011 are coated or filled with a conductive material, and the through holes 3011 extend through the substrate 102 to the back side of the substrate 102 to serve as an interface for the light emitting device die 201 to connect to a printed circuit board in an electronic device. In addition, in some embodiments, in order to meet the requirement of connecting the light emitting device die 201 with the printed circuit board, it is also necessary to provide an RDL 3012 connected with the through hole 3011 on the back surface of the base 102 to improve the convenience of connection.

When the second electrode lines 302 are specifically arranged, the second electrode lines 302 may include an RDL 3012 disposed on the back surface of the substrate 102, where one end of the RDL 3012 is connected to the first back electrode 2012, and the other end serves as an interface for connecting the light emitting device die 201 to the printed circuit board.

Referring to fig. 3, due to the third electrode lines 303 and the fourth electrode lines 304 of the photo-receiver die 202, the first electrode lines 301 and the second electrode lines 302 of the light emitting device die 201 are arranged in a similar manner. In this way, when the third electrode line 303 and the fourth electrode line 304 are set, reference may be made to the setting manner of the first electrode line 301 and the second electrode line 302, and details are not described here.

With reference to fig. 3, the chip package structure may further include a protection layer 305 covering the front surface and the back surface of the substrate 102 to protect the exposed portions of the first electrode lines 301, the second electrode lines 302, the third electrode lines 303, and the fourth electrode lines 304 on the surface of the substrate 102. In addition, when the protection layer 305 is specifically provided, the protection layer 305 may be made of an insulating material such as Polyimide (PI) or poly-p-Phenylene Benzobisoxazole (PBO) to perform an insulating protection function on each electrode line. Since the light-emitting device die 201 and the photoreceiver die 202 are embedded in the base body 102, a window 308 may be provided to expose the light-emitting surface of the light-emitting device die 201 and the light-receiving surface of the photoreceiver die 202 when the protective layer 305 is provided, which may reduce the loss of light. In addition, the heat generated by the light emitting device die 201 and the photoelectric receiver die 202 only needs to be conducted through the protective layer 305, and the heat dissipation path is short, so that the heat dissipation efficiency is high. Further, the thickness of the protective layer 305 may also be made to be on the order of micrometers to achieve higher heat dissipation efficiency.

Referring to fig. 3, considering that the first interface, the second interface, the third interface and the fourth interface are connected to a printed circuit board, a lead 3013 may be further disposed at each RDL 3012 on the back surface of the substrate 102 to lead out each electrode to the surface of the protective layer 305 away from the substrate 102. Thus, the end of the lead 3013 on the surface of the protective layer 305 remote from the base 102 serves as an interface for the corresponding electrode. In addition, one pad 306 may be correspondingly disposed at each interface. Meanwhile, a solder layer may be coated on each bonding pad 306, and the material of the solder layer may be, but is not limited to, solder paste, so as to facilitate the soldering between the chip package structure and the printed circuit board. In the specific arrangement of the solder layer, the thickness of the solder layer may be, but not limited to, 20 to 40 μm, and exemplarily, the thickness of the solder layer may be 25 μm, 28 μm, 30 μm, 32 μm, 35 μm, 38 μm, or the like. On the basis of meeting the welding requirement, the influence of the welding requirement on the volume of the chip packaging structure is reduced. Alternatively, nickel, palladium, gold, or the like may be directly plated on the pad 306 to perform oxidation prevention treatment.

When the chip package structure of the embodiment of the present application is applied to a PPG sensor, two electrodes of the light emitting device die 201 may be powered through two bonding pads 306 at two interfaces of the light emitting device die 201. Meanwhile, after the light emitted by the light emitting device bare chip 201 reaches the human body, the light is reflected back to the light receiving surface of the photoelectric receiver bare chip 202, the photoelectric receiver bare chip 202 forms a loop with the second back electrode 2022 and the back RDL 3012 by the second front electrode 2021, the front RDL 3012 and the through hole 3011, and is connected to the signal processing circuit through the two bonding pads 306 at the interface, so that the detection of the heart rate and the blood oxygen saturation degree is realized.

In addition, in addition to the above structure, with reference to fig. 3, a light-blocking wall 307 may be further included in the chip package structure, and the light-blocking wall 307 is disposed on the front surface of the chip package structure and is disposed between the light-emitting device die 201 and the photo-receiver die 202, so that the light emitted from the light-emitting device die 201 and the light received by the photo-receiver die 202 are not affected by each other, and the detection accuracy of the PPG sensor using the chip package structure can be improved.

Specifically, when the light-blocking wall 307 is disposed, the material of the light-blocking wall 307 may be, but not limited to, a light-shielding material such as Liquid Crystal Polymer (LCP) or black glue, so as to be fixed to the protection layer 305 by adhesion. Since the light emitting device bare chip 201 and the photoelectric receiver bare chip 202 are embedded in the base 102, compared with the scheme of fig. 1 in which the light emitting device bare chip 201 and the photoelectric receiver bare chip 202 are disposed on the surface of the base 102, in the embodiment of the present application, the height of the light ray retaining wall 307 can be reduced as much as possible on the basis that the emitted light ray and the received light ray between the light emitting device bare chip 201 and the photoelectric receiver bare chip 202 are not affected by each other through the light ray retaining wall 307, thereby facilitating the thinning of the chip package structure.

Based on the same inventive concept, the embodiment of the present application further provides an electronic device, which may include the chip package structure in any of the above embodiments, and a printed circuit board. The chip packaging structure is electrically connected with the printed circuit board so as to realize the function of the chip packaging structure. The chip packaging structure of the electronic equipment has small volume, so that the miniaturization and thinning design of the electronic equipment can be realized. The electronic device provided by the embodiment of the application can be, but is not limited to, a terminal device such as a smart phone, a smart television set-top box, a Personal Computer (PC), a wearable device, and an intelligent broadband; or telecommunication devices such as wireless networks, fixed networks, servers, etc., and electronic devices such as chip modules, memories, etc., which are not listed herein.

To further understand the chip package structure according to the above embodiments of the present application, an embodiment of the present application further provides a method for manufacturing the chip package structure, and fig. 4 is a flowchart illustrating a manufacturing process of the chip package structure according to the embodiment of the present application. The preparation method specifically comprises the following steps:

step 001: the light emitting device die 201 and the photoelectric receiver die 202 are bonded to a support plate 501, which may be, but is not limited to, a glass plate, a silicon wafer, a metal plate, or the like. Referring to fig. 5, wherein the front surfaces of the light emitting device die 201 and the photoelectric receiver die 202 are bonded to the support plate 501, the bonding may be, but not limited to, by coating an adhesive layer 502 on the support plate 501.

Step 002: the base body 102 is formed around the light-emitting device die 201 and the photoelectric receiver die 202, referring to fig. 6, so that the light-emitting device die 201 and the photoelectric receiver die 202 are embedded within the base body 102. In addition, the material of the substrate 102 may be, but is not limited to, a molding compound.

Step 003: by using a grinding method, the excess molding compound on the back surfaces of the light-emitting device die 201 and the photoelectric receiver die 202 is removed, referring to fig. 7, so that the first back electrode 2012 of the light-emitting device die 201 and the second back electrode 2022 of the photoelectric receiver die 202 are exposed.

Step 004: a through hole 3011 is formed in the substrate 102, and referring to fig. 8, the through hole 3011 penetrates the substrate 102. The through holes 3011 may be opened near the light-emitting device die 201 and the photoelectric receiver die 202 to facilitate leading out electrodes of the light-emitting device die 201 and the photoelectric receiver die 202.

Step 005: a redistribution layer is formed on the back surface of the base 102. Referring to fig. 9, by using a method of sputtering a seed layer, plating, exposure, development, etching, and the like, a plating layer is formed in the through hole 3011, and an RDL 3012 connected to the first back electrode 2012 of the light-emitting device die 201 and the second back electrode 2022 of the photoreceptor die 202, and an RDL 3012 connected to each through hole 3011 are formed on the back surface of the base 102, respectively. In addition, the protective layer 305 of the RDL 3012 may be formed by coating an insulating material such as Polyimide (PI) or a poly-p-Phenylene Benzobisoxazole (PBO) layer.

Step 006: referring to fig. 10, at each RDL 3012, a pad 306 connected to the RDL 3012 is formed to serve as an input interface or an output interface for each electrode. In addition, it is also possible to brush micron-sized solder paste at each pad 306, and form a thin solder paste pad 306 by reflow soldering.

Step 007: the support plate 501 is bonded on the pad 306 side and turned 180 °. The supporting plate 501 adhered to the back surface of the base 102 is removed by ultraviolet rays, pyrolysis, photolysis, or the like, thereby obtaining the structure shown in fig. 11.

Step 008: a redistribution layer is formed on the front surface of the base 102. Referring to fig. 12, RDLs 3012 connected to the first front electrode 2021 of the light emitting device die 201 and the second front electrode 2022 of the photoreceptor die 202 are formed on the front surface of the substrate 102 by methods such as seed layer sputtering, electroplating, exposure, development, and etching, the RDLs 3012 are further connected to corresponding vias 3011, and insulating materials such as polyimide resin (PI) or poly-p-Phenylene Benzobisoxazole (PBO) may be further coated to form the protective layer 305 of the RDL 3012. In addition, a window design may be performed on the protective layer 305 by exposure, development, etching, and the like to expose the light emitting surface of the light emitting device die 201 and the light receiving surface of the photoreceiver die 202, so as to reduce the loss of light. In addition, it is understood that, in order to make the area of the light emitting surface of the light emitting device die 201 exposed as large as possible, the portions where the RDL 3012 is connected to the first front surface electrode 2011 and the second front surface electrode 2021 may be designed to be straight lines and have a small line width.

Step 009: forming light retaining walls 307. Depending on the interference between the emitted and received light, light barriers 307 may be formed on the front surface of the substrate 102 by bonding LCP or coating black glue between the light emitting device die 201 and the photo-receiver die 202 to form the structure shown in fig. 13. And removing the supporting plate 501 at the side of the bonding pad 306 by ultraviolet, thermal decomposition or photolysis, etc., so as to obtain the chip package structure shown in fig. 3.

By adopting the preparation method of the embodiment of the application, the light-emitting device bare chip 201 and the photoelectric receiver bare chip 202 are embedded into the base body 102, the first front electrode 2011 and the first back electrode 2012 of the light-emitting device bare chip 201 are respectively provided with the through hole 3011 on the base body 102, and the RDL 3012 is respectively arranged on the front surface and the back surface of the base body 102, so that the first front electrode 2011 and the first back electrode 2012 are led to the same side of the base body 102, and an input interface and an output interface for connecting the light-emitting device bare chip 201 and a printed circuit board are formed; the second front electrode 2021 and the second back electrode 2022 of the photo-receiver die 202 are respectively connected to the substrate 102 by forming a through hole 3011, and providing RDLs 3012 on the front surface and the back surface of the substrate 102, respectively, so as to lead the second front electrode 2021 and the second back electrode 2022 to the same side of the substrate 102, and form an input interface and an output interface for connecting the photo-receiver die 202 to a printed circuit board. In addition, each electrode of the bare chip is led out in a mode of being connected with the through hole 3012 penetrating through the base body 102, so that the board occupying design of the chip packaging structure is small, and the thin and small design of the chip packaging structure is favorably realized.

It will be appreciated that during the fabrication of the chip package described above, a wafer level package may be formed for a set of light emitting device die 201 and photo-receiver die 202. The multiple light-emitting device bare chips 201 and the multiple photoelectric receiver bare chips 202 can also be packaged simultaneously to form a panel-level packaging structure, and finally, a mechanical knife or laser is adopted for cutting to form a single chip packaging structure, so that the preparation efficiency of the chip packaging structure can be effectively improved, and the preparation cost is reduced.

In addition, in the process of preparing the chip packaging structure by adopting the chip packaging structure preparation method provided by the embodiment of the application, a plurality of packaging procedures such as packaging a substrate, substrate pre-baking, silver paste baking, wire bonding and the like are not needed, and the total preparation cost is reduced.

In some embodiments of the present application, after the structure shown in fig. 6 is formed in step 002, in a process of removing excess molding compound on the back surfaces of the light-emitting device die 201 and the optoelectronic receiver die 202 by using a grinding method, in order to avoid damaging the first back electrode 2012 of the light-emitting device die 201 and the second back electrode 2022 of the optoelectronic receiver die 202, some molding compound layers may be reserved on the light-emitting device die 201 and the optoelectronic receiver die 202, as shown in fig. 14. In this way, in step 004, the through-hole 3011 penetrating the substrate 102 is formed in the substrate 102, and the through-holes 3011 are also formed in positions on the back surface of the substrate 102 facing the first back electrode 2012 and the second back electrode 2022, respectively, so as to expose the first back electrode 2012 and the second back electrode 2022, thereby forming the structure shown in fig. 15. In this embodiment of the present application, in the subsequent process of preparing the chip package structure, the specific steps may be performed with reference to the previous embodiment, and are not described herein again.

In other embodiments of the present application, after the structure shown in fig. 5 is formed through step 001, a metal layer 1601 may be sputtered or electroless-plated on the glue layer of the supporting board 501 to form the structure shown in fig. 16. Then, a bonding wire 1701 perpendicular to the supporting board 501 is formed on the first backside electrode 2012 of the light emitting device die 201 and the second backside electrode 2022 of the photoreceptor die 202, and on the metal layer 1601, respectively, and after the bonding wire 1701 is pulled to a certain height, the bonding wire 1701 is cut off to form the structure shown in fig. 17.

A base 102 is formed on the structure shown in fig. 17 to package a light-emitting device die 201, a photoelectric receiver die 202, and respective bonding wires 1701, resulting in the structure shown in fig. 18. The excess substrate 102 is removed by polishing or the like until all the bonding wires 1701 are exposed, as shown in fig. 19. Thereafter, RDLs 3012 connected to the bonding lines 1701 may be formed on the substrate 102 layer, as described above with reference to the above embodiment. The subsequent preparation process of the chip package structure in the embodiment of the present application is similar to that in the above embodiment, and is not described herein again.

It is understood that the above method for manufacturing a chip package structure may be, but not limited to, used to package a light emitting device die and a photo-receiver die in a PPG sensor, and it may also be used to manufacture other optical device package structures requiring miniaturized package.

Referring to fig. 20, the present application also provides a chip package structure, which may include a light emitting device die 201, a photoreceiver die 202, and a base 102. In the embodiment of the present application, a side where the light emitting surface of the light emitting device die 201 is located is referred to as a front surface of the chip package structure, and a side opposite to the front surface is referred to as a back surface of the chip package structure, it is understood that the light emitting surface of the light emitting device die 201 and the light receiving surface of the photoreceiver die 202 are located on the same side. The base 102 may include a rigid substrate 2001, a first receiving groove 20011 and a second receiving groove 20012 are formed in the rigid substrate 2001, and the light emitting device die 201 and the photo receiver die 202 are respectively received in the first receiving groove 20011 and the second receiving groove 20012. In addition, in order to prevent the light emitting device die 201 and the photoreceiver die 202 from being worn by the rigid substrate 2001, referring to fig. 20, a certain gap D1 may be formed between the light emitting device die 201 and the groove wall of the first accommodating groove 20011, a certain gap D2 may be formed between the photoreceiver die 202 and the groove wall of the second accommodating groove 20012, and neither the gap D1 nor the gap D2 is smaller than 50 um.

In addition, when there is a gap between the light emitting device die 201 and the first receiving groove 20011, and between the photoreceiver die 202 and the second receiving groove 20012, the base 102 may further include a filling layer 2002, where the filling layer 2002 is disposed on the rigid substrate 2001, and fills the gap between the light emitting device die 201 and the first receiving groove 20011, and the gap between the photoreceiver die 202 and the second receiving groove 20012, so as to limit and fix the light emitting device die 201 and the photoreceiver die 202. The material of the filling layer 2002 may be, but is not limited to, polypropylene (PP) resin or bt (bis-imide triazine) resin, etc. and may be a bonding material.

With continued reference to fig. 20, the base 102 may also expose the light emitting surface of the light emitting device die 201 and the light receiving surface of the photo-receiver die 202 to facilitate improved light emission and reception.

The front surface of the light-emitting device bare chip 201 is provided with a first front surface electrode 2011, the back surface of the light-emitting device bare chip 201 is provided with a first back surface electrode 2012, the first front surface electrode 2011 is connected with the first electrode wire 301, and the first electrode wire 301 penetrates through the base body 102 and then extends out to the back surface of the base body 102 to serve as a first interface; the first back electrode 2012 is connected to the second electrode line 302, and the second electrode line 302 passes through the substrate 102 and then extends to the back of the substrate 102 as a second interface. Wherein the first interface and the second interface can be used as an input interface and an output interface of the light emitting device die 201, respectively.

In the embodiment of the present application, an input interface and an output interface of the light-emitting device die 201 and the printed circuit board are formed by embedding the light-emitting device die 201 and the photoreceiver die 202 into the base 102, and guiding the first front electrode 2011 and the first back electrode 2012 of the light-emitting device die 201 to the same side of the base 102 through the first electrode line 301 and the second electrode line 302 penetrating through the base 102, respectively; the second front electrode 2021 and the second back electrode 2022 of the photo-receiver die 202 are respectively led to the same side of the base 102 through the third electrode line 303 and the fourth electrode line 304 penetrating through the base 102 to form an input interface and an output interface for connecting the photo-receiver die 202 with a printed circuit board. In addition, each electrode of the bare chip is led out in a mode of being connected with an electrode wire penetrating through the base body 102, so that the design of the occupied panel of the chip packaging structure is small, and the thinning and miniaturization design of the chip packaging structure is facilitated.

In particular, when the first electrode lines 301 are disposed, referring to fig. 20, the first electrode lines 301 may include a through hole 3011 opened in the substrate 102, and a redistribution layer (RDL 3012) disposed on the front surface of the substrate 102, where one end of the redistribution layer on the front surface of the substrate 102 is connected to the front surface electrode of the light emitting device die 201, and the other end of the redistribution layer is connected to the through hole 3011. The through holes 3011 are coated or filled with a conductive material, and the through holes 3011 extend through the substrate 102 to the back surface of the substrate 102 to serve as an interface for connecting the light emitting device dies 201 to a printed circuit board. In addition, in some embodiments, a metal layer 1601 is further coated on each of the front surface and the back surface of the rigid substrate 2001, and then circuit traces may be formed on the metal layer 1601 of the rigid substrate 2001 and connected to the through holes 3011 and the RDL 3012 on the rigid substrate 102. With reference to fig. 20, when the hard substrate 2001 has the metal layer 1601 on the back surface, circuit traces may be formed on the metal layer 1601, and the circuit traces are connected to the through holes 3011 on the hard substrate 2001.

In specific arrangement of the second electrode line 302, referring to fig. 20, in some embodiments, the filling layer 2002 covers the first back electrode 2012 of the light emitting device die 201, and when the second electrode line 302 is arranged, the second electrode line 302 includes a via hole opened in the filling layer 2002, one end of the via hole is connected to the first back electrode 2012, and the other end of the via hole is used as an interface for connecting the light emitting device die 201 to the printed circuit board.

Referring to fig. 20, the third electrode lines 303 and the fourth electrode lines 304 of the photoreceptor die 202 are arranged in a similar manner to the first electrode lines 301 and the second electrode lines 302 of the light emitting device die 201. In this way, when the third electrode line 303 and the fourth electrode line 304 are set, reference may be made to the setting manner of the first electrode line 301 and the second electrode line 302, and details are not described here.

With reference to fig. 20, the chip package structure may further include a protection layer 305 covering the front surface and the back surface of the substrate 102 to protect the exposed portions of the first electrode lines 301, the second electrode lines 302, the third electrode lines 303, and the fourth electrode lines 304 on the surface of the substrate 102. In addition, when the protective layer 305 is specifically provided, the protective layer 305 may be, but is not limited to, paint, such as green paint, to perform an insulating protection function on each electrode line. Since the light-emitting device die 201 and the photoelectric receiver die 202 are embedded in the base body 102, the generated heat only needs to be conducted through the partial filling layer 2002 and the protective layer 305, the heat dissipation path is short, and the heat dissipation efficiency is high. Further, the thickness of the protective layer 305 may also be made to be on the order of micrometers to achieve higher heat dissipation efficiency.

Referring to fig. 20, considering that the first interface, the second interface, the third interface and the fourth interface are to be connected to the printed circuit board, a pad 306 may be correspondingly disposed at each of the first interface, the second interface, the third interface and the fourth interface, so as to facilitate connection between the chip package structure and the printed circuit board by soldering.

In addition, with reference to fig. 20, in addition to the above structure, a light-blocking wall 307 may be further included in the chip package structure, and the light-blocking wall 307 is disposed on the front surface of the chip package structure and is disposed between the light-emitting device die 201 and the photo-receiver die 202, so that the light emitted from the light-emitting device die 201 and the light received by the photo-receiver die 202 are not affected by each other, and the detection accuracy of the PPG sensor using the chip package structure can be improved.

Specifically, when the light-blocking wall 307 is disposed, the material of the light-blocking wall 307 may be, but is not limited to, Liquid Crystal Polymer (LCP), black glue, or the like, and is fixed to the protection layer 305 by adhesion. Since the light emitting device bare chip 201 and the photoelectric receiver bare chip 202 are embedded in the base 102, compared with the scheme of fig. 1 in which the light emitting device bare chip 201 and the photoelectric receiver bare chip 202 are disposed on the surface of the base 102, in the embodiment of the present application, the height of the light ray retaining wall 307 can be reduced as much as possible on the basis that the emitted light ray and the received light ray between the light emitting device bare chip 201 and the photoelectric receiver bare chip 202 are not affected by each other through the light ray retaining wall 307, thereby facilitating the thinning of the chip package structure.

To further understand the chip package structure according to the above embodiments of the present application, an embodiment of the present application further provides a method for manufacturing the chip package structure, and reference may be made to fig. 21, where fig. 21 is a flowchart for manufacturing the chip package structure according to the embodiment of the present application. In this embodiment, the preparation method is described by taking an example that the metal layers 1601 are disposed on both the front surface and the back surface of the rigid substrate 2001, and the preparation method specifically includes:

step 101: a first receiving groove 20011 and a second receiving groove 20012 are formed on the rigid substrate 2001. The first receiving groove 20011 and the second receiving groove 20012 may be formed on the rigid substrate 2001 by a drilling process. In addition, a pattern for forming circuit traces may be formed on the metal layer 1601 of the rigid substrate 2001 by etching, electroplating, exposure, and development, and a through hole 3011 may be formed on the rigid substrate 2001, and both ends of the through hole 3011 are connected to the circuit traces on both sides of the rigid substrate 2001, respectively, to form the structure shown in fig. 22.

Step 102: an adhesive layer 502, such as an adhesive tape, is attached to one side of the rigid substrate 2001, and the light emitting device die 201 and the light receiving device die are respectively accommodated in the first accommodating groove 20011 and the second accommodating groove 20012 of the rigid substrate 2001 and are adhered to the adhesive layer 502. Referring to fig. 23, the front surface of the light emitting device die 201 and the front surface of the photo receiver die are bonded to the bonding layer 502, the light emitting device die 201 is in clearance fit with the first receiving groove 20011, the photo receiver die is in clearance fit with the second receiving groove 20012, a clearance D1 between the light emitting device die 201 and the first receiving groove 20011 and a clearance D2 between the photo receiver die and the second receiving groove 20012 are not less than 50um, so as to prevent the hard substrate 2001 from causing mechanical damage to each die.

Step 103: the filling layer 2002 of PP or BT resin or the like is laminated on the rigid substrate 2001 by a laminating device. Referring to fig. 24, the light emitting device bare chip 201 and the photoelectric receiver 202 bare chip are limited and fixed.

Step 104: the adhesive layer 502 on the rigid substrate 2001 is removed, and through holes 2003 exposing the first back electrode 2012 of the light emitting device die 201 and the second back electrode 2022 of the photoreceptor 202 die, respectively, are etched on the filling layer 2002 by using methods such as exposure, development and etching, so as to form the structure shown in fig. 25.

Step 105: a seed layer is manufactured by adopting a sputtering method, a chemical plating method and the like, then an electroplating layer is formed in the via hole 2003, a surface layer circuit trace and a bonding pad 306 are manufactured and formed on the substrate 102 by adopting methods of exposure, development and the like, a solder layer can be coated on the bonding pad 306, nickel, palladium, gold and the like can be directly plated on the bonding pad 306 for anti-oxidation treatment, and the structure shown in fig. 26 is obtained.

Step 106: the rigid substrate 2001 is turned over 180 °, as shown in fig. 27, to facilitate the subsequent process.

Step 107: an RDL 3012 is formed on the front surface of the rigid substrate 2001. RDLs 3012 connected to the first front electrode 2011 of the light emitting device bare chip 201 and the second front electrode 2021 of the photoreceptor bare chip 202 are formed on the front surface of the rigid substrate 2001 by methods of seed layer sputtering, electroplating, exposure, development, etching, and the like, and the RDLs 3012 are further connected to corresponding circuit traces on the rigid substrate 2001. Alternatively, a protective layer 305 may be formed by applying a green paint to both sides of the substrate 102. In addition, a window design may be performed on the protective layer 305 by exposure, development, etching, and the like to expose the light emitting surface of the light emitting device die 201 and the light receiving surface of the photoreceiver die 202, so as to reduce the loss of light. In addition, it is understood that, in order to make the area of the light emitting surface of the light emitting device die 201 exposed as large as possible, the portions where the RDL 3012 is connected to the first front surface electrode 2011 and the second front surface electrode 2021 may be designed to be straight lines and have a small line width. Since the pads 306 need to be connected to the printed circuit board, the pads 306 need to be exposed to form the structure shown in fig. 28 while the window design is performed on the protective layer 305.

Step 108: forming light retaining walls 307. Depending on the interference between the emitted and received light, light barriers 307 may be formed on the front surface of the substrate 102 by bonding LCP or coating black glue between the light emitting device die 201 and the photo-receiver die 202 to form the chip package structure shown in fig. 20.

By adopting the preparation method of the embodiment of the application, the light-emitting device bare chip 201 and the photoelectric receiver bare chip 202 are embedded into the base body 102, and the first front electrode 2011 and the first back electrode 2012 of the light-emitting device bare chip 201 are respectively led to the same side of the base body 102 through the via holes penetrating through the base body 102, so as to form the input interface and the output interface for connecting the light-emitting device bare chip 201 and the printed circuit board; the second front electrode 2021 and the second back electrode 2022 of the photoreceiver die 202 are respectively led to the same side of the base 102 through via holes passing through the base 102 to form an input interface and an output interface for connecting the photoreceiver die 202 with a printed circuit board. In addition, each electrode of the bare chip is led out in a mode of being connected with a through hole penetrating through the base body 102, so that the board occupying design of the chip packaging structure is small, and the thinning and miniaturization design of the chip packaging structure is favorably realized.

In the preparation process of the chip package structure, a wafer-level package structure may be formed for a group of the light emitting device die 201 and the photoelectric receiver die 202. Or a plurality of light emitting device dies 201 and a plurality of photoelectric receiver dies 202 may be packaged simultaneously to form a panel-level package structure, and finally, a mechanical knife or laser may be used to cut the package structure to form a single chip package structure. The preparation efficiency of the chip packaging structure can be effectively improved, and therefore the preparation cost is reduced.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A chip package structure, comprising a die and a substrate, wherein:

the die embedded in the base, the die including a first electrode assembly and a second electrode assembly;

the first electrode assembly is provided with a first interface;

the second electrode assembly is provided with a second interface, and the first interface and the second interface are positioned on the first surface of the base body.

2. The chip packaging structure according to claim 1, wherein the first electrode assembly comprises a first electrode and a first electrode wire which are electrically connected, and the second electrode assembly comprises a second electrode and a second electrode wire which are electrically connected; the first electrode and the second electrode are respectively arranged on two end faces of the bare chip, the two end faces are oppositely arranged, and at least one of the two end faces the first surface of the base body.

3. The chip package structure according to claim 2, wherein the first electrode line includes a first redistribution layer and a connection line, the first redistribution layer is disposed on the first surface of the substrate, the connection line penetrates through the substrate, the first electrode is electrically connected to the connection line through the first redistribution layer, and the first interface is disposed at an end of the connection line away from the first redistribution layer; the second electrode wire comprises a second rewiring layer arranged on the second surface of the base body, and one end, far away from the second electrode, of the second rewiring layer serves as the second interface.

4. The chip package structure according to claim 3, wherein the first electrode line further includes a third redistribution layer disposed on the second surface of the base, the third redistribution layer is electrically connected to the connection line, and the first interface is disposed at an end of the third redistribution layer away from the connection line.

5. The chip package structure according to claim 2, wherein the base includes a rigid substrate, a receiving slot is formed in the rigid substrate, and the bare chip is received in the receiving slot.

6. The chip package structure according to claim 5, wherein a gap exists between the die and the wall of the receiving groove, and the gap is greater than or equal to 50 μm.

7. The chip package structure according to claim 6, wherein the substrate further comprises a filling layer disposed on the rigid substrate and filling a gap between the bare chip and a wall of the accommodating groove.

8. The chip package structure according to any one of claims 5 to 7, wherein the first electrode line includes a fourth redistribution layer and a through hole, the fourth redistribution layer is disposed on the first surface of the base, the through hole penetrates through the base, and the first electrode is electrically connected to the through hole through the fourth redistribution layer; the first interface is arranged at one end of the through hole, which is far away from the fourth rewiring; and one end of the second electrode wire, which is far away from the second electrode, is used as the second interface.

9. The chip packaging structure according to claim 8, wherein circuit traces are respectively disposed on the first surface and the second surface of the rigid substrate, and the fourth redistribution layer and the first interface are electrically connected to the through hole through the circuit traces on the corresponding surfaces of the rigid substrate.

10. The chip packaging structure according to any one of claims 1 to 9, wherein one pad is disposed at each of the first interface and the second interface.

11. The chip packaging structure according to any one of claims 1 to 10, wherein the number of the dies is two, that is, a light emitting device die and a photoelectric receiver die, and a light emitting surface of the light emitting device die and a light receiving surface of the photoelectric receiver die are disposed toward the first surface of the base body.

12. The chip package structure according to claim 11, further comprising a light retaining wall fixed to the first surface of the base, wherein the light retaining wall is disposed between the light emitting device die and the photo-receiver die.

13. The chip package structure according to claim 11 or 12, wherein the base further defines a window for exposing a light emitting surface of the light emitting device die and a light receiving surface of the photoreceiver die.

14. An electronic device comprising a printed circuit board and the chip package structure according to any one of claims 1 to 13, wherein the chip package structure is electrically connected to the printed circuit board.

15. A method for preparing a chip packaging structure is characterized by comprising the following steps:

bonding a bare chip on a first supporting plate, wherein the end face of the bare chip provided with a first electrode is attached to the supporting plate;

forming a matrix around the die such that the die is embedded in the matrix;

forming a through-substrate via hole in the substrate on the side of the die periphery;

forming a first protective layer on the first and second rewiring layers;

forming a third redistribution layer on a surface of the base body remote from the second support plate, the third redistribution layer electrically connecting the first electrode with the through hole;

and forming a second protective layer on the third redistribution layer.

16. The method of manufacturing of claim 15, wherein a matrix is formed around the die such that the die is embedded in the matrix, the method further comprising:

and grinding the base body to expose the second electrode of the bare chip, wherein the second electrode is arranged on the surface of the base body far away from the first supporting plate.

17. The method for manufacturing according to claim 15, wherein when the through-substrate via hole is formed in the substrate on the die periphery side, the method further comprises:

and forming a through hole for exposing a second electrode of the bare chip on the base body, wherein the second electrode is arranged on the end face of the base body far away from the first supporting plate.

18. A method for preparing a chip packaging structure is characterized by comprising the following steps:

forming a metal layer on the first support plate;

forming a first bonding wire on the metal layer, and forming a second bonding wire on a second electrode of the bare chip, wherein the first bonding wire and the second bonding wire are both arranged perpendicular to the first support plate, and the second electrode is arranged on the end face of the bare chip far away from the first support plate;

forming a base around the die, the first wire bond, and the second wire bond such that the die, the first wire bond, and the second wire bond are embedded in the base;

forming a first rewiring layer and a second rewiring layer on the surface of the base body far away from the first supporting plate, wherein the first rewiring layer is electrically connected with the first bonding wire, and the second rewiring layer is electrically connected with the second bonding wire;

forming a first protective layer on the first and second rewiring layers;

forming a third rewiring layer on an end face of the base body away from the second support plate, the third rewiring layer electrically connecting the first electrode with the first bonding wire;

and forming a second protective layer on the third redistribution layer.

19. A method for preparing a chip packaging structure is characterized by comprising the following steps:

adhering an adhesive layer to the first surface of the rigid substrate, accommodating the bare chip in the accommodating groove, and adhering the end face of the bare chip, provided with the first electrode, to the adhesive layer;

bonding a filling layer on the substrate, and limiting and fixing the bare chip;

removing the adhesive layer on the rigid substrate;

and forming a protective layer on the redistribution layer.