CN113644002B - Method for testing minority carrier end contact resistance of solar cell - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000012360 testing method Methods 0.000 title claims abstract description 27
- 238000002161 passivation Methods 0.000 claims abstract description 29
- 230000005540 biological transmission Effects 0.000 claims abstract description 11
- 238000004458 analytical method Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 36
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 11
- 239000002346 layers by function Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 8
- 238000010998 test method Methods 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 claims description 3
- 229920001609 Poly(3,4-ethylenedioxythiophene) Polymers 0.000 claims description 2
- 230000005525 hole transport Effects 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims description 2
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- 238000010586 diagram Methods 0.000 abstract description 6
- 239000000523 sample Substances 0.000 description 19
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 229910000314 transition metal oxide Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000002207 thermal evaporation Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
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- 238000009825 accumulation Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
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- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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- Y02E10/50—Photovoltaic [PV] energy
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Abstract
A testing method of minority carrier terminal contact resistance of solar cell is to draw dV/d (lnI) -I curve through dark state I-V curve corresponding to different front electrode areas S of sample, to combine double (diode + resistance) equivalent circuit model to conduct sectional analysis to the curve, to calculate resistance-electrode area reciprocal curve, to obtain slope of straight line by curve fitting, namely minority carrier terminal specific contact resistance of undoped heterojunction cell sample with passivation layer. According to the method, a corresponding equivalent circuit diagram is established by combining a carrier transmission model of the minority carrier terminal of the undoped heterojunction solar cell with the passivation layer, so that the minority carrier terminal contact resistance of the undoped heterojunction solar cell with the passivation layer is extracted.
Description
Technical Field
The invention relates to the technical field of performance test of undoped heterojunction solar cells, in particular to a test method for extracting minority carrier terminal contact resistance of an undoped heterojunction solar cell with a passivation layer based on a double (diode+resistor) model.
Background
The key to solar cells is to have good passivation contacts, which require good passivation and low contact resistance. The problem that the efficiency of the doping-free heterojunction battery is influenced is more prominent on the problem of the contact resistance of the doping-free heterojunction battery, and the contact resistance of the doping-free heterojunction battery is usually 2-5 orders of magnitude higher than that of the homojunction solar battery, so that the doping-free heterojunction battery largely counteracts the dominant accumulation of the heterojunction battery on passivation. Therefore, how to effectively and accurately test the contact resistance value of the heterojunction is critical to judging the quality of the undoped heterojunction. In the doping-free heterojunction battery, taking an n-type silicon substrate as an example, the minority carrier end (hole transmission end of n-type silicon) contact resistance of the battery is usually 1-2 orders of magnitude larger than the majority carrier end (electron transmission end of n-type silicon) under the same condition, and becomes an important factor influencing the series resistance of the battery.
However, the current contact resistance test methods are mainly CS (Cox and Strack) test methods (Cox R H, strack H.ohmic contacts for GaAs devices [ J ]. Solid State Electronics,1966,10 (12): 36-36) using different disk sizes and test methods (Reeves G K, harrison H.oblating the specific contact resistance from transmission line model measurements [ J ]. IEEE Electron Device Letters,2005,3 (5): 111-113) using a transmission line matrix TLM (Transfer Length Method). Both test methods are applicable to ohmic contact situations. The contact resistance at the majority carrier terminal is tested, mainly in ohmic contact, so that the method can be used for accurately measuring. However, minority carrier terminals are typically non-ohmic contacts and conventional contact resistance testing has failed.
Early Wang Wei et al successfully extracted the specific contact resistance of the heterojunction transition metal oxide/n-Si minority carrier end by an improved CS method (Wang W, lin H, yang Z, et al, an Expanded Cox and Strack Method for Precise Extraction of Specific Contact Resistance of Transition Metal Oxide/n-Silicon Heterojunction [ J ]. IEEE Journal ofPhotovoltaics,2019, 9:1113-1120). However, in order to achieve good passivation quality, a passivation layer is usually introduced between the transition metal oxide and n-Si, and the I-V curve of the heterojunction is complicated by inserting the passivation layer, and the method of Wang Wei and the like cannot explain the change of the curve, so that accurate contact resistance is not extracted.
Disclosure of Invention
Aiming at the defect that at least more than ten physical parameters need to be input in the existing simulation process and a doping-free heterojunction transmission model is difficult to fit, the invention provides a test method for the contact resistance of the minority carrier terminal of the solar cell.
The invention is realized by the following technical scheme:
the invention relates to a test method of a minority carrier terminal contact resistance of a solar cell, which comprises the steps of drawing a dV/d (lnI) -I curve through dark state I-V curves corresponding to different front electrode areas S of samples, carrying out sectional analysis on the curve by combining a double (diode+resistor) equivalent circuit model, further calculating a resistance-electrode area reciprocal curve, and obtaining a slope of a straight line through curve fitting, namely the minority carrier terminal specific contact resistance of a non-doped heterojunction cell sample with a passivation layer.
The sample is obtained by adopting a photoetching method to prepare an isolation layer, and different front electrode areas S are arranged in the functional layer in the preparation process.
The passivation layer adopts but is not limited to SiO x a-Si, H (i) or AlO x And the like.
The functional layer adopts but is not limited to MoO when the substrate is an n-type silicon wafer x PEDOT PSS or VO x A high work function material; when the substrate is a p-type silicon wafer, the functional layer is made of, but not limited to, taO x 、TiO x Or a low work function material such as MgO.
The ohmic contact layer is a majority carrier transmission area, and for n-type silicon, a low work function material or an n+ layer is adopted for transmitting majority carriers (electrons); for p-type silicon, a high work function material or p+ layer is used but not limited to, for transport of majority carrier holes.
The different front electrode areas S refer to: discs of different diameters or square discs of different side lengths are preferred, discs of different diameters d and d=0.06, 0.08,0.10,0.12,0.16,0.20,0.24cm.
The dark state I-V curve test refers to: and connecting the lines by adopting a four-line method or a two-line method, and testing to obtain a dark state I-V curve of the sample.
The total resistance R of the sample T The method specifically comprises the following steps: contact resistance R C Diffusion resistance R S And residual resistance R 0 And, a sum of which: contact resistance R C The heterojunction interface comprises a contact resistance of the heterojunction interface, a functional layer, a metal electrode and a-Si, namely, a bulk resistance of H (i); diffusion resistance R S Related to the thickness and resistivity of silicon; residual resistance R 0 Is a constant value.
The double (diode+resistor) equivalent circuit model, namely an equivalent circuit of an undoped heterojunction minority carrier end interface with a passivation layer, comprises a hole current branch and an electron current branch which are connected in parallel, wherein the hole current branch comprises a hole diode D connected in series P And hole resistance R P The electronic current branch comprises serially connected electronic diodes D N And an electronic resistor R N 。
The segmentation analysis specifically comprises the following steps: current i=i flowing through the test sample N +I P Wherein: v is the total voltage of the equivalent circuit; i 0P And I 0N Current representing saturated holes and electrons, respectively; r is R P And R is N Respectively representing the resistance encountered in hole and electron transmission, q is the unit charge quantity, k is the Boltzmann constant, and T is the absolute temperature; fitting the equivalent circuit with a dark state I-V curve for measuring the undoped heterojunction battery, and extracting the total resistance R T Is defined by the formula: />Wherein: v is applied toThe voltage of the test sample, n, is the ideality factor. The slope of the first half of the linear curve of the dV/d (lnI) -I curve is confirmed to correspond to the resistance at the time of hole transport according to the equivalent circuit, so that the slope of the first half of the linear curve is fitted to obtain the total resistance R T 。
The inverse curve of the resistance-electrode area is passed through the total resistance R of the sample T Calculated diffusion resistance R S Drawing r=r T -R S A linear curve that varies with the inverse 1/S of the electrode area.
The minority carrier end specific contact resistance is obtained by curve fitting according to the inverse of the area of the resistor-electrode to obtain the slope of a straight line, namely the minority carrier end specific contact resistance rho of the undoped heterojunction battery sample with the passivation layer C The method specifically comprises the following steps:
the photolithography method comprises the following specific steps: (1) preparing a passivation layer on the front surface of the sample, and then continuously depositing an isolation layer; (2) spin coating a layer of photoresist on the isolation layer; (3) after the photoresist is dried, a mask is used for covering the sample for ultraviolet exposure; (4) forming disc arrays with different areas and sizes through development; (5) HF was used to remove the spacers under these disks; (6) a functional layer/electrode is deposited on the exposed passivation layer using a reticle.
The masking method refers to: and (3) after preparing a passivation layer on the front surface of the sample, aligning metal masks with different area sizes to the sample to deposit a functional layer/electrode.
Technical effects
The present invention optimizes the conventional CS method because the conventional CS and TLM methods are only applicable to ohmic contact situations. The improved C.S method is further improved at the same time, and the main reason is that the improved CS method is only suitable for extracting the specific contact resistance of heterojunction transition metal oxide/n-Si minority carrier terminal. After the passivation layer (such as intrinsic amorphous silicon or silicon oxide) is introduced into the heterojunction, the conductive characteristic of the heterojunction becomes extremely complex, the quality of the minority carrier end is easily affected by the heterojunction interface characteristic, the conductivity and work function of the heterojunction material, and the like, and the problems such as S-shaped curve, poor thermal stability, and the like are easily formed. If the characteristics of the heterojunction are observed through the preparation of the full cell, the experimental period and difficulty are greatly increased, and the characteristics cannot be well characterized. The invention can effectively test the contact characteristic of the heterojunction minority carrier end with the passivation layer by adopting an extended CS method and combining an analysis method of a dark state I-V curve.
Compared with the prior art, the method can more effectively and accurately extract the contact resistance of the minority carrier end, is simple and easy to implement, and provides a new way for measuring the electrical characteristics of the doping-free heterojunction solar cell. Meanwhile, the contact resistance testing method is modified and improved again around the characteristic of doping-free heterojunction, so that the method can be effectively applied to screening of materials and research of the heterojunction, the research period is shortened, and the battery efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of the transport of dopant-free heterojunction minority carrier termination interface carriers with passivation layers;
FIG. 2 is an equivalent circuit diagram of a dopant-free heterojunction minority carrier termination interface with a passivation layer;
FIG. 3 is a schematic diagram of a sample obtained by photolithography using a metal mask;
FIG. 4 is a schematic diagram of a four probe method for testing a sample of the undoped heterojunction minority carrier terminal ratio contact resistance;
fig. 5 is the result of fitting the example device test sample (d=0.08 cm) to an equivalent circuit;
FIG. 6 is a graph of r-1/S and fitting results obtained from the device test of the example;
fig. 7 is a flowchart of an embodiment.
Detailed Description
As shown in fig. 7, this embodiment relates to a method for testing minority carrier contact resistance of a non-doped heterojunction solar cell with a passivation layer, which uses n-type silicon as a substrate and Ag/MoO x /a-Si:H(i)/An n-Si heterojunction as a sample for a minority carrier-terminated electrical resistance test of a dopant-free heterojunction cell, comprising the steps of:
step 1, selecting a single-sided polished n-type (1 omega cm) silicon wafer with the thickness of 250 mu m as a substrate, cleaning the silicon wafer by using a standard RCA process, and removing an oxide layer on the surface of the wafer by using 4% HF;
step 2, adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method to form an a-Si H (i) film with the thickness of 4nm on the n-type silicon substrate as a passivation layer;
and 3, depositing a 75nm SiNx film serving as an isolation layer on the amorphous silicon film by a Plasma Enhanced Chemical Vapor Deposition (PECVD) device.
Step 4, spin coating photoresist on the isolation layer, patterning the disc array by using a metal mask through a photolithography method, and then removing SiN under the discs by using dilute 4wt% HF solution x A film, exposing the a-Si: H (i) film (as shown in FIG. 3);
step 5, moO with a thickness of 10nm/200nm is performed by a thermal evaporation apparatus using a mask plate with a photolithographic pattern x A/Ag stack (monitored by a quartz crystal microbalance and confirmed by ellipsometry) was deposited onto the bare a-Si: H (i) film to form Ag/MoO x the/a-Si H (i)/n-Si heterojunction is shown in FIG. 4;
step 6, forming ohmic contact by depositing LiF/Al (0.5 nm/400 nm) film on the back surface of the n-type silicon through thermal evaporation;
step 7, testing dark state I-V curves corresponding to different disc areas S by using a four-probe method through a KEITHLEY2400 parameter analyzer test sample;
step 8, by taking the dark state I-V curve data of d=0.08 cm, according to s=pi d 2 And/4, obtaining a corresponding J-V curve, and fitting the obtained data with an equivalent circuit, as shown in figure 5. Obtaining a first half linear curve A of the dV/d (lnJ) -J curve according to the fitted curve, wherein points B are in phase with the dominant cavity current in the J-V curve, so that the slope of the first half linear curve of the dV/d (lnJ) -J curve can reflect the hole transfer resistance of the minority carrier end;
step 9, according to different disc surfacesThe product S is used for drawing a dV/d (lnI) -I curve, and the total resistance R is obtained according to the slope of the linear curve of the first half of curve fitting T N is the serial number of the disc, d is the diameter of the disc, R T The corresponding resistance values were obtained, and the results are shown in Table 1.
TABLE 1
| n | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
| d(cm) | 0.06 | 0.08 | 0.10 | 0.12 | 0.16 | 0.20 | 0.24 |
| R T (Ω) | 90.00 | 48.59 | 27.82 | 19.60 | 10.83 | 7.85 | 5.33 |
Step 10, the resistivity of the n-type monocrystalline silicon piece is 1 Ω cm, and the thickness is 250 μm, thus obtaining the diffusion resistance by calculation
Reuse r=r T -R S The r-value was obtained and the results are shown in Table 2.
TABLE 2
| n | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
| R S (Ω) | 5.47 | 3.57 | 2.50 | 1.84 | 1.11 | 0.74 | 0.52 |
| r(Ω) | 84.53 | 45.03 | 25.33 | 17.76 | 9.73 | 7.11 | 4.81 |
Step 11, according to s=pi d 2 And/4, calculating to obtain the reciprocal 1/S of the area of the corresponding disc of the different disc diameters d.
As shown in fig. 6, the r value obtained for each disk was sequentially changed according to the reciprocal area 1/S of each disk to form a linear curve r=a (1/S) +b. The slope of the fitted straight line a=0.256 Ω·cm is obtained 2 Therefore, the minority carrier end contact resistance rho of the undoped heterojunction cell is calculated C ＝0.256Ω·cm 2 。
Compared with the prior art, the invention adopts an extended CS method and combines an analysis method of a dark state I-V curve, and can effectively test the contact characteristic of the heterojunction minority carrier end with the passivation layer. According to the invention, an equivalent circuit diagram of the transmission model is established by combining a formula of the transmission model, and the characterization of the contact characteristic of the minority carrier end under the condition of having the passivation layer is accurately obtained by combining an experimental result.
The foregoing embodiments may be partially modified in numerous ways by those skilled in the art without departing from the principles and spirit of the invention, the scope of which is defined in the claims and not by the foregoing embodiments, and all such implementations are within the scope of the invention.
Claims (7)
1. A test method of minority carrier terminal contact resistance of solar cell is characterized in that a dV/d (lnJ) -J curve is drawn through dark state I-V curve corresponding to different front electrode areas S of samples, and sectional analysis is carried out on the curve by combining with a double (diode+resistance) equivalent circuit model, further a resistance-electrode area reciprocal curve is calculated, and the slope of a straight line obtained through curve fitting is the minority carrier terminal specific contact resistance of the undoped heterojunction cell sample with passivation layer, wherein: j is current density;
the sample is obtained by adopting a photoetching method to prepare an isolation layer, and different front electrode areas S are arranged in the functional layer in the preparation process;
the double (diode+resistor) equivalent circuit model, namely an equivalent circuit of an undoped heterojunction minority carrier end interface with a passivation layer, comprises a hole current branch and an electron current branch which are connected in parallel, wherein the hole current branch comprises a hole diode D connected in series P And hole resistance R P The electronic current branch comprises serially connected electronic diodes D N And an electronic resistor R N ；
The segmentation analysis specifically comprises the following steps: current i=i flowing through the test sample N +I P Wherein: v is the total voltage of the equivalent circuit; i 0P And I 0N Current representing saturated holes and electrons, respectively; r is R P And R is N Respectively representing the resistance encountered in hole and electron transmission, q is the unit charge quantity, k is the Boltzmann constant, and T is the absolute temperature; dark state I-V curve using equivalent circuit and measuring doping-free heterojunction cellLine-fitting, and extracting the total resistance R from T Is defined by the formula: />Wherein: v is the voltage applied to the test sample, n is the ideal factor, and the slope of the first half of the linear curve of the dV/d (lnJ) -J curve is verified to correspond to the resistance at the time of hole transport according to the equivalent circuit, so that the slope of the first half of the linear curve is fitted to obtain the total resistance R T ；
The inverse curve of the resistance-electrode area is passed through the total resistance R of the sample T And a diffusion resistance R S Drawing r=r T -R S A linear curve that varies with the inverse 1/S of the electrode area.
2. The method for testing minority carrier contact resistance of solar cell according to claim 1, wherein when the substrate is an n-type silicon wafer, the functional layer is MoO x PEDOT PSS or VO x A material; when the substrate is a p-type silicon wafer, the functional layer adopts TaO x 、TiO x Or MgO material;
the passivation layer adopts SiO x a-Si, H (i) or AlO x A material.
3. The method of claim 1, wherein the ohmic contact layer is a majority carrier transport region, and the n-type silicon is a majority carrier or electron transport region, and the n+ layer is formed of a low work function material; for the transport of majority carrier holes for p-type silicon, either a high work function material or a p+ layer is used.
4. The method for testing the minority carrier side contact resistance of the solar cell according to claim 1, wherein the different front electrode areas S are: discs of different diameters or square discs of different side lengths.
5. The method of claim 1 or 4, wherein the different front electrode areas S are discs of different diameters d and d=0.06, 0.08,0.10,0.12,0.16,0.20,0.24cm.
6. The method for testing the minority carrier side contact resistance of the solar cell according to claim 1 or 2, wherein the dark state I-V curve test means: connecting lines by adopting a four-wire method or a two-wire method, and testing to obtain a dark state I-V curve of the sample;
the total resistance R of the sample T The method specifically comprises the following steps: contact resistance R C Diffusion resistance R S And residual resistance R 0 And, a sum of which: contact resistance R C The heterojunction interface comprises a contact resistance of the heterojunction interface, a functional layer, a metal electrode and a-Si, namely, a bulk resistance of H (i); diffusion resistance R S Related to the thickness and resistivity of silicon; residual resistance R 0 Is a constant value.
7. The method for testing the minority carrier terminal contact resistance of a solar cell according to claim 6, wherein the minority carrier terminal specific contact resistance is represented by a slope of a straight line obtained by curve fitting according to the inverse of the area of the resistor-electrode, namely the minority carrier terminal specific contact resistance ρ of the undoped heterojunction cell sample with the passivation layer C The method specifically comprises the following steps: wherein: s is the area of the front electrode and d is the diameter.
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| JP2010175484A (en) * | 2009-01-31 | 2010-08-12 | Calsonic Kansei Corp | Method for estimating internal resistance component of battery and method for estimating charge capacity |
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| CN110140223A (en) * | 2016-12-12 | 2019-08-16 | 洛桑联邦理工学院 | Silicon heterogenous solar battery and manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010175484A (en) * | 2009-01-31 | 2010-08-12 | Calsonic Kansei Corp | Method for estimating internal resistance component of battery and method for estimating charge capacity |
| CN204651337U (en) * | 2012-05-29 | 2015-09-16 | 新加坡国立大学 | Hybrid solar cell |
| CN110140223A (en) * | 2016-12-12 | 2019-08-16 | 洛桑联邦理工学院 | Silicon heterogenous solar battery and manufacturing method |
Non-Patent Citations (1)
| Title |
|---|
| An Expanded Cox and Strack Method for Precise Extraction of Specific Contact Resistance of Transition Metal Oxide/n-Silicon Heterojunction;Wei Wang, Hao Lin, Zhenhai Yang, Zilei Wang, Jiajia Wang, Longfei Zhang, Mingdun Liao, Yuheng Zeng, Pingqi Gao, Baojie Yan, and Jichun Ye;IEEE JOURNAL OF PHOTOVOLTAICS;第9卷(第4期);第1113-1120页 * |
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