CN113641611A

CN113641611A - I2C interface circuit, control method thereof and electronic equipment

Info

Publication number: CN113641611A
Application number: CN202110744791.9A
Authority: CN
Inventors: 李钊
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2021-06-30
Filing date: 2021-06-30
Publication date: 2021-11-12
Anticipated expiration: 2041-06-30
Also published as: CN113641611B

Abstract

The application provides an I2C interface circuit, a control method thereof and electronic equipment, which can solve the problem that the signal state of an I2C bus is unstable due to the breakage of an FPC (flexible printed circuit) when a pull-up resistor of the I2C bus is arranged on a small board side, so as to improve the stability of a processor system of the electronic equipment. The I2C interface circuit comprises a flexible printed circuit board FPC, an I2C pull-up resistor and a detection circuit. The FPC is used to couple the I2C device to the communications interface. The I2C pull-up resistor is arranged on the small plate, and the I2C pull-up resistor is coupled with the communication interface through the FPC. The detection circuit is coupled to the communication interface to enable the processor to detect a level signal of the communication interface to determine whether the platelet is in place. When the processor determines that the platelet is in place, the communication interface is configured to couple with the I2C controller to communicate the I2C device with the I2C controller.

Description

I2C interface circuit, control method thereof and electronic equipment

Technical Field

The present application relates to the field of electronic devices, and in particular, to an I2C interface circuit, a control method thereof, and an electronic device.

Background

At present, electronic devices have more integrated circuit (I2C) devices, such as a camera (camera) in a notebook computer, a touch pad, and the like. Depending on the layout of the devices or equipment in the electronic equipment, the I2C device would typically be located on a small board of the electronic equipment, and the I2C device would communicate with the processor via the I2C bus. To ensure proper communication of the I2C device with the I2C controller in the processor, a pull-up resistor is provided on the I2C bus. Normally, the pull-up resistor is provided on the main board side, as shown in fig. 1.

As devices of electronic equipment increase, the device layout may become denser, and at this time, it may be necessary to set the pull-up resistor on the small board side. When the pull-up resistor is disposed on the panel side, if the FPC between the main board and the small board is broken, the I2C bus may not be pulled up to a high level, which may cause the signal state of the I2C bus to be unstable, and affect the stability of the processor system of the electronic device.

Disclosure of Invention

The embodiment of the application provides an I2C interface circuit, a control method thereof and electronic equipment, which can solve the problem that when a pull-up resistor of an I2C bus is arranged on a small board side, the signal state of the I2C bus is unstable due to the breakage of an FPC (flexible printed circuit), so as to improve the stability of a processor system of the electronic equipment.

In order to achieve the purpose, the technical scheme is as follows:

in a first aspect, the present application provides an I2C interface circuit. The I2C interface circuit is applied to electronic equipment. The electronic equipment comprises a main board and a small board, wherein a processor is arranged on the main board. The processor includes an I2C controller and a communication interface. The small board is provided with I2C equipment, and the I2C equipment is coupled and connected with a communication interface in the processor through I2C interface circuits. The I2C interface circuit includes a flexible printed circuit board FPC, an I2C pull-up resistor, and a detection circuit. The FPC is used to couple the I2C device to the communications interface. The I2C pull-up resistor is arranged on the small plate, and the I2C pull-up resistor is coupled with the communication interface through the FPC. The detection circuit is coupled to the communication interface to enable the processor to detect a level signal of the communication interface to determine whether the platelet is in place. When the processor determines that the platelet is in place, the communication interface is configured to couple with the I2C controller to communicate the I2C device with the I2C controller.

Based on the I2C interface circuit, when the I2C pull-up resistor of the I2C bus is arranged on the small plate, the processor can determine whether the small plate is in place by detecting a level signal of a communication interface of the processor. When the small board is in place, the communication interfaces (such as the first interface GPIO _1 and the second interface GPIO _2) of the processor are used as I2C interfaces to implement an I2C function, so as to avoid that when the small board is not installed in the electronic device, or when an FPC connecting a main board and the small board in the electronic device is broken, the I2C bus cannot be pulled up to a high level to cause signal instability of an I2C path, thereby improving the stability of a processor system of the electronic device. In addition, the I2C pull-up resistor can be arranged on the small board through the I2C interface circuit, so that the layout of electronic devices on a main board and the small board in the electronic equipment is more flexible.

In one possible implementation, the communication interface may include a first interface, a second interface, and a third interface. The I2C pull-up resistor includes a first resistor and a second resistor. The first resistor is coupled with the first interface through the FPC; the second resistor is coupled with the second interface through the FPC; the first resistor and the second resistor are both coupled to a first power source. The detection circuit is coupled to the third interface to enable the processor to detect a level signal of the third interface to determine whether the platelet is in place. When the processor determines that the platelet is in place, the first interface and the second interface are configured to couple with the I2C controller to communicate the I2C device with the I2C controller. Therefore, the I2C interface circuit can determine whether the small plate is in place through the level signal of the third interface, so that the I2C interface is not occupied, and the implementation method is simple.

In one possible implementation, the detection circuit includes a third resistor and a fourth resistor. The third resistor is located on the mainboard, one end of the third resistor is coupled with the third interface, and the other end of the third resistor is coupled with a second power supply located on the mainboard. The fourth resistor is located on the small plate, one end of the fourth resistor is in coupling connection with the third interface through the FPC, and the other end of the fourth resistor is grounded. When the level signal of the third interface is low level, the small plate is in place. When the level signal of the third interface is high, the small board is not in place. In this way, the detection circuit is realized by two resistors (the third resistor R3 and the fourth resistor R4), and the circuit is simple to realize.

In one possible implementation, the detection circuit includes a third resistor and a fourth resistor. The third resistor is located on the mainboard, one end of the third resistor is coupled with the third interface, and the other end of the third resistor is grounded. The fourth resistor is located on the small plate, one end of the fourth resistor is in coupling connection with the third interface through the FPC, and the fourth resistor is coupled with a third power supply located on the small plate. When the level signal of the third interface is high, the small plate is in place. When the level signal of the third interface is low, the small plate is not in place. In this way, the detection circuit is realized by two resistors (the third resistor R3 and the fourth resistor R4), and the circuit is simple to realize.

In a possible implementation manner, the third interface is a GPIO interface, and the processor further includes a GPIO function block; the GPIO functional module comprises a fifth resistor. The detection circuit includes a fifth resistor. One end of the fifth resistor is coupled with the third interface through the first switch, the other end of the fifth resistor is coupled with the fourth power supply, and the first switch is configured to be in a closed state. The third interface is also used for grounding through the FPC. When the level signal of the third interface is low level, the small plate is in place. When the level signal of the third interface is high, the small board is not in place. In the implementation mode, the detection circuit multiplexes a pull-up resistor of the GPIO functional module, and when a small plate is connected in the electronic equipment, the third interface presents a low-level signal; when there is no small board connection in the electronic device, the third interface presents a high level signal, and the third resistor and the fourth resistor in the above scheme can be omitted, so as to simplify the circuit structure.

In a possible implementation manner, the third interface is a GPIO interface, and the processor further includes a GPIO function block; the GPIO functional module comprises a sixth resistor. The detection circuit includes a sixth resistor. One end of the sixth resistor is coupled with the third interface through the second switch, the other end of the sixth resistor is grounded, and the second switch is configured to be in a closed state. The third interface is also used for connecting a third power supply on the small board through the FPC. When the level signal of the third interface is high, the small plate is in place. When the level signal of the third interface is low, the small plate is not in place. Similarly, in this implementation, the detection circuit multiplexes the pull-down resistor in the GPIO functional module, and when a small board is connected to the electronic device, the third interface appears as a high-level signal; when there is no small board connection in the electronic device, the third interface presents a low level signal, and the third resistor and the fourth resistor in the above scheme can be omitted, so as to simplify the circuit structure.

In a possible implementation manner, the first interface and the second interface are both GPIO interfaces, and the motherboard further includes a GPIO function module; the GPIO functional module comprises a seventh resistor and an eighth resistor. One end of the seventh resistor is coupled with the first interface through the third switch, and the other end of the seventh resistor is coupled with the fourth power supply. One end of the eighth resistor is coupled with the second interface through the fourth switch, and the other end of the eighth resistor is coupled with the fourth power supply. The third switch and the fourth switch are configured to a closed state before the processor determines whether the platelet is in place. It should be appreciated that to ensure that the GPIO interface is capable of outputting a stable signal, the GPIO interface needs to be placed at a stable level signal before the first and second interfaces are configured to couple with the I2C controller. In this implementation, by multiplexing the pull-up resistor in the GPIO functional block, the first interface and the second interface can output stable high level signals when the control switches (i.e., the third switch and the fourth switch) of the pull-up resistor are closed.

In a possible implementation manner, the first interface and the second interface are both GPIO interfaces, and the motherboard further includes a GPIO function module; the GPIO functional module comprises a ninth resistor and a tenth resistor. One end of the ninth resistor is coupled with the first interface through the fifth switch, and the other end of the ninth resistor is grounded. One end of the tenth resistor is coupled with the second interface through the sixth switch, and the other end of the tenth resistor is grounded. The fifth switch and the sixth switch are configured to a closed state before the processor determines whether the platelet is in place. In this implementation, by multiplexing the pull-down resistors in the GPIO functional blocks, the first interface and the second interface can output stable low-level signals when the control switches (i.e., the fifth switch and the sixth switch) of the pull-down resistors are closed.

In one possible implementation, the communication interface may include a first interface and a second interface. The I2C pull-up resistor is coupled with the first interface and the second interface respectively through the FPC. The detection circuit is coupled with the first interface and the second interface respectively, so that the processor detects the level signals of the first interface and the second interface to determine whether the small plate is in place. It should be understood that the above-mentioned detection circuit may multiplex the functions in the GPIO functional module, so that the processor detects the level signals of the first interface and the second interface to determine whether the platelet is in place, thereby reducing the use of the communication interface of the processor and saving the wiring resources of the FPC.

In a possible implementation manner, the first interface and the second interface are both GPIO interfaces, and the motherboard further includes a GPIO function module; the GPIO functional module comprises a ninth resistor and a tenth resistor. The detection circuit includes a ninth resistor and a tenth resistor. One end of the ninth resistor is coupled with the first interface through the fifth switch, and the other end of the ninth resistor is grounded. One end of the tenth resistor is coupled with the second interface through the sixth switch, and the other end of the tenth resistor is grounded. When the level signals of the first interface and the second interface are high level, the small plate is in place. When the level signals of the first interface and the second interface are low level, the small plate is not in place. In this implementation manner, the pull-down resistor in the GPIO function block is multiplexed, and according to the selection of the resistance values of the I2C pull-up resistor and the GPIO pull-down resistor (i.e., the ninth resistor and the tenth resistor), it can be realized that when the platelet is in place, the first interface and the second interface are in a high level state, and when the platelet is not in place, the first interface and the second interface are in a floating state and are in a low level state.

In a second aspect, the present application provides a method of controlling an I2C interface circuit. The control method is applicable to any one of the possible I2C interface circuits of the first aspect described above. The method comprises the following steps: the processor detects the level signal of the communication interface and determines whether the small plate is in place. When the processor determines that the platelet is in place, the processor configures the communication interface to couple with the I2C controller to communicate the I2C device on the platelet with the I2C controller.

In one possible implementation, the communication interface includes a first interface, a second interface, and a third interface; the I2C pull-up resistor comprises a first resistor and a second resistor; the first resistor is coupled with the first interface through the FPC; the second resistor is coupled with the second interface through the FPC; the first resistor and the second resistor are both coupled to a first power source. The processor detects a level signal of the communication interface and determines whether the platelet is in place, and the method comprises the following steps: the processor detects the level signal of the third interface and determines whether the platelet is in place. When the processor determines that the platelet is in place, the processor configures the communication interface to couple with the I2C controller to communicate the I2C device on the platelet with the I2C controller, including: when the processor determines that the platelet is in place, the processor configures the first interface and the second interface to couple with the I2C controller to communicate the I2C device on the platelet with the I2C controller.

In one possible implementation, the detection circuit includes a third resistor and a fourth resistor. The third resistor is positioned on the mainboard, one end of the third resistor is coupled with the third interface, and the other end of the third resistor is coupled with a second power supply positioned on the mainboard; the fourth resistor is located on the small plate, one end of the fourth resistor is in coupling connection with the third interface through the FPC, and the other end of the fourth resistor is grounded. The processor detects a level signal of the third interface and determines whether the platelet is in place, and the method comprises the following steps: when the processor detects that the level signal of the third interface is low level, the processor determines that the small plate is in place. When the processor detects that the level signal of the third interface is high, the processor determines that the small plate is not in place.

In one possible implementation, the detection circuit includes a third resistor and a fourth resistor; the third resistor is positioned on the mainboard, one end of the third resistor is coupled with the third interface, and the other end of the third resistor is grounded; the fourth resistor is located on the small plate, one end of the fourth resistor is in coupling connection with the third interface through the FPC, and the fourth resistor is coupled with a third power supply located on the small plate. The processor detects a level signal of the third interface and determines whether the platelet is in place, and the method comprises the following steps: when the processor detects that the level signal of the third interface is high level, the processor determines that the small plate is in place. When the processor detects that the level signal of the third interface is low level, the processor determines that the small plate is not in place.

In a possible implementation manner, the third interface is a GPIO interface, and the processor further includes a GPIO function block; the GPIO functional module comprises a fifth resistor; the detection circuit comprises a fifth resistor; one end of the fifth resistor is coupled with the third interface through the first switch, the other end of the fifth resistor is coupled with the fourth power supply, and the first switch is configured to be in a closed state; the third interface is also used for grounding through the FPC. The processor detects a level signal of the third interface and determines whether the platelet is in place, and the method comprises the following steps: when the processor detects that the level signal of the third interface is low level, the processor is used for determining that the small plate is in place. When the processor detects that the level signal of the third interface is high, the processor is used for determining that the small plate is not in place.

In a possible implementation manner, the third interface is a GPIO interface, and the processor further includes a GPIO function block; the GPIO functional module comprises a sixth resistor; the detection circuit comprises a sixth resistor; one end of the sixth resistor is coupled with the third interface through the second switch, the other end of the sixth resistor is grounded, and the second switch is configured to be in a closed state; the third interface is also used for connecting a third power supply on the small board through the FPC. The processor detects a level signal of the third interface and determines whether the platelet is in place, and the method comprises the following steps: when the processor detects that the level signal of the third interface is high level, the processor determines that the small plate is in place. When the processor detects that the level signal of the third interface is low level, the processor determines that the small plate is not in place.

In one possible implementation, before the processor determines whether the platelet is in place, the method further comprises: the processor configures the first interface and the second interface to a fixed level state.

In one possible implementation, the communication interface includes a first interface and a second interface; the I2C pull-up resistor is coupled with the first interface and the second interface respectively through the FPC. The detection circuit is coupled with the first interface and the second interface respectively;

the processor detects a level signal of the communication interface and determines whether the platelet is in place, and the method comprises the following steps: the processor detects the level signals of the first interface and the second interface and determines whether the small plate is in place.

When the processor determines that the platelet is in place, the processor configures the communication interface to couple with the I2C controller to communicate the I2C device on the platelet with the I2C controller, including: when the processor determines that the platelet is in place, the processor configures the first interface and the second interface to couple with the I2C controller to communicate the I2C device on the platelet with the I2C controller.

In a possible implementation manner, the first interface and the second interface are both GPIO interfaces, and the motherboard further includes a GPIO function module; the GPIO functional module comprises a ninth resistor and a tenth resistor; the detection circuit comprises a ninth resistor and a tenth resistor; one end of the ninth resistor is coupled with the first interface through the fifth switch, and the other end of the ninth resistor is grounded; one end of the tenth resistor is coupled with the second interface through the sixth switch, and the other end of the tenth resistor is grounded. The processor detects the level signals of the first interface and the second interface and determines whether the platelet is in place, and the method comprises the following steps: when the processor detects that the level signals of the first interface and the second interface are high level, the processor determines that the small plate is in place. When the processor detects that the level signals of the first interface and the second interface are low level, the processor determines that the small plate is not in place.

In a third aspect, the present application provides an electronic device. The electronic device comprises a motherboard, a platelet and any of the possible I2C interface circuits as described above in relation to the first aspect. The main board and the small board are connected through a flexible printed circuit board FPC in a coupling mode.

In a fourth aspect, the present application provides a computer-readable storage medium. Wherein the computer readable storage medium has stored therein instructions that, when executed on the electronic device, cause a processor of the electronic device to perform the method as in any one of the possible implementations of the second aspect above.

In a fifth aspect, the present application provides a computer program product. When the computer program product runs on the electronic device, the electronic device is caused to perform the method of any one of the possible implementations of the second aspect.

It is understood that the control method, the electronic device, the computer readable storage medium and the computer program product of the I2C interface circuit provided in the above aspects are all applied to the I2C interface circuit provided in the above aspects or associated with the I2C interface circuit provided in the above aspects, and therefore, the beneficial effects achieved by the control method, the electronic device, the computer readable storage medium and the computer program product can refer to the beneficial effects of the corresponding I2C interface circuit provided in the above aspects, and are not described herein again.

Drawings

Fig. 1 is a schematic structural diagram of an electronic device in which a pull-up resistor is provided on a main board;

FIG. 2 is a schematic diagram of an electronic device having pull-up resistors disposed on a platelet;

fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;

fig. 4 is a first schematic structural diagram of an electronic device including an I2C interface circuit according to an embodiment of the present application;

fig. 5 is a second schematic structural diagram of an electronic device including an I2C interface circuit according to an embodiment of the present application;

fig. 6 is a schematic structural diagram three of an electronic device including an I2C interface circuit according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of an electronic device including an I2C interface circuit according to an embodiment of the present application;

fig. 8 is a schematic structural diagram five of an electronic device including an I2C interface circuit according to an embodiment of the present application;

fig. 9 is a first flowchart of a control method of an I2C interface circuit according to an embodiment of the present disclosure;

fig. 10 is a second flowchart of a control method of the I2C interface circuit according to the embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.

In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.

Further, in this application, directional terms such as "upper," "lower," "left," "right," and the like may be used in a generic and descriptive sense only and not for purposes of limitation, with respect to the orientation of components in the figures, but also with respect to the orientation of components in the figures.

In the present application, unless expressly stated or limited otherwise, the term "coupled" is to be construed broadly, e.g., "coupled" may be a fixed connection, a removable connection, or an integral part; may be directly connected or indirectly connected through an intermediate. Furthermore, the terms "coupled" or "coupling" may be a manner of making electrical connections that communicate signals.

The embodiment of the application provides electronic equipment. The electronic device may be a mobile phone (mobile phone), a tablet computer (pad), a notebook computer, a Personal Digital Assistant (PDA), a television, an intelligent wearable product (e.g., a smart watch, a smart band), a Virtual Reality (VR) terminal device, an Augmented Reality (AR) terminal device, a robot camera, and the like. The embodiment of the present application does not particularly limit the specific form of the electronic device.

Generally, in order to achieve a reasonable layout of each device in the electronic apparatus, the electronic apparatus may be provided with a main board and a small board. Wherein the mainboard is provided with a processor; some peripheral devices (for example, a notebook computer, a camera and a touch pad are peripheral devices disposed on the small board) are disposed on the small board. The motherboard and the small board may be connected via a Flexible Printed Circuit (FPC) to communicate the peripheral device with the processor.

It should be noted that some of the peripheral devices in the electronic device may communicate with the processor by using an I2C bus. In the following embodiments, peripheral devices that communicate with the processor using the I2C bus are referred to as I2C devices.

It should be understood that the I2C bus is a bidirectional two-wire synchronous serial bus having two wires, a data line (SDA) and a clock line (SCL). The I2C bus enables data transfer between the processor and the I2C devices connected on the I2C bus via data lines and clock lines. The data line is used for transmitting data signals, and the clock line is used for transmitting clock signals.

The I2C bus has an Open Drain (OD) characteristic, that is, the I2C bus uses OD gate logic (i.e., wired-and logic), and the OD gate itself has no driving capability and can only output a low level and a high resistance state, and the high level is realized by pulling up an external pull-up resistor when outputting the high resistance state. If only one device on a line of the I2C bus outputs a low, the line goes low. If all devices on both lines of the I2C bus output a high impedance state, then the entire bus is high.

Therefore, in the above electronic device, in order to ensure that the I2C device normally communicates with the processor, a pull-up resistor is usually disposed in the path between the I2C device and the processor, and the pull-up resistor is generally disposed on the motherboard of the electronic device. As the functions of electronic devices and peripheral devices increase, the layout of the peripheral devices becomes denser, and sometimes it may be necessary to place pull-up resistors on small boards of electronic devices.

Fig. 2 is a schematic diagram showing the structure of an electronic device in which pull-up resistors are provided on a small board. As shown in fig. 2, the first resistor R1 and the second resistor R2 are both pull-up resistors of the I2C bus. One end of the first resistor R1 may be coupled to a clock line SCL interface of an I2C controller in the processor through an FPC, and the other end of the first resistor R1 may be coupled to a first power supply, so that when all devices on two wires of the I2C bus output a high impedance state, a clock signal is pulled up to a high level. One end of the second resistor R2 may be coupled to the data line SDA interface of the I2C controller in the processor through an FPC, and the other end of the second resistor R2 may be coupled to the first power supply, so that when all devices on two lines of the I2C bus output a high impedance state, the data signal is pulled up to a high level.

It should be understood that, in the electronic device shown in fig. 2, if the pull-up resistor is directly disposed on the small board of the electronic device, when the FPC of the small board connected to the main board is broken, the clock signal and the data signal on the I2C bus may not be pulled up to high level, so that the signal state of the I2C bus path is unstable, thereby affecting the stability of the system in the electronic device.

To this end, the embodiment of the present application provides an electronic device including an I2C interface circuit. In the electronic device, the I2C interface circuit includes a pull-up resistor and a detection circuit. The pull-up resistor is arranged on the small plate, the detection circuit is used for determining whether the small plate is in place or not, and when the small plate is in place, the pull-up resistor is configured to be coupled with the I2C controller, so that when all devices on two wires of the I2C bus output high-resistance states, clock signals and data signals are pulled up to high levels, the signal states on the I2C bus are stable, and the stability of a processor system in the electronic device is improved.

For a detailed description of the I2C interface circuit and the electronic device including the I2C interface circuit provided in the embodiments of the present application, reference may be made to the following description of the embodiments. The following describes in detail an I2C interface circuit and an electronic device including the I2C interface circuit provided in the embodiments of the present application, taking a notebook computer as an example.

Taking an electronic device as a notebook computer as an example, please refer to fig. 3, which illustrates a schematic structural diagram of a notebook computer provided in an embodiment of the present application. As shown in fig. 3, the notebook computer may include: the portable electronic device comprises a processor 310, a control chip 311, a fan 312, an external memory interface 320, an internal memory 321, a Universal Serial Bus (USB) interface 330, a charging management module 340, a power management module 341, a battery 342, a display 350, an antenna, a wireless communication module 360, an audio module 370, a speaker (i.e., a loudspeaker) 370A, a microphone 370C, an earphone interface 370B, a touch pad 380, a keyboard 390, a camera 391 and the like.

The devices (such as the processor 310, the control chip 311, the fan 312, the external memory interface 320, the internal memory 321, the USB interface 330, the charging management module 340, the power management module 341, the battery 342, the antenna, the wireless communication module 360, the audio module 370, the touch pad 380, the speaker 370A, the microphone 170C, the earphone interface 370B, the keyboard 390, the camera 391, and the like) other than the display 350 may be disposed on the base of the notebook computer. The camera 391 may be disposed on a base of the notebook computer or a frame of the display 350.

It is to be understood that the illustrated structure of the present embodiment does not constitute a specific limitation to the notebook computer. In other embodiments, a notebook computer may include more or fewer components than shown, or some components may be combined, some components may be separated, or a different arrangement of components may be used. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

Processor 310 may include one or more processing units, such as: the processor 310 may include an Application Processor (AP), a modem processor, a Graphics Processing Unit (GPU), an Image Signal Processor (ISP), a controller, a memory, a video codec, a Digital Signal Processor (DSP), a baseband processor, and/or a neural-Network Processing Unit (NPU), etc. The different processing units may be separate devices or may be integrated into one or more processors.

The controller may be the neural center and command center of a laptop computer. The controller can generate an operation control signal according to the instruction operation code and the timing signal to complete the control of instruction fetching and instruction execution.

A memory may also be provided in the processor 310 for storing instructions and data. In some embodiments, the memory in the processor 310 is a cache memory. The memory may hold instructions or data that have just been used or recycled by the processor 310. If the processor 310 needs to reuse the instruction or data, it can be called directly from the memory, avoiding repeated accesses, reducing the latency of the processor 310 and thus increasing the efficiency of the system.

In some embodiments, processor 310 may include one or more interfaces. The interface may include an integrated circuit (I2C) interface, an integrated circuit built-in audio (I2S) interface, a Pulse Code Modulation (PCM) interface, a universal asynchronous receiver/transmitter (UART) interface, a Mobile Industry Processor Interface (MIPI), a general-purpose input/output (GPIO) interface, a Subscriber Identity Module (SIM) interface, and/or a Universal Serial Bus (USB) interface, etc.

It should be understood that the interface connection relationship between the modules in this embodiment is only schematically illustrated, and does not limit the structure of the notebook computer. In other embodiments, the notebook computer may also adopt different interface connection manners or a combination of multiple interface connection manners in the above embodiments.

The charging management module 340 is configured to receive charging input from a charger (e.g., a wireless charger or a wired charger) to charge the battery 342. The power management module 341 is configured to connect the battery 342, the charging management module 340 and the processor 310. The power management module 341 receives the input from the battery 342 and/or the charging management module 340 to supply power to the components of the notebook computer.

The wireless communication function of the notebook computer can be realized by the antenna and wireless communication module 360, the modem processor, the baseband processor, and the like.

The antenna is used for transmitting and receiving electromagnetic wave signals. Each antenna in a notebook computer may be used to cover a single or multiple communication bands. Different antennas can also be multiplexed to improve the utilization of the antennas.

In some embodiments, the antenna of the notebook computer is coupled to the wireless communication module 360 so that the notebook computer can communicate with the network and other devices through wireless communication techniques. The wireless communication module 360 may provide solutions for wireless communication applied to a notebook computer, including Wireless Local Area Networks (WLANs) (e.g., wireless fidelity (Wi-Fi) networks), bluetooth (blue tooth, BT), Global Navigation Satellite Systems (GNSS), Frequency Modulation (FM), Near Field Communication (NFC), Infrared (IR), and the like.

The notebook computer can implement the display function through the GPU, the display screen 350, and the application processor, etc. The GPU is a microprocessor for image processing, and is connected to the display screen 350 and an application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 310 may include one or more GPUs that execute program instructions to generate or alter display information. The display screen 350 is used to display images, video, and the like.

The touch pad 380 has a touch sensor integrated therein. The notebook computer can receive a control command of the notebook computer from a user through the touch pad 380 and the keyboard 390.

The notebook computer can realize the shooting function through the ISP, the camera 391, the video codec, the GPU, the display screen 350, the application processor and the like. The ISP is used to process the data fed back by the camera 391. In some embodiments, the ISP may be provided in the camera 391. The camera 391 is used to capture still images or video. In some embodiments, the notebook computer may include 1 or N cameras 391, N being a positive integer greater than 1.

The external memory interface 320 may be used to connect an external memory card, such as a Micro SD card, to extend the storage capability of the notebook computer. The internal memory 321 may be used to store computer-executable program code, which includes instructions. The processor 310 executes various functional applications of the notebook computer and data processing by executing instructions stored in the internal memory 321. For example, in the embodiment of the present application, the processor 310 may execute instructions stored in the internal memory 321, and the internal memory 321 may include a program storage area and a data storage area.

The notebook computer can implement an audio function through the audio module 370, the speaker 370A, the microphone 170C, the earphone interface 370B, and the application processor. Such as music playing, recording, etc.

The audio module 370 is used to convert digital audio signals to analog audio signal outputs and also to convert analog audio inputs to digital audio signals. The audio module 370 may also be used to encode and decode audio signals. In some embodiments, the audio module 370 may be disposed in the processor 310, or some functional modules of the audio module 370 may be disposed in the processor 310.

The speaker 370A, also called a "horn", is used to convert the audio electrical signal into an acoustic signal.

Microphone 370C, also known as a "microphone," is used to convert sound signals into electrical signals.

The earphone interface 370B is used to connect a wired earphone. The headset interface 370B may be the USB interface 330, or may be a 3.5mm open mobile electronic device platform (OMTP) standard interface, a cellular telecommunications industry association (cellular telecommunications industry association of the USA, CTIA) standard interface.

It should be noted that the I2C devices such as the touch pad 380 and the camera 391 in the notebook computer are generally disposed on a small board of the notebook computer, and can communicate with the processor 310 on the main board through an I2C bus. In this case, I2C devices such as touch pad 380 and camera 391 may be coupled to the processor through I2C interface circuitry.

Fig. 4 to fig. 8 are schematic structural diagrams of an electronic device including an I2C interface circuit according to an embodiment of the present application. As shown in fig. 4 to 8, the electronic apparatus includes a main board and a small board. Wherein, a processor is arranged on the mainboard, and the processor comprises an I2C controller and a communication interface. The small board is provided with an I2C device, and the I2C device is coupled with the communication interface in the processor through an I2C interface circuit.

It should be understood that the communication interface in the above-mentioned processor may include GPIO interfaces (such as the first interface GPIO _1, the second interface GPIO _2, and the third interface GPIO _3 shown in fig. 4). According to the description above, since the I2C bus has a clock line SCL and a data line SDA, both the I2C controller and the I2C device have a clock line SCL interface and a data line SDA interface. In the following embodiments, the clock line SCL interface and the data line SDA interface in the I2C controller are collectively referred to as an I2C interface.

Typically, the GPIO interface is typically multiplexed with the I2C interface due to the number of processor interfaces. That is, the clock line SCL interface and the data line SDA interface in the I2C controller may be respectively coupled to two GPIO interfaces in the processor, such as the first interface GPIO _1 and the second interface GPIO _2 described above. When the processor needs to realize the GPIO function, the first interface GPIO _1 and the second interface GPIO _2 are used as GPIO interfaces. When the processor needs to realize the I2C function, the first interface GPIO _1 and the second interface GPIO _2 are used as the I2C interface.

For example, taking the I2C interface multiplexing the first interface GPIO _1 and the second interface GPIO _2 as an example, the I2C interface circuit includes a flexible printed circuit board (FPC), an I2C pull-up resistor, and a detection circuit.

The I2C device disposed on the electronic device platelet may be coupled to the first interface GPIO _1 and the second interface GPIO _2 of the processor through the FPC. The I2C pull-up resistor is disposed on the small board, and includes a first resistor R1 and a second resistor R2. One end of the first resistor R1 is coupled to the first interface GPIO _1 of the processor through the FPC, and the other end of the first resistor R2 is coupled to a first power supply (e.g., a 1.8V power supply located on the small board). The second resistor R2 is coupled to the second interface GPIO _2 of the processor through the FPC, and the other end of the second resistor R2 is coupled to the first power supply.

The detection circuit is coupled with the communication interface of the processor, so that the processor detects the level signal of the communication interface to determine whether the small plate is in place. When the processor determines that the platelet is in place, the first interface GPIO _1 and the second interface GPIO _2 are configured to be coupled to an I2C controller in the processor, so that an I2C device provided on the platelet communicates with the I2C controller.

It should be noted that determining whether the platelet is in place means whether the platelet is coupled to the motherboard. That is, in the case where the platelet is coupled to the motherboard, it indicates that the platelet is in place. In the case where the platelet is not coupled to the motherboard, this indicates that the platelet is not in place. For example, when a platelet is not provided in the electronic device, it may indicate that the platelet is not in place. For example, when the FPC connecting the main board and the small board in the electronic device is broken, it may indicate that the small board is not in place.

In this way, when the I2C pull-up resistor of the I2C bus is disposed on the small board, the processor may detect a level signal of the communication interface of the processor to determine whether the small board is in place, and when the small board is in place, the first interface GPIO _1 and the second interface GPIO _2 of the processor are used as I2C interfaces to implement the I2C function, so as to avoid that when the small board is not disposed in the electronic device, or when an FPC connecting the main board and the small board is broken in the electronic device, the I2C bus cannot be pulled up to a high level, which results in unstable signals of the I2C channel, thereby improving the stability of the processor system of the electronic device. In addition, the I2C interface circuit provided by the embodiment of the application can arrange the I2C pull-up resistor on the small board, so that the layout of electronic devices on a main board and the small board in the electronic equipment is more flexible.

As some embodiments of the present application, the detection circuit may be coupled to the third interface GPIO _3, so that the processor may determine whether the platelet is in place by detecting a level signal of the third interface GPIO _ 3. The following is a detailed description of the detection circuit coupled to the third interface GPIO _3 to enable the processor to determine whether the platelet is in place.

Illustratively, as shown in fig. 4, the detection circuit includes a third resistor R3 and a fourth resistor R4. The third resistor R3 is located on the motherboard, one end of the third resistor R3 is coupled to the third interface GPIO _3, and the other end of the third resistor R3 is coupled to a second power supply (e.g., a 1.8V power supply) located on the motherboard. The fourth resistor R4 is located on the small board, one end of the fourth resistor R4 is coupled to the third interface GPIO _3 through the FPC, and the other end of the fourth resistor is grounded.

In this way, the processor may detect the level signal of the third interface GPIO _3 to determine whether the platelet is in place. Specifically, when the small board is not connected to the main board of the electronic device or the FPC of the small board in the electronic device is broken, the path from the fourth resistor R4 to the third interface GPIO _3 is disconnected, in which case the processor detects that the level signal of the third interface GPIO _3 is a high level signal. When the small board is coupled with the small board through the FPC, a path from the fourth resistor R4 to the third interface GPIO _3 is turned on, and in this case, the processor detects that the level signal of the third interface GPIO _3 is a low level signal.

That is, when the processor detects that the level signal of the third interface GPIO _3 is a low level signal, the processor may determine that the platelet is in place. When the processor detects that the level signal of the third interface GPIO _3 is a high level signal, the processor may determine that the platelet is not in place.

Illustratively, in other embodiments, as shown in FIG. 5, the detection circuit includes a third resistor R3 and a fourth resistor R4. The third resistor R3 is located on the motherboard, one end of the third resistor R3 is coupled to the third interface GPIO _3, and the other end of the third resistor R3 is grounded. The fourth resistor R4 is located on the small board, one end of the fourth resistor R4 is coupled to the third interface GPIO _3 through the FPC, and the other end of the fourth resistor R4 is coupled to the third voltage located on the small board.

In this way, the processor may also determine whether the platelet is in place by detecting the level signal of the third interface GPIO _ 3. Specifically, when the small board is not connected to the main board of the electronic device or the FPC of the small board in the electronic device is broken, the path from the fourth resistor R4 to the third interface GPIO _3 is disconnected, in which case the processor detects that the level signal of the third interface GPIO _3 is a low level signal. When the small board is coupled with the small board through the FPC, a path from the fourth resistor R4 to the third interface GPIO _3 is turned on, and in this case, the processor detects that the level signal of the third interface GPIO _3 is a high level signal.

That is, when the processor detects that the level signal of the third interface GPIO _3 is a high level signal, the processor may determine that the platelet is in place. When the processor detects that the level signal of the third interface GPIO _3 is a low level signal, the processor may determine that the platelet is not in place.

It should be understood that, in the electronic devices shown in fig. 4 and fig. 5, the third interface is not limited to a GPIO interface, but may also be other types of interfaces, such as a MIPI interface, and when the third interface is a MIPI interface, if a peripheral device that communicates with the processor through the MIPI interface is provided on the platelet, and it can be detected that MIPI data is transmitted through the MIPI interface, the platelet is in place. Therefore, the embodiment of the present application does not specifically limit the type of the third interface.

It should be noted that, in order to implement the GPIO function, the electronic device may be provided with a GPIO function module in the processor. The GPIO function module comprises a pull-up resistor and a pull-down resistor for realizing GPIO functions. The pull-up resistor and the pull-down resistor for realizing the GPIO function can be coupled with the GPIO interface through a switch so as to adjust the level signal of the GPIO interface. In some cases, the level signal of the GPIO interface is required to be a high level signal, and at this time, a switch between the pull-up resistor and the GPIO interface may be closed, so that the GPIO interface outputs the high level signal. In some cases, the level signal requiring the GPIO interface is a low level signal, and at this time, a switch between the pull-down resistor and the GPIO interface may be closed, so that the GPIO interface outputs the low level signal.

When the third interface of the processor is a GPIO interface, the detection circuit in the I2C interface circuit may be implemented by a pull-up resistor or a pull-down resistor of a GPIO function, so that the third resistor R3 and the fourth resistor R4 in fig. 4 and 5 may be omitted to simplify the circuit structure.

The following two specific examples respectively illustrate the implementation of the detection circuit by the pull-up resistor or the pull-down resistor of the GPIO function.

Exemplarily, in other embodiments, as shown in fig. 6, the third interface GPIO _3 of the processor is a GPIO interface, and the processor may further include a GPIO function block. A fifth resistor R5 (i.e., a pull-up resistor of the third interface GPIO _3) may be included in the GPIO functional block. One end of the fifth resistor R5 is coupled to the third interface GPIO _3 through the first switch Q1, the other end of the fifth resistor R5 is coupled to the fourth power supply, and the first switch Q1 is configured to be in a closed state. In this embodiment, the fifth resistor R5 in the GPIO functional block may be used as a detection circuit. When the fifth resistor R5 in the GPIO functional block is used as a detection circuit, the third interface GPIO _3 is also used for grounding through the FPC.

In this way, the processor may also determine whether the platelet is in place by detecting the level signal of the third interface GPIO _ 3. Specifically, when the small board is not connected to the main board of the electronic device (i.e., when there is no FPC), or when the FPC of the small board is broken in the electronic device, the third interface GPIO _3 is not grounded, and the third interface GPIO _3 is connected to the fourth power supply through the fifth resistor R5. In this case, the processor detects that the level signal of the third interface GPIO _3 is a high level signal. When the small board is coupled with the small board through the FPC, the third interface GPIO _3 is grounded through the FPC. In this case, the processor detects that the level signal of the third interface GPIO _3 is a low level signal.

Exemplarily, in other embodiments, as shown in fig. 7, the third interface GPIO _3 of the processor is a GPIO interface, and the processor may further include a GPIO function block. A sixth resistor R6 (i.e., a pull-down resistor of the third interface GPIO _3) may be included in the GPIO functional block. One end of the sixth resistor R6 is coupled to the third interface GPIO _3 through the second switch Q2, the other end of the sixth resistor R6 is grounded, and the second switch Q2 is configured to be in a closed state. In this embodiment, the sixth resistor R6 in the GPIO functional block may be used as the detection circuit. When the sixth resistor R6 in the GPIO functional module is used as a detection circuit, the third interface GPIO _3 is also used to connect a third power supply (e.g., a 1.8V power supply) located on the small board through the FPC.

In this way, the processor may also determine whether the platelet is in place by detecting the level signal of the third interface GPIO _ 3. Specifically, when the small board is not connected to the main board of the electronic device (i.e., when there is no FPC), or when the FPC of the small board is broken in the electronic device, the third interface GPIO _3 is not connected to the power supply, and the third interface GPIO _3 is grounded through the sixth resistor R6. In this case, the processor detects that the level signal of the third interface GPIO _3 is a low level signal. When the small board is coupled with the small board through the FPC, the third interface GPIO _3 is coupled with a third power supply on the small board through the FPC. In this case, the processor detects that the level signal of the third interface GPIO _3 is a high level signal.

The above is a detailed description of the detection circuit in the I2C interface circuit. It should be further noted that, since the first interface and the second interface of the processor are GPIO interfaces, in order to ensure that the GPIO interfaces can output stable signals, before the first interface GPIO _1 and the second interface GPIO _2 are configured to be coupled with the I2C controller, signals of the GPIO interfaces need to be set to stable levels. In this case, the GPIO functional block in the processor may be utilized to implement the GPIO interface to output a stable level signal.

Illustratively, as shown in fig. 4, 5, 6 and 7, the GPIO functional block in the processor includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a tenth resistor R10. One end of the seventh resistor R7 is coupled to the first interface GPIO _1 through the third switch Q3, and the other end of the seventh resistor R7 is coupled to a fourth power supply (e.g., a 1.8V power supply on a motherboard). One end of the eighth resistor R8 is coupled to the second interface GPIO _2 through the fourth switch Q4, and the other end of the eighth resistor R8 is coupled to the fourth power supply. One end of the ninth resistor R9 is coupled to the first interface GPIO _1 through the fifth switch Q5, and the other end of the ninth resistor R9 is grounded. One end of the tenth resistor R10 is coupled to the second interface GPIO _2 through the sixth switch Q6, and the other end of the tenth resistor R10 is grounded.

Before the processor determines whether the platelet is in place, the processor may configure the third switch Q3 and the fourth switch Q4 to be in a closed state, so that the first interface GPIO _1 and the second interface GPIO _2 are both in a high state, to ensure stability of the processor system in the electronic device.

Of course, before the processor determines whether the platelet is in place, the processor may also configure the fifth switch Q5 and the sixth switch Q6 to be in a closed state, so that the first interface GPIO _1 and the second interface GPIO _2 are both in a low state, thereby ensuring the stability of the processor system in the electronic device.

It should be understood that the first power supply and the third power supply may or may not be the same 1.8V power supply located on the platelet. The second power supply and the fourth power supply may be the same 1.8V power supply on the motherboard, or may not be the same 1.8V power supply. Therefore, the embodiments of the present application are not particularly limited.

As another embodiment of the present application, the detection circuit may multiplex functions in the GPIO function block, so that the processor detects level signals of the first interface GPIO _1 and the second interface GPIO _2 to determine whether the platelet is in place.

Specifically, as shown in fig. 9, the GPIO functional block in the processor includes a ninth resistor R9 and a tenth resistor R10. One end of the ninth resistor R9 is coupled to the first interface GPIO _1 through the fifth switch Q5, and the other end of the ninth resistor R9 is grounded. One end of the tenth resistor R10 is coupled to the second interface GPIO _2 through the sixth switch Q6, and the other end of the tenth resistor R10 is grounded. In order to ensure that the GPIO interface outputs a stable signal, the processor may configure the fifth switch Q5 and the sixth switch Q6 to be in a closed state, so that both the first interface GPIO _1 and the second interface GPIO _2 are in a low level state, thereby ensuring the stability of the processor system in the electronic device.

In this case, the detection circuit may multiplex the ninth resistor R9 and the tenth resistor R10 in the GPIO functional block. The processor may detect the level signals of the first interface GPIO _1 and the second interface GPIO _2 to determine whether the platelet is in place.

The resistance of the I2C pull-up resistor is typically 2.2K-4.7K when the platelet is in place. The pull-down resistor in the GPIO functional block is generally 20K to 50K, i.e., the resistance of the ninth resistor R9 or the tenth resistor R10 is 20K to 50K. Taking the pull-down resistor in the GPIO function block as the minimum resistance value of 20K and the pull-up resistor I2C as the maximum resistance value of 4.7K as an example, after voltage division, the voltage of the first interface GPIO _1 and the second interface GPIO _2 is 1.8 × (20K/24.7K) ═ 1.45V. However, the minimum value of the high level thresholds of the first interface GPIO _1 and the second interface GPIO _2 is 0.7 × 1.8V — 1.26V. Therefore, when the small board is in place, the first interface GPIO _1 and the second interface GPIO _2 are still in a high state even if the GPIO function block is configured as a pull-down resistor.

When the small board is not in place, the first interface GPIO _1 and the second interface GPIO _2 are in a floating state, and since the GPIO functional module is configured as a pull-down resistor, the first interface GPIO _1 and the second interface GPIO _2 are still in a low level state.

In this way, when the processor detects that the first interface GPIO _1 and the second interface GPIO _2 are in the low state, the processor may determine that the platelet is not in place. When the processor detects that the first interface GPIO _1 and the second interface GPIO _2 are in a high state, the processor may determine that the platelet is in place. In the scheme, the use of the communication interface of the processor can be reduced, and the wiring resource in the FPC is saved.

In addition, the embodiment of the present application further provides a method for controlling an I2C interface circuit, which may be applied to the electronic devices shown in fig. 4 to 8. Illustratively, as shown in fig. 9, the control method of the I2C interface circuit includes S901 and S902.

S901, the processor detects a level signal of the communication interface and determines whether the small plate is in place.

In S901, how the processor determines whether the platelet is in place may refer to the related description of the electronic device shown in fig. 4 to fig. 8, which is not described herein again.

S902, when the processor determines that the platelet is in place, the processor configures the first interface GPIO _1 and the second interface GPIO _2 to couple with the I2C controller to communicate the I2C device on the platelet with the I2C controller.

Of course, as described in the foregoing embodiment, in order to ensure the stability of the signals output by the first interface GPIO _1 and the second interface GPIO _2, as shown in fig. 10, before the control method of the I2C interface circuit performs the foregoing S901, S901a may be further included.

S901a, the processor configures the first interface GPIO _1 and the second interface GPIO _2 to be in a fixed level state.

Specifically, the GPIO function block may be implemented in the electronic devices shown in fig. 4 to 8. For example, the third switch Q3 between the seventh resistor R7 and the first interface GPIO _1 may be closed, the fourth switch Q4 between the eighth resistor R8 and the second interface GPIO _2 may be closed, or the fifth switch Q5 between the ninth resistor R9 and the first interface GPIO _1 may be closed, and the sixth switch Q4 between the tenth resistor R10 and the second interface GPIO _2 may be closed.

That is, the above S901a may include that the processor may configure the third switch Q3 and the fourth switch Q4 to be in a closed state, so that the first interface GPIO _1 and the second interface GPIO _2 are both in a high level state, so as to ensure the stability of the processor system in the electronic device.

The above S901a may also include that the processor may configure the fifth switch Q5 and the sixth switch Q6 to be in a closed state, so that both the first interface GPIO _1 and the second interface GPIO _2 are in a low level state, so as to ensure stability of a processor system in the electronic device.

Embodiments of the present application further provide a computer storage medium, where the computer storage medium includes computer instructions, and when the computer instructions are run on the electronic device, the electronic device is caused to perform each function or step performed by a processor in the foregoing method embodiments.

The embodiment of the present application further provides a computer program product, which when running on a computer, causes the computer to execute each function or step executed by the mobile phone in the above method embodiments.

Through the above description of the embodiments, it is clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely used as an example, and in practical applications, the above function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device may be divided into different functional modules to complete all or part of the above described functions. For the specific working processes of the system, the apparatus and the unit described above, reference may be made to the corresponding processes in the foregoing method embodiments, and details are not described here again.

Each functional unit in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or make a contribution to the prior art, or all or part of the technical solutions may be implemented in the form of a software product stored in a storage medium and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) or a processor to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: flash memory, removable hard drive, read only memory, random access memory, magnetic or optical disk, and the like.

The above description is only a specific implementation of the embodiments of the present application, but the scope of the embodiments of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the embodiments of the present application should be covered by the scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.

Claims

1. An I2C interface circuit is applied to an electronic device, wherein the electronic device comprises a mainboard and a small plate, and a processor is arranged on the mainboard; the processor comprises an I2C controller and a communication interface;

the small board is provided with an I2C device, and the I2C device is coupled with the communication interface in the processor through the I2C interface circuit;

the I2C interface circuit comprises a flexible printed circuit board (FPC), an I2C pull-up resistor and a detection circuit; the FPC is used for coupling the I2C equipment to the communication interface;

the I2C pull-up resistor is arranged on the small plate, and the I2C pull-up resistor is coupled with the communication interface through the FPC;

the detection circuit is coupled with the communication interface to enable the processor to detect a level signal of the communication interface and determine whether the small plate is in place;

when the processor determines that the platelet is in place, the communication interface is configured to couple with the I2C controller to communicate the I2C device with the I2C controller.

2. The I2C interface circuit of claim 1, wherein the communication interface comprises a first interface, a second interface, and a third interface; the I2C pull-up resistor comprises a first resistor and a second resistor; the first resistor is coupled with the first interface through the FPC; the second resistor is coupled with the second interface through the FPC; the first resistor and the second resistor are both coupled with a first power supply;

the detection circuit is coupled with the third interface, so that the processor detects a level signal of the third interface to determine whether the small plate is in place;

when the processor determines that the platelet is in place, the first interface and the second interface are configured to couple with the I2C controller to communicate the I2C device with the I2C controller.

3. The I2C interface circuit of claim 2, wherein the detection circuit includes a third resistor and a fourth resistor; the third resistor is positioned on the mainboard, one end of the third resistor is coupled with the third interface, and the other end of the third resistor is coupled with a second power supply positioned on the mainboard;

the fourth resistor is positioned on the small plate, one end of the fourth resistor is coupled and connected with the third interface through the FPC, and the other end of the fourth resistor is grounded;

when the level signal of the third interface is low level, the small plate is in place;

when the level signal of the third interface is high level, the small plate is not in place.

4. The I2C interface circuit of claim 2, wherein the detection circuit includes a third resistor and a fourth resistor; the third resistor is positioned on the mainboard, one end of the third resistor is coupled with the third interface, and the other end of the third resistor is grounded;

the fourth resistor is positioned on the small plate, one end of the fourth resistor is coupled and connected with the third interface through the FPC, and the fourth resistor is coupled with a third power supply positioned on the small plate;

when the level signal of the third interface is high level, the small plate is in place;

when the level signal of the third interface is low level, the small plate is not in place.

5. The I2C interface circuit of claim 2, wherein the third interface is a GPIO interface, the processor further comprising a GPIO function block; the GPIO functional module comprises a fifth resistor;

the detection circuit comprises the fifth resistor;

one end of the fifth resistor is coupled with the third interface through a first switch, the other end of the fifth resistor is coupled with a fourth power supply, and the first switch is configured to be in a closed state;

the third interface is also used for grounding through the FPC;

6. The I2C interface circuit of claim 2, wherein the third interface is a GPIO interface, the processor further comprising a GPIO function block; the GPIO functional module comprises a sixth resistor;

the detection circuit comprises the sixth resistor;

one end of the sixth resistor is coupled with the third interface through a second switch, the other end of the sixth resistor is grounded, and the second switch is configured to be in a closed state;

the third interface is also used for connecting a third power supply on the small plate through the FPC;

7. The I2C interface circuit of any one of claims 2-6, wherein the first interface and the second interface are both GPIO interfaces, the motherboard further comprises a GPIO function module; the GPIO functional module comprises a seventh resistor and an eighth resistor;

one end of the seventh resistor is coupled with the first interface through a third switch, and the other end of the seventh resistor is coupled with a fourth power supply;

one end of the eighth resistor is coupled with the second interface through a fourth switch, and the other end of the eighth resistor is coupled with a fourth power supply;

the third switch and the fourth switch are configured to be in a closed state before the processor determines whether the platelet is in place.

8. The I2C interface circuit of any one of claims 2-6, wherein the first interface and the second interface are both GPIO interfaces, the motherboard further comprises a GPIO function module; the GPIO functional module comprises a ninth resistor and a tenth resistor;

one end of the ninth resistor is coupled with the first interface through a fifth switch, and the other end of the ninth resistor is grounded;

one end of the tenth resistor is coupled with the second interface through a sixth switch, and the other end of the tenth resistor is grounded;

the fifth switch and the sixth switch are configured to a closed state before the processor determines whether the platelet is in place.

9. The I2C interface circuit of claim 1, wherein the communication interface comprises a first interface and a second interface; the I2C pull-up resistor is coupled with the first interface and the second interface respectively through the FPC;

the detection circuit is coupled with the first interface and the second interface respectively, so that the processor detects the level signals of the first interface and the second interface to determine whether the small plate is in place.

10. The I2C interface circuit of claim 9, wherein the first interface and the second interface are both GPIO interfaces, the motherboard further comprising a GPIO function module; the GPIO functional module comprises a ninth resistor and a tenth resistor; the detection circuit comprises the ninth resistor and the tenth resistor;

when the level signals of the first interface and the second interface are high levels, the small plate is in place;

when the level signals of the first interface and the second interface are low level, the small plate is not in place.

11. A control method of an I2C interface circuit, which is applied to the I2C interface circuit as claimed in any one of claims 1 to 10;

the method comprises the following steps:

the processor detects a level signal of the communication interface and determines whether the small plate is in place;

when the processor determines that a platelet is in place, the processor configures the communication interface to couple with the I2C controller to communicate I2C devices on the platelet with the I2C controller.

12. The method of claim 11, wherein the communication interface comprises a first interface, a second interface, and a third interface; the I2C pull-up resistor comprises a first resistor and a second resistor; the first resistor is coupled with the first interface through the FPC; the second resistor is coupled with the second interface through the FPC; the first resistor and the second resistor are both coupled with a first power supply;

the processor detects a level signal of the communication interface and determines whether the platelet is in place, including:

the processor detects a level signal of the third interface and determines whether the small plate is in place;

when the processor determines that a platelet is in place, the processor configures the communication interface to couple with the I2C controller to communicate I2C devices on the platelet with the I2C controller, including:

when the processor determines that a platelet is in place, the processor configures the first interface and the second interface to couple with the I2C controller to communicate I2C devices on the platelet with the I2C controller.

13. The control method according to claim 12, wherein the detection circuit includes a third resistor and a fourth resistor; the third resistor is positioned on the mainboard, one end of the third resistor is coupled with the third interface, and the other end of the third resistor is coupled with a second power supply positioned on the mainboard; the fourth resistor is positioned on the small plate, one end of the fourth resistor is coupled and connected with the third interface through the FPC, and the other end of the fourth resistor is grounded;

the processor detects a level signal of the third interface and determines whether the platelet is in place, including:

when the processor detects that the level signal of the third interface is low level, the processor determines that the small plate is in place;

when the processor detects that the level signal of the third interface is high level, the processor determines that the small plate is not in place.

14. The control method according to claim 12, wherein the detection circuit includes a third resistor and a fourth resistor; the third resistor is positioned on the mainboard, one end of the third resistor is coupled with the third interface, and the other end of the third resistor is grounded; the fourth resistor is positioned on the small plate, one end of the fourth resistor is coupled and connected with the third interface through the FPC, and the fourth resistor is coupled with a third power supply positioned on the small plate;

when the processor detects that the level signal of the third interface is high level, the processor determines that the small plate is in place;

when the processor detects that the level signal of the third interface is low level, the processor determines that the small plate is not in place.

15. The control method of claim 12, wherein the third interface is a GPIO interface, and wherein the processor further comprises a GPIO function block; the GPIO functional module comprises a fifth resistor; the detection circuit comprises the fifth resistor; one end of the fifth resistor is coupled with the third interface through a first switch, the other end of the fifth resistor is coupled with a fourth power supply, and the first switch is configured to be in a closed state; the third interface is also used for grounding through the FPC;

when the processor detects that the level signal of the third interface is low level, the processor is used for determining that the small plate is in place;

when the processor detects that the level signal of the third interface is high level, the processor is used for determining that the small plate is not in place.

16. The control method of claim 12, wherein the third interface is a GPIO interface, and wherein the processor further comprises a GPIO function block; the GPIO functional module comprises a sixth resistor; the detection circuit comprises the sixth resistor; one end of the sixth resistor is coupled with the third interface through a second switch, the other end of the sixth resistor is grounded, and the second switch is configured to be in a closed state; the third interface is also used for connecting a third power supply on the small plate through the FPC;

17. The method of any one of claims 12 to 16, wherein before the processor determines whether the platelet is in place, the method further comprises:

the processor configures the first interface and the second interface to a fixed level state.

18. The control method according to claim 11, wherein the communication interface includes a first interface and a second interface; the I2C pull-up resistor is coupled with the first interface and the second interface respectively through the FPC;

the detection circuit is coupled with the first interface and the second interface respectively;

the processor detects level signals of the first interface and the second interface and determines whether the small plate is in place;

19. The control method according to claim 18, wherein the first interface and the second interface are both GPIO interfaces, and the motherboard further comprises a GPIO function module; the GPIO functional module comprises a ninth resistor and a tenth resistor; the detection circuit comprises the ninth resistor and the tenth resistor; one end of the ninth resistor is coupled with the first interface through a fifth switch, and the other end of the ninth resistor is grounded; one end of the tenth resistor is coupled with the second interface through a sixth switch, and the other end of the tenth resistor is grounded;

the processor detects level signals of the first interface and the second interface and determines whether the small plate is in place, and the method comprises the following steps:

when the processor detects that the level signals of the first interface and the second interface are high level, the processor determines that the small plate is in place;

when the processor detects that the level signals of the first interface and the second interface are low level, the processor determines that the small plate is not in place.

20. An electronic device, characterized in that the electronic device comprises a main board, a small board and the I2C interface circuit of any one of claims 1-10, wherein the main board and the small board are connected by flexible printed circuit board FPC coupling.

21. A computer-readable storage medium having stored therein instructions that, when executed on an electronic device, cause a processor of the electronic device to perform the method of any of claims 11-19.