CN113641541A

CN113641541A - Chip testing method, device, chip and storage medium

Info

Publication number: CN113641541A
Application number: CN202110851074.6A
Authority: CN
Inventors: 李晨; 肖珂; 布恩辉; 李健强
Original assignee: Xi'an Xinhai Microelectronics Technology Co ltd
Current assignee: Xi'an Xinhai Microelectronics Technology Co ltd
Priority date: 2021-07-27
Filing date: 2021-07-27
Publication date: 2021-11-12

Abstract

The embodiment of the application discloses a chip testing method, a device, a chip and a storage medium, wherein the chip testing method is applied to the chip, the chip comprises a storage body and a testing unit which are electrically connected with each other, and the chip testing method comprises the steps of obtaining first verification information; if the read-write authority of the memory bank is controlled to be in an open state based on the first verification information, a test enabling signal is sent to the test unit through the memory bank; and controlling the chip to enter a test state according to the test enable signal. Through the implementation of the embodiment, the test unit is controlled to enter the test state through the memory bank, and because the memory bank in the chip is electrically connected with the test unit, pins for enabling the test unit to enter the test state do not need to extend outside the chip, so that the number of pins of a peripheral required by the chip applying the chip test method provided by the embodiment is reduced, the cost for producing the chip is reduced, meanwhile, the size of an electronic product is convenient to reduce, and the difficulty in product popularization is reduced.

Description

Chip testing method, device, chip and storage medium

Technical Field

The application relates to the technical field of chip testing, in particular to a chip testing method, a chip testing device, a chip and a storage medium.

Background

In recent years, with the continuous development of science and technology, the application of electronic products is more and more extensive, and the chip is an important component of the electronic products and has attracted unprecedented attention in the market. In order to ensure that the functions of the chip meet the design requirements, a testing procedure is usually added before the chip is applied to the electronic product to verify the functions of the chip, thereby effectively reducing the defects generated when the electronic product is actually applied. In the prior art, in order to meet the test requirements of a chip, it is generally required to provide a dedicated test pin for each module (e.g., a processor, a memory, a test unit, etc.) in the chip, and an external tester tests the chip by connecting the pin. Although the test method in the prior art can meet the test requirement, the adoption of the test method causes excessive pins in the chip, so that the cost for producing the chip is higher, the size of the electronic product is not reduced, and the product popularization is not facilitated under the condition that the electronic product is miniaturized in the market.

Disclosure of Invention

An embodiment of the present invention provides a chip testing method, a chip testing device, a chip and a storage medium, so as to solve the above problems. The embodiment of the application realizes the aim through the following technical scheme.

In a first aspect, an embodiment of the present application provides a chip testing method, where the chip testing method is applied to a chip, where the chip includes a memory bank and a testing unit, which are electrically connected to each other, and the chip testing method includes: acquiring first verification information; if the read-write authority of the memory bank is controlled to be in an open state based on the first verification information, a test enabling signal is sent to the test unit through the memory bank; and controlling the chip to enter a test state according to the test enable signal.

In a second aspect, an embodiment of the present application provides a chip testing apparatus, where the chip testing apparatus is applied to a chip, the chip includes a memory bank and a testing unit, which are electrically connected to each other, and the chip testing apparatus includes a first verification information obtaining module, a test enabling signal sending module, and a testing module. The first verification information acquisition module is used for acquiring first verification information. The test enabling signal sending module is used for sending a test enabling signal to the test unit through the memory bank if the read-write permission of the memory bank is controlled to be in an open state based on the first verification information. The test module is used for controlling the chip to enter a test state according to the test enable signal

In a third aspect, an embodiment of the present application provides a chip, where the chip includes a memory bank and a test unit electrically connected to each other, and the chip further includes: one or more processors; one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the steps of the chip testing method described above.

In a fourth aspect, the present application provides a computer-readable storage medium, where a computer program is stored, and the computer program may be called by a processor to execute the steps of the chip testing method.

Compared with the prior art, in the chip testing method, the device, the chip and the storage medium provided by the embodiment, the first verification information can be obtained through the storage body, the read-write permission of the storage body is controlled to be opened based on the first verification information, and the test enabling signal is sent to the test unit, so that the test unit can enter the test state, when the test unit tests, the test unit can also read and write data in the storage body, the test unit is controlled to enter the test state through the storage body, because the storage body and the test unit in the chip are electrically connected with each other, a pin for enabling the test unit to enter the test state does not need to extend from the outside of the chip, thereby reducing peripheral pins required by the chip applying the chip testing method provided by the embodiment, reducing the cost for producing the chip, being convenient for reducing the volume of electronic products, and under the condition that the electronic products approach to miniaturization in the market, is also beneficial to the popularization of products.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive exercise.

Fig. 1 shows a flow chart of a chip testing method provided by an embodiment of the present application.

Fig. 2 shows a module schematic diagram of a chip in the chip testing method provided by the embodiment of the present application.

Fig. 3 is a flow chart illustrating a first verification information matching process in the method shown in fig. 1.

FIG. 4 is a flow chart illustrating a process for entering a test state in the method of FIG. 1.

Fig. 5 shows a further schematic flow chart of the method of fig. 1 for entering a test state.

Fig. 6 is a flow chart illustrating a mode selection signal in the method shown in fig. 5.

FIG. 7 is a flow chart illustrating the exit from the test state in the method of FIG. 1.

FIG. 8 is a flow chart illustrating a process of controlling the chip to exit the test state based on the second verification information in the method shown in FIG. 7.

Fig. 9 shows a functional block diagram of a chip testing apparatus according to an embodiment of the present application.

Fig. 10 shows a functional block diagram of a chip according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

At present, in an existing chip testing method, a wafer-testing (CP) is usually performed only before a packaging process is performed, after a wafer is packaged, a test enable bit is not led out, and a final-test (FT) stage after the packaging does not enter a test mode, so that a user cannot enter the test stage after the chip is packaged, and private data of the chip cannot be obtained through the chip testing, thereby realizing data protection. Although this kind of mode has realized data protection, because of this kind can't test the chip after the encapsulation, in the packaging process, if the chip receives the impact, produce the damage after, can't filter the chip through the test, probably lead to the unqualified chip of quality to flow outward, the normal operating of the electronic product that is equipped with this chip is influenced. Further, in order to ensure data security and also to test the chip after packaging, a dedicated test pin may be provided for each module (e.g., processor, memory, test unit, etc.) in the chip, and an external tester may test the chip by connecting the pins. This kind of mode of setting up special test pin can satisfy the test demand, but, adopts this kind of test method to lead to the pin in the chip too much for the cost of producing this chip is higher, is unfavorable for reducing the electronic product volume simultaneously, and electronic product is in the market under the miniaturized condition of approaching, also does not benefit to the product and promotes.

In order to solve the above-described problems, the inventors of the present application continued research and development, and made an effort to design a new chip testing method that can reduce the number of pins required in a chip. Based on this, the inventor of the present application proposes a chip testing method, which is applied to a chip including a bank and a testing unit electrically connected to each other, the chip testing method including: acquiring first verification information; if the read-write authority of the memory bank is controlled to be in an open state based on the first verification information, a test enabling signal is sent to the test unit through the memory bank; and controlling the chip to enter a test state according to the test enable signal. By implementing the chip testing method, the first verification information can be acquired through the memory bank, the read-write permission of the memory bank is controlled to be opened based on the first verification information, and the test enabling signal is sent to the test unit, so that the test unit can enter a test state, and the test unit is controlled to enter the test state through the memory bank. Because the memory body in the chip is electrically connected with the test unit, pins for enabling the test unit to enter a test state do not need to extend out of the chip, so that peripheral pins needed by the chip are reduced, the cost for producing the chip is reduced, the size of an electronic product is convenient to reduce, the product popularization is facilitated under the condition that the electronic product tends to be miniaturized in the market, in addition, the test unit is indirectly controlled through the first verification information, the process of opening the read-write permission of the memory body and the process of controlling the test unit to enter the test state do not need to be independently executed, the process of enabling the chip to enter the test state is reduced, the test process of the chip is more convenient, and the time for testing the chip is reduced.

Specific chip testing methods are described below, and embodiments of the present application will be described in detail with reference to the accompanying drawings.

Referring to fig. 1, the present disclosure provides a chip testing method, where the chip testing method is applied to a chip 100, the chip 100 may include a memory bank 101 and a testing unit 102 (shown in fig. 2) electrically connected to each other, and the chip testing method may include the following steps S11 to S13.

Step S11: first authentication information is acquired.

In the present embodiment, the chip 100 may include a semiconductor provided with an integrated circuit. The integrated circuit may include an analog integrated circuit, a digital integrated circuit, a mixed signal integrated circuit, and the like, and the type of the integrated circuit is not particularly limited. The semiconductor may include silicon, germanium, gallium arsenide, and the like, and the material properties of the semiconductor are not particularly limited.

In this embodiment, memory banks 101 may be used to store information. The information may include regular data that the chip 100 needs to extract in the data processing process, for example, the regular data may be data that needs to be called when the chip 100 is tested for its function, data that needs to be called when the chip 100 is put into practical use, and the like; the information may also include private data of the chip 100, which may be data that is not modifiable by the user, data that is not retrievable by the user, etc., and the specific content of the information is not particularly limited herein. In addition, a safety region may be disposed in the memory bank 101, the safety region may be electrically connected to the test unit 102, the safety region may store data required during the test of the test unit 102, and the test unit 102 may obtain the data required during the test from the safety region during the test of the test unit 102.

In this embodiment, the test unit 102 may be a unit for testing the chip 100, and may verify the designed chip 100. The test unit 102 may include a unit for implementing tests of the chip 100 for functionality, performance, reliability, etc. It should be noted that, in the test process, the test unit 102 in this embodiment may obtain data related to the test from the memory bank 101, or may not obtain data from the memory bank 101, and a source of the test unit 102 obtaining data is not particularly limited herein. For example, when the test unit 102 acquires data related to a test from the memory bank 101, the data may be acquired from a secure area in the memory bank 101 or may be acquired from a portion other than the secure area in the memory bank 101. When the test unit 102 does not obtain data from the memory bank 101, the test unit 102 may obtain data from outside the chip 100, or may obtain data from a memory unit of the test unit 102 that is previously set for a test.

It should be noted that, when the storage 101 is provided with a secure area, in the test process of the test unit 102, if only the read-write permission of the secure area is controlled to be opened, data outside the secure area in the storage 101 can be effectively prevented from being leaked in the test process, so that the security of the private data in the test process is effectively improved.

In this embodiment, the first authentication information may include information for opening the read/write authority of the storage 101. For example, the first verification information may be information for verifying whether to open the read/write authority of all data stored in the memory bank 101, and may also be information for verifying whether to open the read/write authority of a secure area in the memory bank 101. In addition, the first authentication information may be binary information, octal information, decimal information, hexadecimal information, etc., and the expression form of the first authentication information is not particularly limited herein.

In some examples, the first authentication information may be obtained from a device other than the chip 100. For example, when the tester needs to test the chip 100, first verification information may be sent to the chip 100 for opening the read/write permission of the memory bank 101. When the first verification information is verified to pass, the read-write permission of all data stored in the storage body 101 may be controlled to be opened, or the read-write permission of the secure area in the storage body 101 may be controlled to be opened. The test machine may include a machine for sending test information to the chip 100 and obtaining a test result generated by the chip 100 according to the test information.

Step S12: if the read/write authority of the memory bank 101 is controlled to be in an on state based on the first verification information, a test enable signal is transmitted to the test unit 102 through the memory bank 101.

In this embodiment, the read/write authority of the memory bank 101 has an on state and an off state. When the read-write permission of all the data in the memory bank 101 is in the open state, the test unit 102 may access all the data stored in the memory bank 101; when the read/write authority of the memory bank 101 is in the off state, the test unit 102 cannot access the data stored in the memory bank 101. In addition, when the read-write authority of the secure area in the storage body 101 is controlled to be in an open state based on the first authentication information, the test unit 102 may access data stored in the secure area; when the read-write authority of the secure area in the storage 101 is controlled to be in the closed state based on the first authentication information, the test unit 102 cannot access the data stored in the secure area.

In this embodiment, the test enable signal may include information that enables the test unit 102 to enter a test state. Specifically, the test enable signal may be binary information, octal information, decimal information, hexadecimal information, or the like, and the representation form of the test enable signal is not particularly limited herein. For example, if the read/write permission of the memory bank 101 is in an on state, the memory bank 101 may send a high level signal to the test unit 102, where the high level signal may be regarded as a test enable signal; if the read/write permission of the memory bank 101 is in the off state, the memory bank 101 may send a low signal to the test unit 102.

In addition, when the memory bank 101 is provided with a secure area, a test enable signal may be transmitted to the test unit 102 through the secure area when the first authentication information controls the read/write authority of the secure area in the memory bank 101 to be in an open state.

Step S13: the chip 100 is controlled to enter a test state according to the test enable signal.

In this embodiment, the test status may include a status that the test pins in the test unit 102 are able to receive test information sent by the test machine. The test pins may include pins for receiving information sent by the test machine and/or pins for sending information to the test machine. For example, when the test unit 102 receives the test enable signal, the test pins in the test unit 102 are in an active state, so that the test unit 102 and the tester perform information transmission to implement testing on the chip 100.

In this embodiment, through the implementation of the above steps S11 to S13, the first verification information can be obtained through the memory 101, the read/write permission of the memory 101 is controlled to be opened based on the first verification information, and the test enable signal is sent to the test unit 102, so that the test unit 102 can enter the test state, and the test unit 102 is controlled to enter the test state through the memory 101, and because the memory 101 and the test unit 102 in the chip 100 are electrically connected to each other, there is no need to extend a pin for causing the test unit 102 to enter the test state outside the chip 100, thereby reducing peripheral pins required by the chip 100 to which the chip testing method provided by this embodiment is applied, reducing the cost for producing the chip 100, facilitating the reduction of the volume of electronic products, and facilitating the product popularization in the case that electronic products in the market approach to miniaturization, in addition, the test unit 102 can be indirectly controlled through the first verification information, so that the process of opening the read-write permission of the memory 101 and the process of controlling the test unit 102 to enter the test state do not need to be executed independently, the process of the chip 100 entering the test state is reduced, the test process of the chip 100 is more convenient, and the time for testing the chip 100 is reduced.

Further, the embodiment of the present application also provides a chip testing method, the chip testing method is applied to the chip 100, the chip 100 may include the memory bank 101 and the test unit 102 electrically connected to each other, and the chip testing method may include steps S21 to S23. The chip testing method provided in this embodiment may include the same or similar steps as those in the above embodiments, and for the execution of the same or similar steps, reference may be made to the foregoing description, and the description is not repeated.

Step S21: first authentication information is acquired.

Step S22: if the read/write authority of the memory bank 101 is controlled to be in an on state based on the first verification information, a test enable signal is transmitted to the test unit 102 through the memory bank 101.

Further, in order to prevent the read/write authority of the storage 101 from being illegally opened, the first authentication information may be matched with pre-stored information, and whether to open the read/write authority may be determined based on a matching result, as shown in fig. 3, and the above step S22 may include the following steps S221 to S222.

Step S221: and matching the first verification information with first preset verification information.

In this embodiment, the first preset verification information may include information for verifying whether the first verification information conforms to the permission to open the read-write operation. The first preset authentication information may be binary information, octal information, decimal information, hexadecimal information, etc., and the expression form of the first preset authentication information should be the same as that of the first authentication information.

In this embodiment, the matching form between the first verification information and the first preset verification information is not particularly limited. For example, the first verification information and the first preset verification information may be compared, if the first verification information is the same as the first preset verification information, it is determined that the first verification information is successfully matched with the first preset verification information, and if the first verification information is different from the first preset verification information, it is determined that the first verification information is unsuccessfully matched with the first preset verification information; or, the first verification information and the first preset verification information may be subjected to an and gate operation, if the result of the and gate operation is "1", it is determined that the first verification information and the first preset verification information are successfully matched, and if the result of the and gate operation is "0", it is determined that the first verification information and the first preset verification information are unsuccessfully matched.

In this embodiment, the first preset authentication information may be stored in the memory bank 101 in advance. The first preset authentication information may be stored in a secure area of the memory bank 101, or may be stored in a portion of the memory bank 101 outside the secure area, where the storage location of the first preset authentication information is not particularly limited.

Step S222: if the first verification information is successfully matched with the first preset verification information, the read-write permission of the memory 101 is opened.

In this embodiment, if the first verification information is successfully matched with the first preset verification information, the read-write permission of all data in the storage body 101 may be opened, and the read-write permission of the secure area in the storage body 101 may also be opened, which may be specifically set based on an actual scene.

In some examples, the storage body 101 may be set to a plurality of areas, each area stores corresponding first preset verification information, and if the first verification information is successfully matched with the first preset verification information stored in a certain area, the read-write permission of the area corresponding to the first preset verification information in the storage body 101 may be opened.

In this embodiment, through the implementation of the above steps S221 to S222, the first verification information may be matched with the pre-stored information, and whether to open the read/write permission is determined based on the matching result, so as to effectively prevent the read/write permission of the storage 101 from being illegally opened.

Step S23: the chip 100 is controlled to enter a test state according to the test enable signal.

In order to further reduce the number of pins provided outside the chip 100, the target test mode may be obtained based on the test enable signal, and the chip 100 may be tested, so that there is no need to provide a mode selection pin for receiving a test machine transmission outside the chip 100, as shown in fig. 4, and the above step S23 may include the following steps S231 to S233.

Step S231: the mode selection signal is derived from the test enable signal.

In this embodiment, the test enable signal may include a mode selection signal, and may also include a mode selection signal and a signal for controlling the chip 100 to enter a test state. In some examples, when the test enable signal includes the mode selection signal, the chip 100 may be directly controlled to enter a state and the mode selection signal may be acquired from the test enable signal. When the test enable signal includes the mode selection signal and the signal for controlling the chip 100 to enter the test state, it may be determined whether the test enable signal includes the signal for controlling the chip 100 to enter the test state, and if the test enable signal includes the signal, the chip 100 is controlled to enter the state, and the mode selection signal is obtained from the test enable signal.

Step S232: and determining a target test mode according to the corresponding relation between the mode selection signal and the test mode.

In the present embodiment, the mode selection signal may include binary information, octal information, decimal information, hexadecimal information, etc., and the expression form of the mode selection signal is not particularly limited herein.

In this embodiment, a mapping relationship between the mode selection signal and the test mode may be preset, so that when the mode selection signal is acquired, the test mode may be determined based on the mapping relationship and may be set as the target test mode. In the following table (1), for example, when the obtained mode selection signal is "1", the test pattern "a" is set as the target test pattern, when the mode selection signal is "2", the test pattern "B" is set as the target test pattern, and when the mode selection signal is "3", the test pattern "C" is set as the target test pattern.

Mode selection signal	Test mode
		1	A
2	B
		3	C

Watch (1)

Step S233: the chip 100 is tested in the target test mode.

In this embodiment, through the implementation of the steps S231 to S233, the target test mode can be obtained based on the test enable signal, and the chip 100 is tested, so that a mode selection pin for receiving the test signal sent by the test machine does not need to be arranged outside the chip 100, further pins arranged outside the chip 100 are reduced, the cost for producing the chip 100 is reduced, and meanwhile, the size of the electronic product is convenient to reduce, and the product popularization is facilitated under the condition that the electronic product tends to be miniaturized in the market.

Further, in order to obtain an expected test result, the test patterns of the chip 100 may be divided in advance, a target test pattern is obtained from the test patterns, and the chip 100 is tested based on the target test pattern; the chip 100 may also include at least one multiplexing pin disposed on the test unit 102. As shown in fig. 5, the chip testing method provided in this embodiment may further include the following steps S24 to S26.

Step S24: a mode selection signal input via the multiplexing pin is acquired.

In this embodiment, the multiplexing pin may include a pin for acquiring the mode selection signal at one time and for acquiring the test information at another time. That is, after the mode selection signal is acquired through the multiplexing pin, test information may be acquired based on the multiplexing pin to test the chip 100. In addition, the multiplexing pin may be a passive pin, an input pin, a bidirectional pin, etc., and the type of the service pin is not particularly limited herein.

In this embodiment, the mode selection signal may be a signal indicative of a selection of the test mode. In addition, the mode selection signal may be binary information, octal information, decimal information, hexadecimal information, etc., and the expression form of the mode selection signal is not particularly limited herein.

Furthermore, in order to determine whether the signal input to the multiplexing pin is a mode selection signal and prevent test mode selection errors, verification can be performed through a clock signal, and the mode selection signal is acquired on the basis of passing the verification; the multiplexing pin may be plural, the mode selection signal may include a clock signal and a mode selection signal, and as shown in fig. 6, the step S24 may include the following steps S241 to S242.

Step S241: a clock signal input via a multiplexing pin is acquired.

In this embodiment, the clock signal may be a pulse signal. For example, the clock signal may be a single pulse or a plurality of consecutive pulses.

Step S242: and if the clock information in the clock signal meets the preset clock condition, acquiring the mode selection signal input through the rest multiplexing pins.

In this embodiment, the preset clock condition may be preset. For example, the preset clock condition may be that the clock signal is two consecutive pulses, three consecutive pulses, etc.

In this embodiment, the remaining multiplexing pin may be a multiplexing pin other than the acquisition clock signal among the plurality of multiplexing pins. It should be noted that the clock signal acquisition and the mode selection signal acquisition may be performed synchronously, and if the clock signal meets a preset clock condition, the signals acquired by the remaining multiplexing pins are used as the mode selection signal.

In this embodiment, through the implementation of the above steps S241 to S242, the clock signal can be verified first, and the mode selection signal can be obtained based on the verification, so as to prevent the test mode selection from being incorrect.

Step S25: a target test pattern corresponding to the pattern selection signal is determined.

In this embodiment, the mapping relationship between the mode selection signal and the test mode may be pre-determined, and after the mode selection signal is obtained, the test mode corresponding to the selection signal in the mode may be obtained, and the test mode may be used as the target test mode.

Further, in order to increase the diversity of mode selection, a plurality of multiplexing pins may be provided in the test unit 102, and the target test mode may be determined based on the high-low level information received by the plurality of multiplexing pins; in the present embodiment, the multiplexing pin is plural, and the mode selection signal includes high-low level information input via the plural multiplexing pins; the step S25 may include: and determining a target test mode according to the preset corresponding relation between the high and low level information and the test mode.

In this embodiment, a mapping relationship between the high and low level information and the test pattern may be preset, so that when the high and low level information is acquired, the test pattern may be determined based on the mapping relationship, and the test pattern may be used as the target test pattern. The number of multiplexing pins may be greater than or equal to 2, and the high-low level information is a level received by the plurality of multiplexing pins.

Specifically, taking the following table (2) as an example, when the high-low level information is obtained as "000", the test pattern "E" is taken as the target test pattern, when the high-low level information is obtained as '001', the test pattern 'F' is taken as the target test pattern, when the high/low level information is "010", the test pattern "G" is set as the target test pattern, when the obtained high-low level information is "011", the test pattern "H" is taken as the target test pattern, when the high-low level information is obtained as "100", the test pattern "I" is taken as the target test pattern, when the high-low level information is obtained as "101", the test pattern "J" is taken as the target test pattern, when the high-low level information is obtained as "110", the test pattern "K" is taken as the target test pattern, when the high/low level information is "111", the test pattern "L" is set as the target test pattern. As can be seen from the example of table (2), each different high-low level information of the plurality of multiplexing pins may represent a corresponding test pattern. By analogy, the number of the multiplexing pins can be two, and at the moment, at most four test modes can exist; the number of multiplexing pins can also be four, and in this case, there can be at most sixteen test modes.

Test mode	Multiplex pin a	Multiplex pin b	Multiplex pin c
				E	0	0	0
F	0	0	1
				G	0	1	0
H	0	1	1
				I	1	0	0
J	1	0	1
				K	1	1	0
L	1	1	1

Watch (2)

It should be noted that, in this embodiment, when there are a plurality of multiplexing pins, a part of the high-low level information may be associated with the test pattern mapping first, and another part of the high-low level information may be associated with the test pattern mapping newly added subsequently, so as to facilitate the later stage of migrating the extended test pattern.

Step S26: the chip 100 is tested in the target test mode.

Further, in order to reduce the number of pins provided in the test unit 102, multiplexing the multiplexed pins may be performed, and the step S26 may include: and configuring the function of the multiplexing pin according to the target test mode, and testing the chip 100 through the configured multiplexing pin.

In this embodiment, after the target test mode is acquired, the function of the multiplexing pin may be switched from acquiring the mode selection signal to acquiring the test information input by the test machine. Therefore, the mode selection signal can be acquired and the test information can be acquired or sent through the multiplexing pins at different times.

In this embodiment, the configuration relationship between the target test pattern and the multiplexing pin may be preset. For example, when the plurality of multiplexing pins include a first multiplexing pin, a second multiplexing pin, and a third multiplexing pin, the first multiplexing pin, the second multiplexing pin, and the third multiplexing pin may be associated with a target test mode, and when the target test mode is obtained, the multiplexing pin associated with the target test mode is enabled to be tested. As shown in the following table (3), when the target test mode is M, the first multiplexing pin may be disabled, the second multiplexing pin may be disabled, the third multiplexing pin may be enabled, when the target test mode is N, the first multiplexing pin may be disabled, the second multiplexing pin may be enabled, the third multiplexing pin may be disabled, when the target test mode is O, the first multiplexing pin may be disabled, the second multiplexing pin may be enabled, the third multiplexing pin may be enabled, when the target test mode is P, the first multiplexing pin may be enabled, the second multiplexing pin may be disabled, the third multiplexing pin may be disabled, when the target test mode is Q, the first multiplexing pin may be enabled, the second multiplexing pin may be disabled, the third multiplexing pin may be enabled, when the target test mode is R, the first multiplexing pin may be enabled, the second multiplexing pin may be enabled, the third multiplexing pin may be disabled, when the target test mode is S, the first multiplexing pin may be enabled, the second multiplexing pin may be enabled, and the third multiplexing pin may be enabled.

Target test mode	First multiplex pin	Second multiplex pin	Third multiplexing pin
				M	×	×	√
N	×	√	×
				O	×	√	√
P	√	×	×
				Q	√	×	√
R	√	√	×
				S	√	√	√

Watch (3)

In this embodiment, through the implementation of the above steps S24 to S26, in order to obtain an expected test result, the test mode of the chip 100 may be divided in advance, a target test mode is obtained from the test mode, the chip 100 is tested based on the target test mode, and meanwhile, in the test process, a multiplexing pin disposed in the test unit 102 may be multiplexed, so that it is not necessary to separately dispose a pin for receiving a mode selection signal and a pin for acquiring test information in the test unit 102, the number of pins disposed in the chip 100 is reduced, the cost for producing the chip 100 is reduced, and meanwhile, the volume of an electronic product is reduced, and the product popularization is facilitated when the electronic product in the market approaches miniaturization.

Further, after the chip 100 completes the test, the read-write permission of the chip 100 may be closed, so that the chip 100 exits the test state; the embodiment of the present application further provides a chip testing method, where the chip testing method is applied to a chip 100, and the chip 100 may include a memory bank 101 and a testing unit 102 electrically connected to each other, as shown in fig. 7, and the chip testing method may include steps S31 to S34. The chip testing method provided in this embodiment may include the same or similar steps as those in the above embodiments, and for the execution of the same or similar steps, reference may be made to the foregoing description, and the description is not repeated.

Step S31: first authentication information is acquired.

Step S32: if the read/write authority of the memory bank 101 is controlled to be in an on state based on the first verification information, a test enable signal is transmitted to the test unit 102 through the memory bank 101.

Step S33: the chip 100 is controlled to enter a test state according to the test enable signal.

Step S34: if the test of the chip 100 is completed, the read/write permission of the memory 101 required by the chip 100 during the test is closed, so that the chip 100 exits the test state.

In this embodiment, the memory bank 101 may be divided into a plurality of areas, where the data stored in each area is different, and the read-write permission of the area related to the read data required in the test process may be closed.

It should be noted that after the read/write permission of the memory bank 101 required by the chip 100 for testing is turned off, the memory bank 101 may send a test disable signal to the test unit 102 to disable the test unit 102 from entering the test state. Specifically, the test prohibition signal may be binary information, octal information, decimal information, hexadecimal information, or the like, and the expression form of the test prohibition signal is not particularly limited herein. For example, if the read/write permission of the memory bank 101 is in an off state, the memory bank 101 may send a low level signal to the test unit 102, and the low level signal may be regarded as a test prohibition signal.

Further, in order to prevent the memory bank 101 from being closed by mistake, second preset authentication information may be set in the memory bank 101, and the acquired second authentication information may be matched with the second preset authentication information, as shown in fig. 8, where the step S34 may include the following steps S341 to S343.

Step S341: and acquiring second verification information, wherein the second verification information is used for closing the read-write permission of the memory 101 required by the chip 100 during testing.

In this embodiment, the second verification information may include information for turning off the read/write authority of the memory bank 101 required when the test is performed. For example, the second verification information may be information for verifying whether to close the read/write authority of all data stored in the memory bank 101, and may also be information for verifying whether to close the read/write authority of a secure area in the memory bank 101. In addition, the second verification information may be binary information, octal information, decimal information, hexadecimal information, etc., and the expression form of the second verification information is not particularly limited herein.

In some examples, the second authentication information may be obtained from a device other than the chip 100. For example, after the chip 100 completes the test, the test machine may send second verification information to the memory bank 101 to close the read/write permission of the memory bank 101 required for the test. When the second authentication information is authenticated to pass, the read-write permission of all data stored in the memory bank 101 may be closed, or the read-write permission of the secure area in the memory bank 101 may be closed.

Step S342: and matching the second verification information with second preset verification information.

In this embodiment, the second preset verification information may include information for verifying whether the second verification information conforms to the permission to close reading and writing. The second preset authentication information may be binary information, octal information, decimal information, hexadecimal information, etc., and should have the same expression form as the second authentication information.

In this embodiment, the matching form between the second verification information and the second preset verification information is not particularly limited. For example, the second verification information may be compared with second preset verification information, if the second verification information is the same as the second preset verification information, it is determined that the second verification information is successfully matched with the second preset verification information, and if the second verification information is different from the second preset verification information, it is determined that the second verification information is unsuccessfully matched with the second preset verification information; and performing and gate operation on the second verification information and second preset verification information, if the result of the and gate operation is "1", determining that the second verification information and the second preset verification information are successfully matched, and if the result of the and gate operation is "0", determining that the second verification information and the second preset verification information are unsuccessfully matched.

In this embodiment, the second preset authentication information may be stored in the memory bank 101 in advance. The second preset authentication information may be stored in a secure area of the memory bank 101, or may be stored in a portion of the memory bank 101 outside the secure area, where the storage location of the second preset authentication information is not particularly limited.

Step S343: if the second verification information is successfully matched with the second preset verification information, the read-write permission of the memory 101 required by the chip 100 during testing is closed, so that the chip 100 exits the testing state.

In this embodiment, if the second verification information is successfully matched with the second preset verification information, the read/write permission of the memory bank 101 required by the chip 100 during the test may be closed. For example, the read/write permission of all data in the storage 101 may be closed, or the read/write permission of a secure area in the storage 101 may be closed, which may be specifically set based on an actual scene.

In some examples, the storage body 101 may be set to multiple areas, each area stores corresponding second preset verification information, and if the second verification information is successfully matched with the second preset verification information stored in a certain area, the read-write permission of the area corresponding to the second preset verification information in the storage body 101 may be closed.

In this embodiment, through the implementation of the above steps S341 to S343, second preset verification information may be set in the storage body 101, the obtained second verification information may be matched with the second preset verification information, and the read-write permission is closed based on the matching result, so that the read-write permission of the storage body 101 is effectively prevented from being closed by mistake.

Further, in order to enable the chip 100 to enter the test state again after the test is completed, the control bit in the memory bank 101 for sending the test enable signal to the test unit 102 may be blown to ensure that the test unit 102 cannot receive the test enable signal any more, the chip testing method provided in this embodiment may further include: control bits in memory bank 101 used to send a test enable signal to test unit 102 are blown to disable chip 100 from entering a test state.

In the present embodiment, the control bit for sending the test enable signal to the test unit 102 may be disposed in a safe region in the memory bank 101, or may be disposed in a region outside the safe region in the memory bank 101, and the position of the control bit is not particularly limited herein. It should be noted that when the control bit is blown, the control bit cannot send the test enable signal, and the test unit 102 cannot enter the test state again.

In this embodiment, through the implementation of the above steps S31 to S34, after the chip 100 is tested, the read/write permission of the memory 101 required for the test is closed, and the control bit for sending the test enable signal to the test unit 102 is blown, so that the chip 100 cannot enter the test state again, thereby preventing an illegal intrusion into the test state and obtaining the private data in the memory 101, and improving the data security of the chip 100.

Referring to fig. 9, a block diagram of a chip testing apparatus provided in an embodiment of the present application is shown, where the chip testing apparatus may be applied to a chip 100, the chip 100 includes a memory bank 101 and a testing unit 102 electrically connected to each other, and the chip testing apparatus includes a first verification information obtaining module 41, a test enabling signal sending module 42, and a testing module 43. The first verification information obtaining module 41 is configured to obtain first verification information. The test enable signal sending module 42 is configured to send a test enable signal to the test unit 102 through the memory bank 101 if the read/write permission of the memory bank 101 is controlled to be in an on state based on the first verification information. The test module 43 is used for controlling the chip 100 to enter a test state according to the test enable signal.

Further, as an implementation manner of this embodiment, the test enable signal sending module 42 may include a matching unit and a read-write permission opening unit. The matching unit is used for matching the first verification information with first preset verification information. The read-write permission opening unit is configured to open the read-write permission of the storage 101 if the first verification information is successfully matched with the first preset verification information.

Further, as an implementation manner of the present embodiment, the test module 43 may include a first mode selection signal acquisition unit, a target test mode determination unit, and a test unit 102. The first mode selection signal acquisition unit is used for acquiring a mode selection signal from a test enable signal. The target test mode determining unit is used for determining a target test mode according to the corresponding relation between the mode selection signal and the test mode. The test unit 102 is used for testing the chip 100 according to the target test pattern.

Further, as an implementation manner of this embodiment, the chip 100 may further include at least one multiplexing pin disposed on the test unit 102; the chip testing device provided by the embodiment may further include a mode selection signal obtaining module, a target test mode determining module, and a target testing module. The mode selection signal acquisition module is used for acquiring a mode selection signal input through a multiplexing pin. The target test mode determination module is used for determining a target test mode corresponding to the mode selection signal. The target test module is used for testing the chip 100 according to the target test mode.

Further, as an implementation manner of the embodiment, the target test module may include a multiplexing pin test unit. The multiplexing pin test unit is configured to configure a function of the multiplexing pin according to the target test mode, and test the chip 100 through the configured multiplexing pin.

Further, as an implementation manner of the present embodiment, the multiplexing pin is plural, and the mode selection signal includes high-low level information input via the plural multiplexing pins; the target test pattern may include a high-low level determination unit. The high-low level determining unit is used for determining a target test mode according to a preset corresponding relation between the high-low level information and the test mode.

Further, as an implementation manner of this embodiment, the number of multiplexing pins is multiple, and the mode selection signal includes a clock obtaining signal and a mode selection signal; the mode selection signal acquisition module may include a clock signal acquisition unit and a second mode selection signal acquisition unit. The clock signal acquisition unit is used for acquiring a clock signal input through a multiplexing pin. The second mode selection signal acquisition unit is used for acquiring the mode selection signal input by the rest multiplexing pins if the clock information in the clock signal meets the preset clock condition.

Further, as an implementation manner of this embodiment, the chip testing apparatus provided in this embodiment may further include a test state exit module. The test state exit module is configured to close the read-write permission of the memory 101 required by the chip 100 during the test if the test of the chip 100 is completed, so that the chip 100 exits the test state.

Further, as an implementation manner of this embodiment, the test state exit module may include a second verification information obtaining unit, a preset information matching unit, and a test state exit unit. The second verification information obtaining unit is configured to obtain second verification information, where the second verification information is used to close the read-write permission of the memory 101 required by the chip 100 during testing. The preset information matching unit is used for matching the second verification information with second preset verification information. The test state exit unit is configured to close the read-write permission of the memory 101 required when the chip 100 performs the test if the second verification information is successfully matched with the second preset verification information, so that the chip 100 exits the test state.

Further, as an implementation manner of this embodiment, the chip testing apparatus provided in this embodiment may further include a test status prohibition module. The test state disabling module is configured to blow a control bit in the memory bank 101 for sending a test enable signal to the test unit 102, so as to disable the chip 100 from entering the test state.

It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of each module in the above-described apparatus may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, the coupling or direct coupling or communication connection between the modules shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or modules may be in an electrical, mechanical or other form.

In addition, functional modules in the embodiments of the present application may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.

Referring to fig. 10, a chip 100 provided in an embodiment of the present application is shown, where the chip 100 includes a memory bank 101 and a test unit 102 electrically connected to each other, and the chip 100 may further include one or more processors; one or more programs, wherein the one or more programs are stored in the memory bank 101 and configured to be executed by the one or more processors, the one or more programs configured to perform the chip testing method provided by the above-described embodiments. The chip 100 may include a processor 810, a communication module 820, a memory 830, and a bus. The processor 810, the communication module 820, the memory 830, the battery 10 and the temperature control device 20 are connected to each other through a bus and perform communication with each other. The bus may be an ISA bus, PCI bus, EISA bus, CAN bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. Wherein:

and a memory 830 for storing programs. In particular, the memory 830 may be used to store software programs as well as various data. The memory 830 may mainly include a program storage area and a data storage area, wherein the program storage area may store an application program required to operate at least one function and may include program codes including computer operating instructions. In addition to storing programs, the memory 830 may temporarily store messages or the like that the communication module 820 needs to send. The memory 830 may include a high-speed RAM memory, and may further include a non-volatile memory (non-volatile memory), such as at least one Solid State Disk (SSD).

The processor 810 is configured to execute programs stored in the memory 830. The program is executed by a processor to implement the steps of the chip testing method of the above embodiments.

The embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements each process of the above chip testing method embodiment, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here. The computer-readable storage medium includes, for example, a Read-Only Memory (ROM), a Random Access Memory (RAM), an SSD, a charged Erasable Programmable Read-Only Memory (EEPROM), or a Flash Memory (Flash).

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, SSD, Flash), and includes several instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the methods of the embodiments of the present application.

While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A chip testing method is applied to a chip, the chip comprises a memory bank and a testing unit which are electrically connected with each other, and the chip testing method comprises the following steps:

acquiring first verification information;

if the read-write authority of the memory bank is controlled to be in an open state based on the first verification information, a test enabling signal is sent to the test unit through the memory bank; and

and controlling the chip to enter a test state according to the test enabling signal.

2. The chip testing method according to claim 1, wherein the controlling the read-write permission of the memory bank to be in an open state based on the first verification information comprises:

matching the first verification information with first preset verification information;

and if the first verification information is successfully matched with the first preset verification information, starting the read-write permission of the memory bank.

3. The chip testing method according to claim 1, wherein the controlling the chip to enter the testing state according to the test enable signal comprises:

acquiring a mode selection signal from the test enable signal;

determining a target test mode according to the corresponding relation between the mode selection signal and the test mode;

and testing the chip according to the target test mode.

4. The chip testing method according to claim 1, wherein the chip further comprises at least one multiplexing pin disposed in the testing unit; the chip testing method further comprises the following steps:

acquiring a mode selection signal input via the multiplexing pin;

determining a target test pattern corresponding to the pattern selection signal;

and testing the chip according to the target test mode.

5. The chip testing method according to claim 4, wherein the testing the chip according to the target test mode comprises:

and configuring the function of the multiplexing pin according to the target test mode, and testing the chip through the configured multiplexing pin.

6. The chip testing method according to claim 4, wherein the multiplexing pin is plural, and the mode selection signal includes high-low level information input via the plural multiplexing pins; the determining a target test pattern corresponding to the mode selection signal includes:

and determining the target test mode according to the preset corresponding relation between the high and low level information and the test mode.

7. The chip testing method according to claim 4, wherein the multiplexing pin is plural, and the mode selection signal includes a clock signal and a mode selection signal; the acquiring the mode selection signal input via the multiplexing pin comprises:

acquiring a clock signal input through the multiplexing pin;

and if the clock information in the clock signal meets a preset clock condition, acquiring a mode selection signal input through the residual multiplexing pin.

8. The chip testing method according to any one of claims 1 to 7, further comprising:

and if the test of the chip is finished, closing the read-write permission of the memory body required by the chip during the test so as to enable the chip to exit the test state.

9. The chip testing method according to claim 8, wherein the closing of the read-write permission of the memory bank required for the chip to perform the test so that the chip exits the test state comprises:

acquiring second verification information, wherein the second verification information is used for closing the read-write permission of a memory bank required by the chip during testing;

matching the second verification information with the second preset verification information;

if the second verification information is successfully matched with the second preset verification information, closing the read-write permission of the memory bank required by the chip during testing so as to enable the chip to exit the testing state.

10. The chip testing method according to claim 8, further comprising:

and fusing a control bit in the memory bank for sending a test enabling signal to the test unit so as to prohibit the chip from entering a test state.

11. A chip testing device, characterized in that, be applied to the chip, the chip includes memory bank and the test element of mutual electric connection, chip testing device includes:

the first verification information acquisition module is used for acquiring first verification information;

the test enabling signal sending module is used for sending a test enabling signal to the test unit through the memory bank if the read-write permission of the memory bank is controlled to be in an open state based on the first verification information;

and the test module is used for controlling the chip to enter a test state according to the test enabling signal.

12. A chip comprising a memory bank and a test unit electrically connected to each other, the chip further comprising:

one or more processors;

one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the chip testing method of any of claims 1 to 10.

13. A computer-readable storage medium, in which a program code is stored, the program code being called by a processor to execute the chip testing method according to any one of claims 1 to 10.