CN116453581B - Memory chip testing method and device, electronic equipment and readable storage medium - Google Patents
Memory chip testing method and device, electronic equipment and readable storage medium Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The embodiment of the invention provides a memory chip testing method, a memory chip testing device, electronic equipment and a computer readable storage medium. The method comprises the following steps: acquiring a test instruction of a memory chip; decoding the memory chip test instruction to obtain memory chip test information; inputting a test signal into a first test input pin of a memory chip to be tested according to the test information of the memory chip; reading a feedback signal from a first test output pin of a memory chip to be tested; under the condition that the feedback signal does not meet the preset chip working parameter threshold value, stopping testing processing of the memory chip to be tested, and marking the corresponding memory chip to be tested as a defective product; the chip working parameter threshold represents the minimum parameter threshold requirement which is needed to be reached when the memory chip realizes any function. According to the scheme provided by the embodiment of the invention, the testing efficiency of the memory chip can be improved, and the memory chip which is unqualified in testing can be rapidly removed.
Description
Technical Field
The present invention relates to the field of chip testing technologies, and in particular, to a method and apparatus for testing a memory chip, an electronic device, and a computer readable storage medium.
Background
Along with the continuous increase of the demand of electronic products, the storage chips applied to the electronic products also show an exponential increase; the method comprises the steps that a storage chip is required to be subjected to test processing of multiple functional parameters before being used, a test result related to the corresponding storage chip is finally obtained, and finally the test result is analyzed and processed to determine whether the storage chip is qualified or not; however, the testing process of the memory chip is relatively complicated, and the memory chip which is unqualified in test cannot be removed rapidly, so that the workload of testing the memory chip is increased.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art.
Therefore, the invention provides a memory chip testing method which can accelerate the testing efficiency of the memory chip and rapidly reject the memory chip which is unqualified in testing.
The invention also provides a device applying the memory chip testing method.
The invention also provides electronic equipment applying the memory chip testing method.
The invention also provides a computer readable storage medium applying the storage chip testing method.
According to an embodiment of the first aspect of the present invention, a method for testing a memory chip includes:
acquiring a test instruction of a memory chip;
decoding the memory chip test instruction to obtain memory chip test information;
inputting a test signal into a first test input pin of a memory chip to be tested according to the memory chip test information;
reading a feedback signal from a first test output pin of the memory chip to be tested;
stopping test processing on the memory chip to be tested under the condition that the feedback signal does not meet a preset chip working parameter threshold value, and marking the corresponding memory chip to be tested as a defective product;
the chip working parameter threshold represents the minimum parameter threshold requirement which is needed to be reached when the memory chip realizes any function.
According to some embodiments of the invention, before the acquiring the memory chip test instruction, the method further includes:
acquiring verification information;
and controlling the read-write permission of the memory chip to be tested to be in an open state according to the verification information.
According to some embodiments of the invention, the inputting the test signal at the first test input pin of the memory chip to be tested according to the memory chip test information includes:
analyzing and processing the memory chip test information to obtain chip test item information, wherein the chip test item information comprises test port information and test level information;
determining the first test input pin of the memory chip to be tested according to the test port information;
and inputting the test signal to the first test input pin according to the test level information.
According to some embodiments of the invention, the reading the feedback signal from the first test output pin of the memory chip to be tested includes:
determining the first test output pin according to the test port information;
reading feedback level information from the first test output pin of the memory chip to be tested in response to the test signal;
the feedback level information is determined as the feedback signal.
According to some embodiments of the invention, in a case where the feedback signal does not meet a preset chip operating parameter threshold, stopping the test process for the memory chip to be tested includes:
converting the feedback signal to obtain a detection feedback parameter;
comparing the detection feedback parameter with the chip working parameter threshold;
and stopping testing the memory chip to be tested when the detection feedback parameter is not in the range of the chip working parameter threshold.
According to some embodiments of the present invention, the controlling the read-write permission of the memory chip to be tested according to the verification information in an on state includes:
analyzing the verification information to obtain test opening trigger information;
and opening the read-write permission of the memory chip to be tested according to the test opening triggering information.
According to some embodiments of the invention, after the controlling the read-write permission of the memory chip to be tested according to the verification information is in an on state, the method further includes:
transmitting a test enabling signal to the memory chip to be tested;
and controlling the memory chip to be tested to enter a test state based on the test enabling signal.
According to an embodiment of the second aspect of the present invention, a memory chip testing apparatus includes:
the first processing module is used for acquiring a memory chip test instruction;
the second processing module is used for decoding the memory chip test instruction to obtain memory chip test information;
the third processing module is used for inputting a test signal into a first test input pin of the memory chip to be tested according to the memory chip test information;
the fourth processing module is used for reading a feedback signal from a first test output pin of the memory chip to be tested;
the fifth processing module is used for stopping the test processing of the memory chip to be tested and marking the corresponding memory chip to be tested as a defective product under the condition that the feedback signal does not meet the preset chip working parameter threshold;
the chip working parameter threshold represents the minimum parameter threshold requirement which is needed to be reached when the memory chip realizes any function.
An electronic device according to an embodiment of a third aspect of the present invention includes: a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the memory chip test method as described above when executing the computer program.
A computer-readable storage medium according to an embodiment of the fourth aspect of the present invention stores computer-executable instructions that, when executed by a control processor, implement the memory chip testing method as described above.
The memory chip testing method provided by the embodiment of the invention has at least the following beneficial effects: in the process of detecting the memory chip, firstly acquiring a memory chip test instruction, and then decoding the memory chip test instruction to obtain memory chip test information; then, inputting a test signal into a first test input pin of the memory chip to be tested according to the test information of the memory chip; reading a feedback signal from a first test output pin of a memory chip to be tested; under the condition that the feedback signal does not meet the preset chip working parameter threshold value, stopping testing processing of the memory chip to be tested, and marking the corresponding memory chip to be tested as defective products; the chip working parameter threshold represents the minimum parameter threshold requirement which is needed to be reached when the memory chip realizes any function. Through the technical scheme, the test processing is stopped immediately under the condition that a certain function of the memory chip is found to be unqualified in the test process, so that the test time of the memory chip can be well saved, the test efficiency of the memory chip is improved, and the unqualified memory chip is removed.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain, without limitation, the disclosed embodiments.
FIG. 1 is a flow chart of a method for testing a memory chip according to an embodiment of the present invention;
FIG. 2 is a flowchart of a method for testing a memory chip according to another embodiment of the present invention;
FIG. 3 is a flowchart showing an input test signal of a memory chip test method according to an embodiment of the present invention;
FIG. 4 is a flowchart showing a read feedback signal of a memory chip test method according to an embodiment of the present invention;
FIG. 5 is a flowchart showing a method for testing a memory chip according to an embodiment of the present invention, wherein the method includes stopping testing a memory chip to be tested;
FIG. 6 is a flowchart of a method for testing a memory chip according to an embodiment of the present invention, wherein the method controls the read/write permission of the memory chip to be in an on state;
FIG. 7 is a flowchart of a method for testing a memory chip according to another embodiment of the present invention;
FIG. 8 is a schematic diagram of a memory chip testing apparatus according to an embodiment of the present invention;
fig. 9 is a schematic diagram of the configuration of an electronic device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In the description of the present invention, a number means one or more, a number means two or more, and greater than, less than, exceeding, etc. are understood to not include the present number, and above, below, within, etc. are understood to include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present invention can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical scheme.
The invention provides a memory chip testing method, a memory chip testing device, electronic equipment and a computer readable storage medium, wherein the method comprises the following steps: in the process of detecting the memory chip, firstly acquiring a memory chip test instruction, and then decoding the memory chip test instruction to obtain memory chip test information; then, inputting a test signal into a first test input pin of the memory chip to be tested according to the test information of the memory chip; reading a feedback signal from a first test output pin of a memory chip to be tested; under the condition that the feedback signal does not meet the preset chip working parameter threshold value, stopping testing processing of the memory chip to be tested, and marking the corresponding memory chip to be tested as defective products; the chip working parameter threshold represents the minimum parameter threshold requirement which is needed to be reached when the memory chip realizes any function. Through the technical scheme, the test processing is stopped immediately under the condition that a certain function of the memory chip is found to be unqualified in the test process, so that the test time of the memory chip can be well saved, the test efficiency of the memory chip is improved, and the unqualified memory chip is removed.
Embodiments of the present invention will be further described below with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a flowchart of a method for testing a memory chip according to an embodiment of the invention. The method includes, but is not limited to, step S100, step S200, step S300, step S400, and step S500:
step S100, obtaining a memory chip test instruction;
step S200, decoding the memory chip test instruction to obtain memory chip test information;
step S300, inputting a test signal into a first test input pin of a memory chip to be tested according to the test information of the memory chip;
step S400, reading a feedback signal from a first test output pin of a memory chip to be tested;
and S500, stopping the test processing of the memory chip to be tested and marking the corresponding memory chip to be tested as a defective product under the condition that the feedback signal does not meet the preset chip working parameter threshold.
In the process of detecting the memory chip, firstly, a memory chip test instruction is obtained, and then the memory chip test instruction is decoded to obtain memory chip test information; then, inputting a test signal into a first test input pin of the memory chip to be tested according to the test information of the memory chip; reading a feedback signal from a first test output pin of a memory chip to be tested; under the condition that the feedback signal does not meet the preset chip working parameter threshold value, stopping testing processing of the memory chip to be tested, and marking the corresponding memory chip to be tested as defective products; the chip working parameter threshold represents the minimum parameter threshold requirement which is needed to be reached when the memory chip realizes any function. Through the technical scheme, the test processing is stopped immediately under the condition that a certain function of the memory chip is found to be unqualified in the test process, so that the test time of the memory chip can be well saved, the test efficiency of the memory chip is improved, and the unqualified memory chip is removed.
Notably, the chip operating parameter threshold characterizes the minimum parameter threshold requirement that the memory chip needs to achieve any function. Namely, the parameter requirements which need to be met when the memory chip completes a certain function; the operation frequency of the memory chip is tested, and when the basic read-write requirements are required to be met, the operation frequency of the memory chip is required to be at least 1600MHz, and the operation frequency of the memory chip obtained through testing is only 1200MHz, so that the test processing of the memory chip is stopped, the memory chip is marked as defective products, the test efficiency of the memory chip is improved well, and the memory chip which does not meet the working requirements is removed rapidly.
It can be understood that the test instruction of the memory chip can be issued to the memory chip through the upper computer; then decoding the memory chip test instruction issued by the upper computer to obtain corresponding memory chip test information; the memory chip test information includes test item information for performing a functional test on the memory chip.
It should be noted that, after the memory chip which does not meet the test requirement is marked as a defective product, the defective product is also recovered for subsequent operation.
In addition, in an embodiment, as shown in fig. 2, step S110 and step S120 may be included, but are not limited to, before step S100 is performed.
Step S110, acquiring verification information;
step S120, controlling the read-write authority of the memory chip to be tested to be in an open state according to the verification information.
It should be noted that, before the memory chip test instruction is obtained, the memory chip may also obtain verification information, and then control the read-write authority of the memory chip to be tested to be in an on state according to the verification information, so as to prepare for subsequent memory chip test.
In addition, in an embodiment, as shown in fig. 3, the step S300 may include, but is not limited to, step S310, step S320, and step S330.
Step S310, analyzing and processing the stored chip test information to obtain chip test item information, wherein the chip test item information comprises test port information and test level information;
step S320, determining a first test input pin of the memory chip to be tested according to the test port information;
step S330, a test signal is input to the first test input pin according to the test level information.
In the process of testing the memory chip, firstly, analyzing and processing the test information of the memory chip to obtain chip test item information, wherein the chip test item information comprises test port information and test level information; determining a first test input pin of the memory chip to be tested according to the test port information; and then, inputting a test signal to the first test input pin according to the test level information.
It can be appreciated that the corresponding first test input pin is determined according to the test port information; and determining a test signal input to the first test input pin according to the test level information so as to realize test processing on a certain function of the memory chip.
In addition, in an embodiment, as shown in fig. 4, the step S400 may include, but is not limited to, step S410, step S420, and step S430.
Step S410, determining a first test output pin according to the test port information;
step S420, responding to the test signal, reading feedback level information from a first test output pin of the memory chip to be tested;
in step S430, the feedback level information is determined as a feedback signal.
In the process of testing the memory chip, the first test output pin is determined according to the test port information; then, responding to the test signal, and reading feedback level information from a first test output pin of the memory chip to be tested; and finally, determining the feedback level information as a feedback signal. And the test result of the memory chip can be obtained by analyzing and processing the feedback level information. The memory chip may read feedback level information from a first test output pin of the memory chip to be tested in response to the test signal.
In addition, in an embodiment, as shown in fig. 5, the step S500 may include, but is not limited to, step S510, step S520, and step S530.
Step S510, converting the feedback signal to obtain a detection feedback parameter;
step S520, comparing the detection feedback parameter with a chip working parameter threshold;
and step S530, stopping the test processing of the memory chip to be tested when the detection feedback parameter is not in the range of the chip working parameter threshold.
In the process of testing the memory chip, the feedback signal is converted to obtain the detection feedback parameter; then comparing the detection feedback parameter with a chip working parameter threshold value; when the detection feedback parameter is not in the interval range of the chip working parameter threshold, the test processing of the memory chip to be tested is stopped, so that the test efficiency of the memory chip can be improved, and the memory chips which do not meet the working requirement can be rapidly removed in the process of testing the memory chips in the same batch.
It will be appreciated that the conversion of the feedback signal may convert the feedback signal into a digital form of the parameter to facilitate comparison of the sensed feedback parameter with the chip operating parameter threshold. In the interval range that the detection feedback parameter is not located in the chip working parameter threshold, the fact that the storage chip cannot complete a certain chip function and cannot normally operate is indicated, and therefore the storage chip which does not meet the requirements is marked as a defective product.
In addition, in an embodiment, as shown in fig. 6, the step S120 may include, but is not limited to, step S121 and step S122.
Step S121, analyzing and processing the verification information to obtain test opening trigger information;
step S122, the read-write permission of the memory chip to be tested is started according to the test start trigger information.
It should be noted that, before testing the memory chip, the verification information may be analyzed to obtain the test start trigger information; and then, opening the read-write permission of the memory chip to be tested according to the test opening trigger information, and preparing for the subsequent test of the memory chip.
In addition, in an embodiment, as shown in fig. 7, after the step S120 is performed, the method may further include, but is not limited to, step S130 and step S140.
Step S130, sending a test enabling signal to the memory chip to be tested;
step S140, controlling the memory chip to be tested to enter the test state based on the test enable signal.
It should be noted that, after the read-write port of the memory chip is in an open state, a test enabling signal may also be sent to the memory chip to be tested; the memory chip to be tested is then brought into a test state based on the test enable signal, ready for subsequent memory chip testing.
In some embodiments of the present invention, as shown in fig. 8, an embodiment of the present invention further provides a memory chip testing apparatus 10, the apparatus comprising:
a first processing module 100, configured to obtain a memory chip test instruction;
the second processing module 200 is configured to decode the memory chip test instruction to obtain memory chip test information;
the third processing module 300 is configured to input a test signal at a first test input pin of the memory chip to be tested according to the memory chip test information;
a fourth processing module 400, configured to read a feedback signal from a first test output pin of the memory chip to be tested;
the fifth processing module 500 is configured to stop the testing process for the memory chip to be tested and mark the corresponding memory chip to be tested as a defective product if the feedback signal does not meet the preset chip working parameter threshold;
the chip working parameter threshold represents the minimum parameter threshold requirement which is needed to be reached when the memory chip realizes any function.
The specific implementation of the memory chip testing device 10 is substantially the same as the specific embodiment of the above-mentioned memory chip testing method, and will not be described herein.
In some embodiments of the present invention, as shown in fig. 9, an embodiment of the present invention further provides an electronic device 700, including: the memory 720, the processor 710, and the computer program stored on the memory 720 and executable on the processor 710, the processor 710 implements the memory chip testing method in the above-described embodiments when executing the computer program, for example, performing the method steps S100 to S500 in fig. 1, the method steps S110 to S120 in fig. 2, the method steps S310 to S330 in fig. 3, the method steps S410 to S430 in fig. 4, the method steps S510 to S530 in fig. 5, the method steps S121 to S122 in fig. 6, and the method steps S130 to S140 in fig. 7 described above.
In some embodiments of the present invention, an embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions that are executed by a processor or controller, for example, by one of the processors in the above-described device embodiments, which may cause the processor to perform the memory chip testing method in the above-described embodiment, for example, performing the method steps S100 to S500 in fig. 1, the method steps S110 to S120 in fig. 2, the method steps S310 to S330 in fig. 3, the method steps S410 to S430 in fig. 4, the method steps S510 to S530 in fig. 5, the method steps S121 to S122 in fig. 6, and the method steps S130 to S140 in fig. 7 described above.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
While the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the above embodiment, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the present invention, and these equivalent modifications and substitutions are intended to be included in the scope of the present invention as defined in the appended claims.
Claims (8)
1. A memory chip testing method, comprising:
acquiring a test instruction of a memory chip;
decoding the memory chip test instruction to obtain memory chip test information;
inputting a test signal into a first test input pin of a memory chip to be tested according to the memory chip test information;
reading a feedback signal from a first test output pin of the memory chip to be tested;
stopping test processing on the memory chip to be tested under the condition that the feedback signal does not meet a preset chip working parameter threshold value, and marking the corresponding memory chip to be tested as a defective product;
the chip working parameter threshold represents the minimum parameter threshold requirement which is required to be reached when the memory chip realizes any function;
the step of inputting a test signal into a first test input pin of the memory chip to be tested according to the memory chip test information comprises the following steps:
analyzing and processing the memory chip test information to obtain chip test item information, wherein the chip test item information comprises test port information and test level information;
determining the first test input pin of the memory chip to be tested according to the test port information;
inputting the test signal to the first test input pin according to the test level information;
the reading the feedback signal from the first test output pin of the memory chip to be tested includes:
determining the first test output pin according to the test port information;
reading feedback level information from the first test output pin of the memory chip to be tested in response to the test signal;
the feedback level information is determined as the feedback signal.
2. The memory chip testing method of claim 1, wherein prior to the retrieving the memory chip test instruction, the method further comprises:
acquiring verification information;
and controlling the read-write permission of the memory chip to be tested to be in an open state according to the verification information.
3. The method for testing a memory chip according to claim 1, wherein stopping the test process for the memory chip to be tested if the feedback signal does not satisfy a preset chip operation parameter threshold value, comprises:
converting the feedback signal to obtain a detection feedback parameter;
comparing the detection feedback parameter with the chip working parameter threshold;
and stopping testing the memory chip to be tested when the detection feedback parameter is not in the range of the chip working parameter threshold.
4. The method for testing a memory chip according to claim 2, wherein controlling the read-write permission of the memory chip to be tested to be in an on state according to the verification information comprises:
analyzing the verification information to obtain test opening trigger information;
and opening the read-write permission of the memory chip to be tested according to the test opening triggering information.
5. The method for testing a memory chip according to claim 2, wherein after the controlling the read-write permission of the memory chip to be tested according to the verification information is in an on state, the method further comprises:
transmitting a test enabling signal to the memory chip to be tested;
and controlling the memory chip to be tested to enter a test state based on the test enabling signal.
6. A memory chip testing apparatus, comprising:
the first processing module is used for acquiring a memory chip test instruction;
the second processing module is used for decoding the memory chip test instruction to obtain memory chip test information;
the third processing module is used for inputting a test signal into a first test input pin of the memory chip to be tested according to the memory chip test information;
the fourth processing module is used for reading a feedback signal from a first test output pin of the memory chip to be tested;
the fifth processing module is used for stopping the test processing of the memory chip to be tested and marking the corresponding memory chip to be tested as a defective product under the condition that the feedback signal does not meet the preset chip working parameter threshold;
the chip working parameter threshold represents the minimum parameter threshold requirement which is required to be reached when the memory chip realizes any function;
the step of inputting a test signal into a first test input pin of the memory chip to be tested according to the memory chip test information comprises the following steps:
analyzing and processing the memory chip test information to obtain chip test item information, wherein the chip test item information comprises test port information and test level information;
determining the first test input pin of the memory chip to be tested according to the test port information;
inputting the test signal to the first test input pin according to the test level information;
the reading the feedback signal from the first test output pin of the memory chip to be tested includes:
determining the first test output pin according to the test port information;
reading feedback level information from the first test output pin of the memory chip to be tested in response to the test signal;
the feedback level information is determined as the feedback signal.
7. An electronic device, comprising:
memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the memory chip testing method according to any one of claims 1 to 5 when the computer program is executed.
8. A computer readable storage medium storing computer executable instructions which when executed by a control processor implement the memory chip testing method of any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310460347.3A CN116453581B (en) | 2023-04-23 | 2023-04-23 | Memory chip testing method and device, electronic equipment and readable storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310460347.3A CN116453581B (en) | 2023-04-23 | 2023-04-23 | Memory chip testing method and device, electronic equipment and readable storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116453581A CN116453581A (en) | 2023-07-18 |
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