CN113641524B - Reset method, device and equipment for single board starting overtime and readable storage medium - Google Patents
Reset method, device and equipment for single board starting overtime and readable storage medium Download PDFInfo
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- 238000004891 communication Methods 0.000 description 11
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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Abstract
The invention provides a reset method, a reset device, reset equipment and a readable storage medium for starting overtime of a single board, wherein the method comprises the following steps: acquiring a time threshold and first input information, wherein the first input information comprises confirmation information that a single board is powered on and started, and the first input information is used for triggering a programmable logic device on the single board to detect a hard disk action signal of a hard disk on the single board; analyzing whether the programmable logic device detects the hard disk action signal within the time threshold to obtain an analysis result, wherein the analysis result is used for triggering a resetting device to reset a processor in the single board. The invention monitors the SATA_ACT signal state of the hard disk of the single board by adding the programmable logic device, thereby solving the problem that the single board is dead during starting and can not be reset automatically.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method, an apparatus, a device, and a readable storage medium for resetting a single board startup timeout.
Background
In existing communication devices, particularly reset systems for single board communication devices, a watchdog chip is typically used to monitor the operational status of the system. When the system is in error, the watchdog chip triggers a reset mechanism to reset the processor of the board card system and restart the whole system so as to achieve the purpose that the system can run again. In the traditional reset method, once the phenomenon of hanging and the like occurs in the starting process of the single board, the watchdog chip still outputs a flag bit signal by the CPLD (programmable logic device) and cannot be switched to the processor, so that the phenomenon that the single board is hung and the single board cannot be reset automatically occurs.
Disclosure of Invention
The present invention aims to provide a reset method, device, equipment and readable storage medium for starting overtime of a single board, so as to improve the above problems.
In order to achieve the above purpose, the embodiment of the present application provides the following technical solutions:
in one aspect, an embodiment of the present application provides a reset method for a board start timeout, where the method includes:
acquiring a time threshold and first input information, wherein the first input information comprises confirmation information that a single board is powered on and started, and the first input information is used for triggering a programmable logic device on the single board to detect a hard disk action signal of a hard disk on the single board;
analyzing whether the programmable logic device detects the hard disk action signal within the time threshold to obtain an analysis result, wherein the analysis result is used for triggering a resetting device to reset a processor in the single board.
Optionally, the analyzing whether the programmable logic device detects the hard disk action signal within the time threshold value to obtain an analysis result, where the analysis result is used to trigger a reset device to perform a reset operation on a processor in the board, includes:
analyzing whether the programmable logic device detects the hard disk action signal within the time threshold, and if the obtained analysis result is that the programmable logic device does not detect the hard disk action signal within the time threshold, triggering the programmable logic device to send a reset command to a watchdog chip, wherein the reset command is used for triggering the watchdog chip to reset a processor in the single board.
Optionally, before the acquiring the time threshold and the first input information, the method further includes:
acquiring second input information, wherein the second input information comprises a time threshold value range input by a user;
and selecting a numerical value as the time threshold value at random in the time threshold value range.
Optionally, the analyzing whether the programmable logic device detects the hard disk action signal within the time threshold value, after obtaining an analysis result, further includes:
analyzing whether the programmable logic device detects the hard disk action signal within the time threshold when the reset device performs the reset operation, and if not, sending a control command, wherein the control command comprises a command for controlling the reset device to perform the reset operation on the processor in the single board.
In a second aspect, an embodiment of the present application provides a reset device for a board start timeout, where the device includes a first obtaining module and a first analyzing module.
The first acquisition module is used for acquiring a time threshold and first input information, wherein the first input information comprises confirmation information that a single board is electrified and started, and the first input information is used for triggering a programmable logic device on the single board to detect a hard disk action signal of a hard disk on the single board;
the first analysis module is configured to analyze whether the programmable logic device detects the hard disk action signal within the time threshold to obtain an analysis result, where the analysis result is used to trigger a reset device to perform a reset operation on a processor in the board.
Optionally, the first analysis module includes:
the analysis unit is used for analyzing whether the programmable logic device detects the hard disk action signal within the time threshold, and if the obtained analysis result is that the programmable logic device does not detect the hard disk action signal within the time threshold, the analysis result is used for triggering the programmable logic device to send a reset command to a watchdog chip, and the reset command is used for triggering the watchdog chip to reset a processor in the single board.
Optionally, the apparatus further includes:
the second acquisition module is used for acquiring second input information, wherein the second input information comprises a time threshold value range input by a user;
and the selecting module is used for arbitrarily selecting a numerical value from the time threshold value range as the time threshold value.
Optionally, the apparatus further includes:
and the second analysis module is used for analyzing whether the programmable logic device detects the hard disk action signal within the time threshold when the reset device performs reset operation, and if not, the second analysis module sends a control command which comprises a command for controlling the reset device to perform reset operation on the processor in the single board.
In a third aspect, an embodiment of the present application provides a reset device for a board start timeout, where the device includes a memory and a processor. The memory is used for storing a computer program; the processor is used for realizing the reset method of the single board starting overtime when executing the computer program.
In a fourth aspect, embodiments of the present application provide a readable storage medium, where a computer program is stored, where the computer program when executed by a processor implements the steps of the above-mentioned reset method for a board start timeout.
The beneficial effects of the invention are as follows:
1. in the traditional reset method, once the phenomenon of hanging and the like occurs in the starting process of the single board, the watchdog chip still outputs a flag bit signal by a CPLD (programmable logic device) and cannot be switched to a processor, so that the phenomenon of hanging and the like of the single board and cannot be reset automatically occurs; the invention realizes the monitoring of the SATA_ACT signal state of the hard disk of the single board by adding the programmable logic device, thereby solving the problem that the single board is dead during the starting process and can not be reset automatically.
2. The invention can enable the user to flexibly set the value of the time threshold according to the self demand.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a reset method of a single board start timeout according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a reset device with a single board start timeout according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a reset device with a single board start timeout according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals or letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
Example 1
As shown in fig. 1, the present embodiment provides a reset method of a board start timeout, which includes step S1 and step S2.
Step S1, acquiring a time threshold and first input information, wherein the first input information comprises confirmation information that a single board is electrified and started, and the first input information is used for triggering a programmable logic device on the single board to detect a hard disk action signal of a hard disk on the single board;
and S2, analyzing whether the programmable logic device detects the hard disk action signal within the time threshold to obtain an analysis result, wherein the analysis result is used for triggering a reset device to reset the processor in the single board.
In this embodiment, when the single board is powered on and started, the programmable logic device (CPLD) automatically starts the monitoring function of the sata_act (hard disk action) signal, that is, monitors the hard disk action signal, and when the hard disk action signal is not monitored within 40s-2min, the programmable logic device automatically sends a reset command to the watchdog chip, and after the watchdog chip receives the reset command, resets the processor in the single board, that is, restarts the processor;
in this embodiment, the hard disk information must be read in the starting process of the single board, when the hard disk information is read, the sata_act (hard disk action) signal will ACT, if no sata_act (hard disk action) signal is monitored to ACT within the starting time specified by the system, it can be seen that the processor is dying in the starting process, the programmable logic device immediately makes a command to the watchdog chip, and resets and restarts the single board;
in the traditional reset method, before the system is completely started, the processor does not enter a normal working state, and the programmable logic device is required to continuously output a marking signal to the watchdog chip, so that the watchdog chip can work normally. When the system is completely started, the flag signal output by the programmable logic device stops transmitting, and the processor transmits the flag signal to the watchdog chip. When the processor is in abnormal states such as hanging death and running flight, the sign signals output by the processor cannot be normally sent out, and then the watchdog chip cannot receive the sign signals, and reset actions are carried out on the processor, and the processor is restarted. However, in the reset method, the flag signal output by the processor is too dependent, once the processor is suspended before being completely started, the flag signal of the watchdog reset chip cannot be output by the processor, and the programmable logic device can always output the flag signal, so that once the single board communication system is in a suspended state, the single board can be restarted only by manually resetting the single board or performing power-off restarting work, and the processing mechanism has a great leak to the single board system; in the embodiment, the programmable logic device is added to monitor the state of the SATA_ACT (hard disk action) signal of the hard disk of the single board, so that the problem that the single board is dead during starting and cannot be reset automatically is solved.
In a specific embodiment of the disclosure, the step S2 may further include a step S21.
Step S21, analyzing whether the programmable logic device detects the hard disk action signal within the time threshold, and if the obtained analysis result is that the programmable logic device does not detect the hard disk action signal within the time threshold, triggering the programmable logic device to send a reset command to a watchdog chip, wherein the reset command is used for triggering the watchdog chip to reset a processor in the single board.
In a specific embodiment of the disclosure, before the step S1, step S11 and step S12 may further be included.
Step S11, obtaining second input information, wherein the second input information comprises a time threshold value range input by a user;
step S12, arbitrarily selecting a numerical value from the time threshold value range as the time threshold value.
In the embodiment, the time threshold value range input by the user can be 40s-2min, and the time threshold value range is acquired by adopting a user input mode, so that the user can flexibly set the time threshold value range according to the self requirement; in another embodiment, the time threshold of the user input may also be obtained directly.
In a specific embodiment of the disclosure, the method may further include step S3.
And S3, analyzing whether the programmable logic device detects the hard disk action signal within the time threshold when the reset device performs reset operation, and if not, sending a control command, wherein the control command comprises a command for controlling the reset device to perform reset operation on a processor in the single board.
In this embodiment, when the reset restart is performed by the watchdog chip, if the hard disk action signal is still not detected within the time threshold during the restart, the reset restart is performed by the watchdog chip again.
Example 2
As shown in fig. 2, the present embodiment provides a reset device for a board start timeout, where the device includes a first acquisition module 701 and a first analysis module 702.
The first obtaining module 701 is configured to obtain a time threshold and first input information, where the first input information includes acknowledgement information that a board has been powered on and started, and the first input information is used to trigger a programmable logic device on the board to detect a hard disk action signal of a hard disk on the board;
the first analysis module 702 is configured to analyze whether the programmable logic device detects the hard disk action signal within the time threshold, and obtain an analysis result, where the analysis result is used to trigger a reset device to perform a reset operation on a processor in the board.
In the traditional reset method, once the phenomenon of hanging and the like occurs in the starting process of the single board, the watchdog chip still outputs a flag bit signal by a CPLD (programmable logic device) and cannot be switched to a processor, so that the phenomenon of hanging and the like of the single board and cannot be reset automatically occurs; in the embodiment, the programmable logic device is added to monitor the state of the SATA_ACT (hard disk action) signal of the hard disk of the single board, so that the problem that the single board is dead during starting and cannot be reset automatically is solved.
In a specific embodiment of the disclosure, the first analysis module 702 further includes an analysis unit 7021.
The analysis unit 7021 is configured to analyze whether the programmable logic device detects the hard disk action signal within the time threshold, and if the obtained analysis result is that the programmable logic device does not detect the hard disk action signal within the time threshold, the analysis result is used to trigger the programmable logic device to send a reset command to a watchdog chip, where the reset command is used to trigger the watchdog chip to perform a reset operation on a processor in the board.
In a specific embodiment of the disclosure, the apparatus further includes a second acquisition module 703 and a selection module 704.
A second obtaining module 703, configured to obtain second input information, where the second input information includes a time threshold value range input by a user;
and a selecting module 704, configured to arbitrarily select a value from the time threshold value range as the time threshold value.
In one embodiment of the present disclosure, the apparatus further comprises a second analysis module 705.
And a second analysis module 705, configured to analyze whether the programmable logic device detects the hard disk action signal within the time threshold when the reset device performs a reset operation, and if not, send a control command, where the control command includes a command for controlling the reset device to perform a reset operation on a processor in the board.
It should be noted that, regarding the apparatus in the above embodiments, the specific manner in which the respective modules perform the operations has been described in detail in the embodiments regarding the method, and will not be described in detail herein.
Example 3
Corresponding to the above method embodiment, the embodiment of the present disclosure further provides a reset device for a board start timeout, where the reset device for a board start timeout described below and the reset method for a board start timeout described above may be referred to correspondingly with each other.
Fig. 3 is a block diagram of a reset device 800 showing a single board start timeout according to an example embodiment. As shown in fig. 3, the reset device 800 for a board start timeout may include: a processor 801, a memory 802. The single board boot timeout reset device 800 may also include one or more of a multimedia component 803, an input/output (I/O) interface 804, and a communication component 805.
The processor 801 is configured to control the overall operation of the reset device 800 for the single board start timeout, so as to complete all or part of the steps in the reset method for the single board start timeout. Memory 802 is used to store various types of data to support the operation of reset device 800 at the single board start timeout, which may include, for example, instructions for any application or method operating on reset device 800 at the single board start timeout, as well as application related data such as contact data, messages sent and received, pictures, audio, video, and the like. The Memory 802 may be implemented by any type or combination of volatile or non-volatile Memory devices, such as static random access Memory (Static Random Access Memory, SRAM for short), electrically erasable programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM for short), erasable programmable Read-Only Memory (Erasable Programmable Read-Only Memory, EPROM for short), programmable Read-Only Memory (Programmable Read-Only Memory, PROM for short), read-Only Memory (ROM for short), magnetic Memory, flash Memory, magnetic disk, or optical disk. The multimedia component 803 may include a screen and an audio component. Wherein the screen may be, for example, a touch screen, the audio component being for outputting and/or inputting audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signals may be further stored in the memory 802 or transmitted through the communication component 805. The audio assembly further comprises at least one speaker for outputting audio signals. The I/O interface 804 provides an interface between the processor 801 and other interface modules, which may be a keyboard, mouse, buttons, etc. These buttons may be virtual buttons or physical buttons. The communication component 805 is configured to perform wired or wireless communication between the reset device 800 and other devices when the board starts up and times out. Wireless communication, such as Wi-Fi, bluetooth, near field communication (Near FieldCommunication, NFC for short), 2G, 3G or 4G, or a combination of one or more thereof, the respective communication component 805 may thus comprise: wi-Fi module, bluetooth module, NFC module.
In an exemplary embodiment, the reset device 800 of the single board start timeout may be implemented by one or more application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC), digital signal processor (DigitalSignal Processor, abbreviated as DSP), digital signal processing device (Digital Signal Processing Device, abbreviated as DSPD), programmable logic device (Programmable Logic Device, abbreviated as PLD), field programmable gate array (Field Programmable Gate Array, abbreviated as FPGA), controller, microcontroller, microprocessor, or other electronic component for performing the reset method of the single board start timeout described above.
In another exemplary embodiment, a computer readable storage medium is also provided, which includes program instructions that, when executed by a processor, implement the steps of the above reset method for a single board start timeout. For example, the computer readable storage medium may be the memory 802 including program instructions described above, which are executable by the processor 801 of the reset device 800 for a board start timeout to perform the reset method for a board start timeout described above.
Example 4
Corresponding to the above method embodiments, the embodiments of the present disclosure further provide a readable storage medium, where a readable storage medium described below and a reset method of a board start timeout described above may be referred to correspondingly to each other.
A readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the reset method of the veneer start timeout of the above method embodiment.
The readable storage medium may be a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, and the like.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. The reset method of the single board starting overtime is characterized by comprising the following steps:
acquiring a time threshold and first input information, wherein the first input information comprises confirmation information that a single board is powered on and started, and the first input information is used for triggering a programmable logic device on the single board to detect a hard disk action signal of a hard disk on the single board;
analyzing whether the programmable logic device detects the hard disk action signal within the time threshold to obtain an analysis result, wherein the analysis result is used for triggering a resetting device to reset a processor in the single board, and the method comprises the following steps:
analyzing whether the programmable logic device detects the hard disk action signal within the time threshold, and if the obtained analysis result is that the programmable logic device does not detect the hard disk action signal within the time threshold, triggering the programmable logic device to send a reset command to a watchdog chip, wherein the reset command is used for triggering the watchdog chip to reset a processor in the single board.
2. The method for resetting a start timeout of a board according to claim 1, wherein before the time threshold and the first input information are acquired, further comprising:
acquiring second input information, wherein the second input information comprises a time threshold value range input by a user;
and selecting a numerical value as the time threshold value at random in the time threshold value range.
3. The method for resetting a single board start timeout according to claim 1, wherein the analyzing whether the programmable logic device detects the hard disk action signal within the time threshold value, after obtaining the analysis result, further comprises:
analyzing whether the programmable logic device detects the hard disk action signal within the time threshold when the reset device performs the reset operation, and if not, sending a control command, wherein the control command comprises a command for controlling the reset device to perform the reset operation on the processor in the single board.
4. The reset device for the starting timeout of the single board is characterized by comprising:
the first acquisition module is used for acquiring a time threshold and first input information, wherein the first input information comprises confirmation information that a single board is electrified and started, and the first input information is used for triggering a programmable logic device on the single board to detect a hard disk action signal of a hard disk on the single board;
the first analysis module is configured to analyze whether the programmable logic device detects the hard disk action signal within the time threshold, and obtain an analysis result, where the analysis result is used to trigger a reset device to perform a reset operation on a processor in the board, and includes:
the analysis unit is used for analyzing whether the programmable logic device detects the hard disk action signal within the time threshold, and if the obtained analysis result is that the programmable logic device does not detect the hard disk action signal within the time threshold, the analysis result is used for triggering the programmable logic device to send a reset command to a watchdog chip, and the reset command is used for triggering the watchdog chip to reset a processor in the single board.
5. The reset device for a single board start timeout of claim 4, further comprising:
the second acquisition module is used for acquiring second input information, wherein the second input information comprises a time threshold value range input by a user;
and the selecting module is used for arbitrarily selecting a numerical value from the time threshold value range as the time threshold value.
6. The reset device for a single board start timeout of claim 4, further comprising:
and the second analysis module is used for analyzing whether the programmable logic device detects the hard disk action signal within the time threshold when the reset device performs reset operation, and if not, the second analysis module sends a control command which comprises a command for controlling the reset device to perform reset operation on the processor in the single board.
7. The reset device for starting overtime of the single board is characterized by comprising the following components:
a memory for storing a computer program;
a processor for implementing the steps of the reset method of the single board start timeout according to any one of claims 1 to 3 when executing said computer program.
8. A readable storage medium, characterized by: the readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the reset method of a single board start timeout according to any of claims 1 to 3.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998037466A1 (en) * | 1997-02-19 | 1998-08-27 | Mitsubishi Denki Kabushiki Kaisha | Personal computer-incorporated numerical controller |
| KR20010057840A (en) * | 1999-12-23 | 2001-07-05 | 오길록 | Apparatus for protecting harddisk data |
| KR20020096661A (en) * | 2001-06-21 | 2002-12-31 | 삼성전자 주식회사 | computer system and booting control method thereof |
| JP2009271582A (en) * | 2008-04-30 | 2009-11-19 | Brother Ind Ltd | Computer system, program, and system start method for computer system |
| CN101800675A (en) * | 2010-02-25 | 2010-08-11 | 华为技术有限公司 | Failure monitoring method, monitoring equipment and communication system |
| CN101916216A (en) * | 2010-09-08 | 2010-12-15 | 神州数码网络(北京)有限公司 | Device and control method for automatically repairing BOOTROM in embedded operating system |
| CN104503859A (en) * | 2014-12-29 | 2015-04-08 | 长园深瑞继保自动化有限公司 | Method for monitoring computer operating system in starting process |
| CN105373440A (en) * | 2015-11-02 | 2016-03-02 | 努比亚技术有限公司 | Fault detection and recovery apparatus and method |
| CN110457158A (en) * | 2019-08-16 | 2019-11-15 | 深圳市智微智能软件开发有限公司 | House dog implementation method, device, equipment and storage medium based on finite state machine |
| CN110619203A (en) * | 2018-06-20 | 2019-12-27 | 深圳市中航比特通讯技术有限公司 | Logic watchdog implementation method based on finite-state machine |
| CN111625386A (en) * | 2020-05-27 | 2020-09-04 | 苏州浪潮智能科技有限公司 | Monitoring method and device for power-on overtime of system equipment |
| CN112579400A (en) * | 2020-12-30 | 2021-03-30 | 苏州浪潮智能科技有限公司 | Equipment fault positioning method, device, equipment and storage medium |
-
2021
- 2021-08-09 CN CN202110908717.6A patent/CN113641524B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998037466A1 (en) * | 1997-02-19 | 1998-08-27 | Mitsubishi Denki Kabushiki Kaisha | Personal computer-incorporated numerical controller |
| KR20010057840A (en) * | 1999-12-23 | 2001-07-05 | 오길록 | Apparatus for protecting harddisk data |
| KR20020096661A (en) * | 2001-06-21 | 2002-12-31 | 삼성전자 주식회사 | computer system and booting control method thereof |
| JP2009271582A (en) * | 2008-04-30 | 2009-11-19 | Brother Ind Ltd | Computer system, program, and system start method for computer system |
| CN101800675A (en) * | 2010-02-25 | 2010-08-11 | 华为技术有限公司 | Failure monitoring method, monitoring equipment and communication system |
| CN101916216A (en) * | 2010-09-08 | 2010-12-15 | 神州数码网络(北京)有限公司 | Device and control method for automatically repairing BOOTROM in embedded operating system |
| CN104503859A (en) * | 2014-12-29 | 2015-04-08 | 长园深瑞继保自动化有限公司 | Method for monitoring computer operating system in starting process |
| CN105373440A (en) * | 2015-11-02 | 2016-03-02 | 努比亚技术有限公司 | Fault detection and recovery apparatus and method |
| CN110619203A (en) * | 2018-06-20 | 2019-12-27 | 深圳市中航比特通讯技术有限公司 | Logic watchdog implementation method based on finite-state machine |
| CN110457158A (en) * | 2019-08-16 | 2019-11-15 | 深圳市智微智能软件开发有限公司 | House dog implementation method, device, equipment and storage medium based on finite state machine |
| CN111625386A (en) * | 2020-05-27 | 2020-09-04 | 苏州浪潮智能科技有限公司 | Monitoring method and device for power-on overtime of system equipment |
| CN112579400A (en) * | 2020-12-30 | 2021-03-30 | 苏州浪潮智能科技有限公司 | Equipment fault positioning method, device, equipment and storage medium |
Non-Patent Citations (1)
| Title |
|---|
| 一种基于有限状态机的逻辑看门狗实现方案;唐启翔;康健;邹旭军;雷群龙;尤海艳;;信息通信(第09期);45-46 * |
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