CN113641207A - Segmented power supply management circuit, power-on circuit and chip - Google Patents

Segmented power supply management circuit, power-on circuit and chip Download PDF

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Publication number
CN113641207A
CN113641207A CN202110932015.1A CN202110932015A CN113641207A CN 113641207 A CN113641207 A CN 113641207A CN 202110932015 A CN202110932015 A CN 202110932015A CN 113641207 A CN113641207 A CN 113641207A
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voltage
circuit
output end
input end
gate
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CN113641207B (en
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寇玉霞
袁芳
郭玉洁
常育宽
杨沛
张旭
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Zhejiang Haike Electronic Technology Co ltd
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Institute of Semiconductors of CAS
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Electronic Switches (AREA)

Abstract

The invention discloses a sectional power supply management circuit, which can be applied to a depletion type GaN sectional drive circuit, and comprises: the voltage pre-regulation circuit comprises a negative voltage direct current-direct current circuit, a first AND gate, a first low dropout linear regulator, a second AND gate, a second low dropout linear regulator, a third AND gate, a first OR gate, a third low dropout linear regulator and a first NOT gate. The negative voltage DC-DC circuit supplies power to the first stage circuit; the first voltage and the negative voltage supply power for the second stage circuit; the first voltage, the second voltage and the negative voltage supply power for the third-stage circuit; the third voltage and the negative voltage supply power for the fourth-stage circuit; and gates, or gates and not gates are used for the generation of internal logic signals. The sectional power supply management circuit supplies power in sections when the sectional driving circuit is in different stages, and compared with the traditional power supply mode, the sectional power supply management circuit avoids the power consumption of a non-working module and reduces the power consumption.

Description

Segmented power supply management circuit, power-on circuit and chip
Technical Field
The invention relates to the field of power management and power driving, in particular to a segmented power management circuit which can be used for a depletion type GaN segmented driving circuit and is also suitable for an enhanced GaN segmented driving circuit and a half-bridge power driving circuit.
Background
The GaN is used as a third-generation wide bandgap semiconductor material, compared with the first-generation Si and the second-generation GaAs, the GaN has the advantages of large forbidden bandwidth, high breakdown electric field intensity, high electron saturation drift speed and the like, and the power device manufactured by the GaN has the advantages of small on-resistance, high voltage resistance, high switching frequency, low junction-shell thermal resistance and high bearable junction temperature, can better meet the requirements of electronic technology on high-temperature, high-power and high-frequency devices, and has wide application prospects in industries such as automobile electronics, new energy automobiles, 5G technology and the like. The GaN device is divided into depletion type GaN and enhancement type GaN, and compared with the enhancement type GaN device, the depletion type GaN device has lower on resistance and smaller junction capacitance, and is simple in manufacturing process and better in performance.
GaN devices having a smaller CISSCapacitance, crossover losses decrease, greatly increasing its switching speed, but high switching frequencies result in large di/dt and dv/dt, introducing high frequency EMI noise can create unwanted noise and faults in the circuit. The enhanced GaN device has the same driving mode as the traditional NMOS, and is turned off at zero voltage and turned on at positive voltage; the threshold voltage of the depletion type GaN device is negative, the depletion type GaN device needs to be closed by a voltage lower than the threshold voltage, the depletion type GaN device is opened at zero voltage, and the control mode is more complex
The traditional power supply mode of the segmented driving circuit has certain defects: when the driving circuit works, all power supplies are supplied at all times, and when a certain circuit works alone at a certain stage, the rest control modules and power supply modules which do not work still consume power, so that certain loss is caused.
Disclosure of Invention
The invention provides a segmented power supply management circuit for a depletion type GaN segmented drive circuit, which supplies power to a working module and closes a power supply of a non-working module at different stages of the segmented drive circuit, solves the power consumption problem of the non-working module and the power supply thereof from the source, and can effectively reduce the power consumption of the drive circuit compared with the traditional power supply system. Meanwhile, a silicon chip implementation scheme is provided by combining the process, different substrates are selected for power supplies and driving circuits of different voltage domains, and the negative voltage generating circuit and other circuits are manufactured on the same chip, so that the problem that the traditional negative voltage generating circuit cannot be integrated in a single chip is solved.
In some embodiments of the present invention, a segmented power management circuit applied to a depletion mode GaN segmented driving circuit is provided, including:
the voltage pre-adjusting circuit comprises a first input end and a first output end, wherein the first input end is connected with an external power supply;
the negative voltage direct current-direct current circuit comprises a second input end, a second output end and a third output end, wherein the second input end is connected with the first output end, and the second output end outputs negative voltage;
the first AND gate comprises a third input end, a fourth input end and a fourth output end, and the third input end is connected with the third output end;
the first low dropout regulator comprises a fifth input end, a fifth output end and a sixth output end, wherein the fifth input end is connected with the fourth output end, and the fifth output end outputs a first voltage;
the second AND gate comprises a sixth input end, a seventh input end and a seventh output end, and the sixth input end is connected with the sixth output end;
the second low dropout regulator comprises an eighth input end, an eighth output end and a ninth output end, wherein the eighth input end is connected with the seventh output end, and the eighth output end outputs a second voltage;
the third AND gate comprises a ninth input end, a tenth input end and a tenth output end, the ninth input end is connected with the ninth output end, and the tenth input end is connected with the third output end;
a first OR gate including an eleventh input terminal, a twelfth input terminal, and an eleventh output terminal, the eleventh input terminal being connected to the tenth output terminal,
the third low dropout regulator comprises a thirteenth input end, a twelfth output end and a thirteenth output end, wherein the thirteenth input end is connected with the eleventh output end, and the twelfth output end outputs a third voltage;
the first NOT gate comprises a fourteenth input end and a fourteenth output end, the fourteenth input end is respectively connected with the twelfth input end and the thirteenth output end, and the fourteenth output end is respectively connected with the fourth input end and the seventh input end;
the negative voltage DC-DC circuit supplies power to the first stage circuit; the first voltage and the negative voltage supply power for the second stage circuit; the first voltage, the second voltage and the negative voltage supply power for the third-stage circuit; the third voltage and the negative voltage supply the fourth stage circuit.
In some embodiments of the present invention, in the segmented power management circuit, the first stage circuit includes a fast charge control circuit, the second stage circuit includes a controllable charge control circuit, the third stage circuit includes a hold charge control circuit, and the fourth stage circuit includes a discharge control circuit.
In some embodiments of the present invention, the segmented power management circuit further includes:
a drive circuit;
and the input end of the drive control circuit is used for receiving a control signal, and the output end of the drive control circuit is respectively connected with the input ends of the drive circuit of the quick charge control circuit, the controllable charge control circuit, the charge maintaining control circuit and the discharge stage control circuit.
In some embodiments of the present invention, the segmented power management circuit further includes:
a depletion mode GaN;
one end of the first resistor is connected with the grid electrode of the depletion type GaN;
the grid electrode of the first NMOS tube is connected with the output end of the rapid charging control circuit, the source electrode of the first NMOS tube is connected with the grid electrode of the depletion type GaN, and the drain electrode of the first NMOS tube is connected with a power supply of 0V;
the grid electrode of the second NMOS tube is connected with the output end of the controllable charging control circuit, the source electrode of the second NMOS tube is connected with the grid electrode of the depletion type GaN, and the drain electrode of the second NMOS tube is connected with the first voltage;
a grid electrode of the third NMOS tube is connected with the output end of the holding control circuit, a source electrode of the third NMOS tube is connected with the other end of the first resistor, and a drain electrode of the third NMOS tube is connected with a power supply of 0V;
a grid electrode of the fourth NMOS tube is connected with the output end of the discharge control circuit, a source electrode of the fourth NMOS tube is connected with a negative voltage, and a drain electrode of the fourth NMOS tube is connected with a grid electrode of the depletion type GaN;
and the grid electrode of the sixth NMOS tube is connected with the output end of the driving circuit, the source electrode of the sixth NMOS tube is connected with the power supply 0V, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the depletion type GaN.
In some embodiments of the present invention, in the segmented power management circuit described above:
the power supply of the rapid charging control circuit is connected with 0V, and the ground is connected with a negative voltage;
the power supply of the controllable charging control circuit is connected with the first voltage, and the ground is connected with the negative voltage;
the power supply of the holding control circuit is connected with 0V, and the ground is connected with a second voltage;
the power supply of the discharge control circuit is connected with the third voltage and the ground is connected with the negative voltage
The power supply of the driving circuit is connected with the first voltage, and the ground is connected with the negative voltage.
In some embodiments of the present invention, in the segmented power management circuit described above:
the negative voltage is used for rapidly charging, controllably charging and turning off the grid electrode of the depletion type GaN;
the first voltage is used for controllably charging the grid electrode of the depletion type GaN and controlling the switch of the sixth NMOS tube;
the second voltage is used for keeping the voltage of the depletion type GaN grid at the starting voltage at the stage of receiving the turn-off signal after the depletion type GaN is charged;
the third voltage is used to turn off the depletion mode GaN gate.
In some embodiments of the present invention, in the segmented power management circuit:
the range of the negative voltage comprises-14V to-20V;
the first voltage is 5V;
the second voltage is-5V;
the third voltage is 5V higher than the negative voltage.
The invention also discloses a power-on circuit, which comprises the segmented power management circuit and further comprises:
the input end of the band-gap reference voltage source is connected with the first output end, and the output end of the band-gap reference voltage source is connected with the fifth input end;
the input end of the second NOT gate is connected with the sixth output end;
one input end of the fourth AND gate is connected with the output end of the second NOT gate, the other input end of the fourth AND gate is connected with an external control signal, and the output end of the fourth AND gate is connected with the second input end;
one input end of the negative voltage detection circuit is connected with the second output end, the other input end of the negative voltage detection circuit is connected with the output end of the second NOT gate, and the output end of the negative voltage detection circuit is respectively connected with the eighth input end and the thirteenth input end;
and one input end of the NAND gate is connected with the ninth output end, the other input end of the NAND gate is connected with the thirteenth output end, and the output of the NAND gate is an end signal.
The invention also discloses a chip, and the chip is provided with the segmented power supply management circuit.
In some embodiments of the present invention, the chip includes a substrate, the substrate is a P-type doped substrate, an N well is disposed on the substrate, the ground potential of the N well region is 0V, and the ground potential of the non-N well region on the substrate is a negative voltage.
Through the technical scheme, the four-stage selective power supply is realized through the voltage pre-adjusting circuit, the negative voltage direct current-direct current circuit, the first low-dropout linear regulator, the second low-dropout linear regulator and the third low-dropout linear regulator in cooperation with the logic signal control of the first AND gate, the second AND gate, the third AND gate, the first OR gate and the NOT gate, the technical problem of power consumption of a non-working module in the related technology is solved, and the power consumption of the circuit is reduced.
Drawings
FIG. 1 schematically illustrates a logic diagram of a segmented power management circuit of an embodiment of the present invention.
Fig. 2 schematically shows a driving signal diagram of an embodiment of the invention.
Fig. 3 schematically illustrates a fast charging circuit schematic of an embodiment of the present invention.
Fig. 4 schematically shows a schematic diagram of a controllable charging circuit according to an embodiment of the invention.
FIG. 5 schematically illustrates a holding circuit schematic of an embodiment of the present invention.
FIG. 6 schematically shows a discharge circuit schematic of an embodiment of the invention.
FIG. 7 schematically illustrates a segmented drive circuit schematic of an embodiment of the present invention.
Fig. 8 schematically shows a drive circuit schematic of a segmented drive circuit of an embodiment of the invention.
Fig. 9 schematically shows a block diagram of a power supply of an embodiment of the invention.
FIG. 10 schematically illustrates a power-up management circuit of an embodiment of the present invention.
FIG. 11 schematically illustrates a VNEG brown-out detection circuit schematic of a power-up circuitry of an embodiment of the present invention.
FIG. 12 schematically shows a power-up signal diagram of an embodiment of the invention.
Fig. 13 schematically shows a power silicon implementation principle of the embodiment of the present invention.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
It is to be understood that such description is merely illustrative and not intended to limit the scope of the present invention. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention. It may be evident, however, that one or more embodiments may be practiced without these specific details. Furthermore, in the following description, descriptions of well-known technologies are omitted so as to avoid unnecessarily obscuring the concepts of the present invention.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "comprising" as used herein indicates the presence of the features, steps, operations but does not preclude the presence or addition of one or more other features.
All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It is noted that the terms used herein should be interpreted as having meanings consistent with the context of the present specification and should not be interpreted in an idealized or overly formal manner, such as, for example, a voltage pre-regulator circuit (pre-regulator), a negative voltage dc-dc circuit (negative voltage DCDC circuit); a Low-dropout regulator (LDO), also called a Low-dropout regulator, is one of linear dc voltage regulators and is used to provide a stable dc voltage power supply. Compared with a common linear direct current voltage stabilizer, the low dropout voltage stabilizer can work under the condition of smaller output and input voltage difference; AND gate (AND ), also known as AND circuit, logical product, logical AND circuit; OR gates (OR), also known as OR circuits, logic and circuits; NOT gates (INV), also called inverter circuits, inverters, logic negation circuits, and NOT gates for short, are basic units of logic circuits; a NAND gate (NAND), which is a basic logic circuit of a digital circuit, is a stack of an and gate and a not gate, and has a plurality of inputs and an output; the output (ok) of the low dropout linear regulator, the output (en) of the or gate, the negative Voltage (VNEG), and the Threshold voltage (Vth), generally refer to the input voltage corresponding to the midpoint of the transition region where the output current changes sharply with the input voltage in the transfer characteristic curve as the Threshold voltage. As in the description of the characteristics of field emission, the voltage at which the current reaches 10mA is referred to as the threshold voltage. The gate-source Voltage (VGS), the VGS nominal voltage, is the maximum voltage that can be applied between the gate and source electrodes. The main purpose of setting the rated voltage is to prevent gate oxide damage caused by excessive voltage. The voltage that the actual gate oxide layer can bear is far higher than the rated voltage, but can change with the difference of manufacturing process, so the reliability of application can be guaranteed by keeping VGS within the rated voltage. Voltage (vdd), an Electromagnetic Interference Effect (EMI), is electronic noise that interferes with the cable signal and reduces signal integrity, EMI typically generated by Electromagnetic radiation generating sources such as motors and machinery; the band gap reference voltage source (Bandgap for short) is a classic band gap reference voltage reference which realizes a voltage reference independent of temperature by utilizing the sum of a voltage with a positive temperature coefficient and a voltage with a negative temperature coefficient, and the temperature coefficients of the two are mutually offset.
The invention discloses a sectional power supply management circuit, which supplies power to a working module and turns off the power supply of a non-working module under different stages of a sectional driving circuit, solves the power consumption problem of the non-working module and the power supply thereof from the source, and can effectively reduce the power consumption of a driving circuit compared with the traditional power supply system.
Meanwhile, the silicon chip selects the same substrate for power supplies and driving circuits of different voltage domains, and the negative voltage generating circuit and other circuits are manufactured on the same chip, so that the problem that the traditional negative voltage generating circuit cannot be integrated in a single chip is solved.
FIG. 1 schematically illustrates a logic diagram of a segmented power management circuit of an embodiment of the present invention.
In some embodiments of the present invention, a segmented power management circuit is provided, which is applied to a depletion mode GaN segmented driving circuit, as shown in fig. 1, and includes a voltage pre-regulation circuit, a negative dc-dc circuit, a first and gate, a second and gate, a third and gate, a first low dropout regulator, a second low dropout regulator, a third low dropout regulator, a first or gate, and a first not gate.
In some embodiments of the present invention, the voltage pre-adjustment circuit includes a first input terminal and a first output terminal, and the first input terminal is connected to an external power source. The objective is to output a lower voltage (prevdd) to the negative dc-dc circuit DCDC.
In some embodiments of the invention, the negative dc-dc circuit comprises a second input terminal, a second output terminal and a third output terminal, the second input terminal being connected to the first output terminal, the second output terminal outputting the negative voltage, the third output terminal outputting the control signal (ok 1).
In some embodiments of the invention, the first and gate comprises a third input terminal, a fourth input terminal and a fourth output terminal, the third input terminal being connected to the third output terminal. The control signal (ok1) at the third input end and the control signal (ok4_ n) at the fourth input end pass through the first AND gate and then output an enable signal (en 1).
In some embodiments of the present invention, the first low dropout linear regulator includes a fifth input terminal, a fifth output terminal, and a sixth output terminal, the fifth input terminal is connected to the fourth output terminal, and the fifth output terminal outputs the first voltage. The enable signal (en1) enters the first low dropout linear regulator (LDO1) through the fifth input terminal and then outputs a signal (ok 2).
In some embodiments of the invention, the second and gate comprises a sixth input terminal, a seventh input terminal and a seventh output terminal, the sixth input terminal being connected to the sixth output terminal. The signal (ok2) together with the control signal (ok4_ n) at the seventh input outputs the control signal (en2) at the seventh output via a second AND gate (AND 2).
In some embodiments of the present invention, the second low dropout regulator includes an eighth input terminal, an eighth output terminal, and a ninth output terminal, the eighth input terminal is connected to the seventh output terminal, and the eighth output terminal outputs the second voltage. The control signal (en2) enters the second low dropout linear regulator (LDO2) through the eighth input, and outputs a voltage (Vdd2) at the eighth output and a signal (ok3) at the ninth output.
In some embodiments of the invention, the third and gate comprises a ninth input terminal, a tenth input terminal and a tenth output terminal, the ninth input terminal being connected to the ninth output terminal, the tenth input terminal being connected to the third output terminal.
In some embodiments of the invention, the first or gate comprises an eleventh input, a twelfth input and an eleventh output, the eleventh input being connected to the tenth output. The signal (ok3) AND the control signal (ok1) at the third output pass through a third AND gate (AND3) AND then pass through a first OR gate (OR) with the control signal (ok4) at the twelfth input to generate a control signal (en 3).
In some embodiments of the present invention, the third low dropout linear regulator includes a thirteenth input terminal, a twelfth output terminal, and a thirteenth output terminal, the thirteenth input terminal is connected to the eleventh output terminal, and the twelfth output terminal outputs the third voltage.
In some embodiments of the present invention, the first not gate includes a fourteenth input terminal and a fourteenth output terminal, the fourteenth input terminal is connected to the twelfth input terminal and the thirteenth output terminal, and the fourteenth output terminal is connected to the fourth input terminal and the seventh input terminal. The control signal (en3) passes through the third LDO3 and then outputs Vdd3 at the twelfth output terminal and outputs a signal (ok4) at the thirteenth output terminal, and the control signal enters the NOT gate (INV) from the fourteenth input terminal to generate a control signal (ok4_ n).
In some embodiments of the invention, the negative dc-dc circuit powers the first stage circuit; the first voltage and the negative voltage supply power for the second stage circuit; the first voltage, the second voltage and the negative voltage supply power for the third-stage circuit; the third voltage and the negative voltage supply the fourth stage circuit.
In some embodiments of the present invention, as shown in fig. 1, the operation process and the operation principle of the segmented power management circuit of the embodiments of the present invention are as follows:
the power supply Voltage (VCC) is connected with the voltage pre-regulator, after the conversion of the pre-regulator, the first output end of the pre-regulator outputs a lower voltage (prevdd) to the negative voltage DC-DC circuit DCDC, and the DCDC starts working and outputs a negative Voltage (VNEG) through the second output end.
AND outputting a control signal (ok1) to the third input end through the third output end, outputting an enable signal (en1) from the fourth output end after the control signal (ok4_ n) of the fourth input end passes through the first AND gate (AND1), AND enabling the enable signal en1 to enter the first low dropout linear regulator (LDO1) through the fifth input end.
The voltage (Vdd1) is output at the fifth output AND the signal (ok2) is output at the sixth output, the signal ok2 AND the control signal ok4 — n at the seventh input pass through the second AND gate (AND2) AND the control signal (en2) is output at the seventh output.
The control signal en2 enters the second low dropout linear regulator (LDO2) through the eighth input terminal, AND outputs a voltage (Vdd2) at the eighth output terminal, AND outputs a signal (ok3) at the ninth output terminal, AND the signal ok3 AND the control signal ok1 at the third output terminal pass through the third AND gate (AND3) AND then pass through the first OR gate (OR) with the control signal (ok4) at the twelfth input terminal to generate a control signal (en 3).
The control signal en3 passes through the third LDO3 and then outputs Vdd3 at the twelfth output terminal and OK4 at the thirteenth output terminal, and the control signal OK4_ n is generated after entering the NOT gate (INV) from the fourteenth input terminal.
Fig. 2 schematically shows a driving signal diagram of an embodiment of the invention.
In some embodiments of the present invention, as shown in fig. 2, when the power supply voltage is VCC, the pre-regulator circuit (pre-regulator) outputs high level, the DCDC generates negative voltage VNEG, and supplies power to the fast charging circuit D1 during the fast charging phase (i phase), and simultaneously generates high level ok1, where ok4 is low, ok4_ n is high, and ok4_ n and ok1 are in phase and then generate signal en 1.
In some embodiments of the present invention, the segment driving circuit enters a controllable charging stage (stage ii), and the LDO1 operates to generate the Vdd1 voltage and the high level signal ok2, and the Vdd1 voltage and the VNEG voltage are used together to power the controllable charging circuit D2.
In some embodiments of the present invention, the ok2 signal is anded with the high ok4_ n to generate the signal en2 as high, the segment driver enters the hold stage, the LDO2 operates to generate Vdd2 voltage to power the hold circuit D3, and simultaneously generate the high ok3 signal, the ok3 signal is anded with the high ok1 as high, and is further ored with the low ok4 to generate the high en3 signal.
In some embodiments of the present invention, the segment driving circuit enters into the discharging stage, the LDO3 operates to generate Vdd3 voltage to power the discharging circuit D4, and at the same time, generates a high ok4 signal to generate a low ok4 — n signal via INV to make the enable signals en1 and en2 become low, the LDO1 and the LDO2 stop operating, and the controllable charging circuit and the holding circuit have no power supply, so that the segment driving circuit has no redundant power consumption.
In some embodiments of the present invention, to avoid the turn-on of depletion mode GaN, a negative Voltage (VNEG) is applied to the gate, while avoiding false turn-on due to dv/dt crosstalk.
In some embodiments of the present invention, the off-voltage VNEG is much different from the threshold voltage (Vth), and as can be seen from Q ═ CU, a large off-voltage increases the gate charge Q that needs to be charged to turn on the GaN deviceGAnd thus the charging speed of the process.
In some embodiments of the invention, in the first phase (phase i), the fast charging circuit (D1) is used to drive the switching tube (M1) to charge the depletion mode GaN (M5) gate, and the gate current is large (Ig1), so that the GaN gate-source Voltage (VGS) is quickly swept from VNEG to Vth; the second phase (phase II) driving strength is too high to cause di/dt and dv/dt effects, and the high-speed changing current and voltage during the switching process can generate strong electromagnetic interference (EMI) effects, which can cause the circuit to generate noise to cause errors. In order to improve EMI noise and ensure high-reliability work of a GaN device, a sectional driving mode is adopted for driving, namely, the grid source voltage is quickly charged before reaching a threshold voltage, and the starting time delay is reduced as much as possible; when the threshold voltage is reached, the controllable charging circuit provides stable small current charging in a di/dt area and a dv/dt area, and the dv/dt is adjustably controlled by changing the charging current, so that the EMI (electro-magnetic interference) is reduced; when the voltage reaches the starting voltage, in order to reduce the static power consumption of the circuit, the controllable charging circuit needs to be turned off at the moment, but the grid electrode of the GaN power tube is in a high-resistance state and is easily influenced by crosstalk, and at the moment, the grid electrode potential is connected to the starting voltage by adopting the holding circuit, a low-resistance path is provided for the grid electrode of the GaN power tube, and the influence of crosstalk noise is reduced.
In some embodiments of the invention, a controllable charging circuit (D2) is used to control the charging intensity at this stage to avoid the instantaneous large current from rapidly charging the GaN device; in the third stage (stage III), the GaN device is fully charged to the turn-on voltage (Von), at the moment, the grid electrode of the GaN device is not required to be charged by a controllable circuit, and the grid electrode is kept at the turn-on voltage by adopting a holding circuit (D3); the fourth stage (stage IV) is a discharging stage, and the discharging circuit (D4) controls the switch tube (M4) to be opened to provide a drain path for the grid electrode charge.
In some embodiments of the present invention, for the operation principle of the depletion type GaN segment driver circuit, the main operation principle of the segment power management circuit of the present invention is that when in the fast charging phase (i phase), the negative voltage DCDC generates VNEG voltage to supply power to the fast charging circuit D1.
In some embodiments of the present invention, after the fast charging circuit D1 increases the gate-source voltage VGS of the depletion mode GaN (M5) from VNEG to Vth, the segmented driving circuit enters the controllable charging mode (phase ii), and the low dropout regulator LDO1 generates Vdd1 voltage, which is used as the VNEG voltage to power the controllable charging circuit D2, and Vdd1 voltage to power the driving circuit D5.
In some embodiments of the present invention, after the gate-source voltage VGS of the depletion mode GaN (M5) is raised from Vth to Von, the segmented driving circuit enters the holding stage (stage iii), and the low dropout regulator LDO2 circuit generates the voltage Vdd2 to power the holding circuit D3.
In some embodiments of the present invention, the discharging stage (stage iv) low dropout regulator LDO3 generates a Vdd3 voltage, which is used to supply the discharging circuit D4 together with the VNEG voltage, after the discharging circuit operates, the ok4 signal generated by the low dropout regulator LDO3 is high level, and becomes low level after passing through the inverter, and the low dropout regulators LDO1 and LDO2 are controlled to stop operating, and the controllable charging circuit D2, the holding circuit D3, and the driving circuit D5 powered by Vdd1 and Vdd2 stop operating.
In some embodiments of the invention, the segmented power management circuit is matched with the segmented driving circuit, when the segmented driving circuit enters a driving stage, the power management circuit generates corresponding voltage to supply power to the driving circuit, and the power supply is stopped when the driving circuit does not work, so that the possibility that the driving circuit still consumes power when the driving circuit does not work is avoided, and the system power consumption is effectively reduced.
Fig. 3 schematically illustrates a fast charging circuit diagram according to an embodiment of the present invention, fig. 4 schematically illustrates a controllable charging circuit diagram according to an embodiment of the present invention, fig. 5 schematically illustrates a holding circuit diagram according to an embodiment of the present invention, and fig. 6 schematically illustrates a discharging circuit diagram according to an embodiment of the present invention, which is within the ability of those skilled in the art to understand the specific circuit design of the present invention through fig. 3 to fig. 6, and will not be described herein again.
In some embodiments of the present invention, the segmented power management circuit further includes a driving circuit and a driving control circuit.
In some embodiments of the invention, the driver circuit is located between the main circuit and the control circuit, and the intermediate circuit is used to amplify the signal of the control circuit (i.e. amplify the signal of the control circuit to enable it to drive the power transistor).
In some embodiments of the present invention, the input end of the driving control circuit is configured to receive a control signal, and the output end of the driving control circuit is connected to the input ends of the fast charging control circuit, the controllable charging control circuit, the charge maintaining control circuit, and the discharging stage control circuit, respectively.
In some embodiments of the present invention, the segmented power management circuit further comprises a depletion mode GaN, a first resistor, and an NMOS transistor.
In some embodiments of the present invention, the source and drain of the field effect transistor are symmetrical in structure and can be used interchangeably, and the gate voltage of the depletion type MOS transistor can be positive or negative, compared to the enhancement type GaN.
One end of the first resistor is connected with the grid electrode of the depletion type GaN. And the grid electrode of the first NMOS tube is connected with the output end of the rapid charging control circuit, the source electrode of the first NMOS tube is connected with the grid electrode of the depletion type GaN, and the drain electrode of the first NMOS tube is connected with a power supply of 0V. And the grid electrode of the second NMOS tube is connected with the output end of the controllable charging control circuit, the source electrode of the second NMOS tube is connected with the grid electrode of the depletion type GaN, and the drain electrode of the second NMOS tube is connected with the first voltage. And the grid electrode of the third NMOS tube is connected with the output end of the holding control circuit, the source electrode of the third NMOS tube is connected with the other end of the first resistor, and the drain electrode of the third NMOS tube is connected with a power supply of 0V. And a grid electrode of the fourth NMOS tube is connected with the output end of the discharge control circuit, a source electrode of the fourth NMOS tube is connected with VNEG, and a drain electrode of the fourth NMOS tube is connected with a grid electrode of depletion type GaN. And the grid electrode of the sixth NMOS tube is connected with the output end of the driving circuit, the source electrode of the sixth NMOS tube is connected with the power supply 0V, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the depletion type GaN.
Fig. 7 schematically shows a sectional driving circuit schematic diagram of an embodiment of the present invention, and fig. 8 schematically shows a driving circuit schematic diagram of a sectional driving circuit of an embodiment of the present invention.
Fig. 9 schematically shows a block diagram of a power supply of an embodiment of the invention.
In some embodiments of the present invention, due to the negative voltage turn-off characteristic of the GaN device, a positive power voltage (Vdd1) and a certain negative power voltage are required during the driving operation of the GaN device, and the involved negative power voltages include VNEG, Vdd2 (0-V)0)、Vdd3(VNEG+V0) Fig. 9 shows a block diagram of the generation of the power supply voltage.
In some embodiments of the invention, the first low dropout linear regulator (LDO1) module power is VCC, ground is 0V, resulting in a Vdd1 voltage, the DCDC module power is 0V, resulting in a VNEG voltage, the second low dropout linear regulator (LDO2) module power is 0V, ground is VNEG, resulting in Vdd2, Vdd2 is a relatively 0V low V0The third LDO3 module has a power supply of 0V, ground is VNEG, and Vdd3 and Vdd3 is a high V relative to VNEG0The voltage of (c).
In some embodiments of the present invention, the fast charge control circuitry is powered at 0V and grounded at VNEG. The power supply of the controllable charging control circuit is connected with the first voltage, and the ground is connected with VNEG. The power supply of the holding control circuit is connected with 0V, and the ground is connected with the second voltage. The power supply of the discharge control circuit is connected with the third voltage and the ground is connected with VNEG. The power supply of the driving circuit is connected with the first voltage, and the ground is connected with VNEG.
In some embodiments of the invention, VNEG is used to rapidly charge, controllably charge, and turn off the gate of depletion mode GaN.
In some embodiments of the present invention, the first voltage is used for controllably charging the gate of the depletion mode GaN and for controlling the switching of the sixth NMOS transistor.
In some embodiments of the present invention, the second voltage is used to maintain the voltage of the depletion mode GaN gate at the turn-on voltage after the depletion mode GaN is charged to the stage of receiving the turn-off signal.
In some embodiments of the present invention, the third voltage is used to turn off the depletion mode GaN gate.
In some embodiments of the invention, the VNEG range includes-14V to-20V. The first voltage is 5V. The second voltage is-5V. The third voltage is 5V higher than VNEG. In terms of a driving mode, the depletion-mode GaN device adopts a sectional driving mode, a sectional driving circuit of the depletion-mode GaN device generally comprises a quick charge control circuit (D1), a controllable charge control circuit (D2), a holding control circuit (D3), a discharge control circuit (D4) and a driving circuit (D5), power supply voltages required by modules are different, VNEG (generally-14V to-20V) is required to be used as the ground of the quick charge control circuit (D1), the controllable charge control circuit (D2) and the discharge control circuit (D4) for supplying power, and functions of quick charge and controllable charge to the depletion-mode GaN gate and turn off the depletion-mode GaN gate are realized; vdd1 (typically 5V), a power supply for the controllable charging circuit (D2) enabling controllable charging of the GaN power tube gate, and a power supply for the driver circuit (D5) controlling the switching of the sixth NMOS (M6); vdd2 (generally-5V) is used as the ground of a holding circuit in the sectional drive for supplying power, so that the function of keeping the grid voltage of the GaN power tube at the turn-on voltage before the turn-off signal comes after the charging is finished is realized; vdd3 (usually VNEG +5V) is used as a power supply of the discharge control circuit (D4) to turn off the depletion GaN gate.
In a second aspect of the embodiments of the present invention, a power-on circuit is disclosed, which includes the segmented power management circuit, and further includes: the band-gap reference voltage source, the second NOT gate, the fourth AND gate, the negative voltage detection circuit and the NAND gate.
In some embodiments of the present invention, the bandgap reference voltage source has an input terminal connected to the first output terminal and an output terminal connected to the fifth input terminal.
In some embodiments of the invention, the second not gate has an input connected to the sixth output.
In some embodiments of the present invention, an input terminal of the fourth and gate is connected to the output terminal of the second not gate, another input terminal of the fourth and gate is connected to the external control signal, and an output terminal of the fourth and gate is connected to the second input terminal.
In some embodiments of the present invention, one input terminal of the negative voltage detection circuit is connected to the second output terminal, another input terminal of the negative voltage detection circuit is connected to the output terminal of the second not gate, and the output terminals of the negative voltage detection circuit are respectively connected to the eighth input terminal and the thirteenth input terminal.
In some embodiments of the present invention, the nand gate has one input connected to the ninth output, another input connected to the thirteenth output, and the nand gate outputs the end signal.
Fig. 10 schematically shows a power-on management circuit diagram according to an embodiment of the present invention, fig. 11 schematically shows a VNEG under-voltage detection circuit diagram of a power-on pipeline circuit according to an embodiment of the present invention, and fig. 12 schematically shows a power-on signal diagram according to an embodiment of the present invention.
Fig. 10 shows a power-on circuit implementation of the segment driving circuit according to the present invention, which includes a voltage pre-regulator circuit pre-regulator, a bandgap reference voltage source bandgap, a first low dropout regulator LDO1, a second low dropout regulator LDO2, a third low dropout regulator LDO3, a negative voltage DCDC circuit, a VNEG brown-out detection circuit (VNEG _ UV), an inverter INV, an AND NAND gate, AND the brown-out detection circuit is shown in fig. 11.
In some embodiments of the present invention, when the power supply Voltage (VCC) rises, the voltage pre-regulation circuit pre-regulation 1 (fig. 12) starts to generate the voltage (prevdd), and under the enable action of the prevdd voltage, the bandgap reference voltage source bandgapt2 (fig. 12) starts to generate the voltage (Vbg — 1p2) of 1.2V, and the first low dropout linear regulator LDO1 generates the voltage of Vdd1 with reference to the voltage of 1.2V.
In some embodiments of the present invention, when the time t3 (fig. 12) is reached, a signal (LDO1_ ok _ n) is generated to indicate that the first low dropout linear regulator LDO1 has completed working, the LDO1_ ok _ n signal is passed through an inverter to obtain an en _ vneg signal, and an enable signal (en _ dcdc) is obtained when the external control signal (ctr) is passed through an and gate.
In some embodiments of the present invention, when the DCDC output voltage starts to drop from 0V at time t4 (fig. 12) and drops to time t5 (fig. 12) under the enabling action of en _ DCDC, the VNEG under-voltage detection circuit (VNEG _ UV) detects the VNEG signal under the action of the en _ VNEG enabling signal to generate a VNEG _ ok _ n signal, which indicates that the DCDC module has generated the VNEG voltage.
In some embodiments of the present invention, under the action of the vneg _ ok _ n enable signal, the second low dropout linear regulator LDO2 generates a Vdd2 voltage and LDO2_ ok _ n signal, the third low dropout linear regulator LDO3 generates a Vdd3 voltage and LDO3_ ok _ n signal, and LDO2_ ok _ n and LDO3_ ok _ n generate an EN signal through a NAND gate NAND, indicating that all voltage sources are fully operated.
FIG. 13 is a schematic diagram of a power silicon implementation of an embodiment of the invention.
In a third aspect of embodiments of the present invention, a chip is provided, on which any one of the segmented power management circuits is disposed.
Fig. 13 shows a silicon chip implementation of the segmented driving circuit and the power supply according to the present invention, where the substrate Potential (PSUB) of the chip is VNEG, and the ground potentials of the driving circuit (D5) and the first low dropout regulator LDO1 are 0V.
In some embodiments of the present invention, in a single N-well, the ground of the fast charging circuit D1, the controllable charging circuit D2, the holding circuit D3, the discharging circuit D4, the negative voltage DCDC, the second low dropout linear regulator LDO2, and the third low dropout linear regulator LDO3 are VNEG, so seven modules are located in the substrate. The project combines a specific process, innovatively adopts the chip substrate as negative pressure, reasonably utilizes the traditional silicon-based process to realize negative pressure output, and reduces the design difficulty compared with the traditional buck-boost mode. The Buck-BOOST circuit is a traditional BOOST and Buck circuit, the two circuits often appear in the circuit design together, the Buck circuit refers to a single-tube non-isolated direct current conversion with output voltage smaller than voltage, and the BOOST circuit refers to a single-tube non-isolated direct current conversion with output voltage higher than input voltage.
In some embodiments of the present invention, the chip includes a substrate, the substrate is a P-type doped substrate, an N well is disposed on the substrate, the ground potential of the N well region is 0V, and the ground potential of the non-N well region on the substrate is a negative voltage. From the process point of view, for the process of the conventional substrate 0, it is very difficult to realize the monolithic integration of positive pressure and negative pressure by adopting the buck-boost structure. The scheme can better solve the problem.
The segmented power management circuit for the depletion type GaN segmented driving circuit is mainly applied to the depletion type GaN segmented driving circuit, provides a reliable power supply for the driving circuit, and can effectively reduce the power consumption of the segmented driving circuit by adopting the segmented power management idea and matching with the segmented driving mode.
So far, the embodiments of the present invention have been described in detail with reference to the accompanying drawings. It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. In addition, the above definitions of the components are not limited to the specific structures, shapes or manners mentioned in the embodiments, and those skilled in the art may easily modify or replace them.
It will be appreciated by a person skilled in the art that various combinations and/or combinations of features described in the various embodiments and/or in the claims of the invention are possible, even if such combinations or combinations are not explicitly described in the invention. In particular, various combinations and/or combinations of the features recited in the various embodiments and/or claims of the present invention may be made without departing from the spirit or teaching of the invention. All such combinations and/or associations fall within the scope of the present invention.
The above embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, and it should be understood that the above embodiments are only examples of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A segmented power management circuit applied to a depletion mode GaN segmented drive circuit is characterized by comprising:
the voltage pre-adjusting circuit comprises a first input end and a first output end, wherein the first input end is connected with an external power supply;
the negative voltage direct current-direct current circuit comprises a second input end, a second output end and a third output end, wherein the second input end is connected with the first output end, and the second output end outputs negative voltage;
the first AND gate comprises a third input end, a fourth input end and a fourth output end, and the third input end is connected with the third output end;
the first low dropout regulator comprises a fifth input end, a fifth output end and a sixth output end, wherein the fifth input end is connected with the fourth output end, and the fifth output end outputs a first voltage;
the second AND gate comprises a sixth input end, a seventh input end and a seventh output end, and the sixth input end is connected with the sixth output end;
the second low dropout regulator comprises an eighth input end, an eighth output end and a ninth output end, wherein the eighth input end is connected with the seventh output end, and the eighth output end outputs a second voltage;
the third AND gate comprises a ninth input end, a tenth input end and a tenth output end, the ninth input end is connected with the ninth output end, and the tenth input end is connected with the third output end;
a first OR gate including an eleventh input terminal, a twelfth input terminal, and an eleventh output terminal, the eleventh input terminal being connected to the tenth output terminal, the first OR gate
The third low dropout regulator comprises a thirteenth input end, a twelfth output end and a thirteenth output end, wherein the thirteenth input end is connected with the eleventh output end, and the twelfth output end outputs a third voltage;
a first not gate, including a fourteenth input end and a fourteenth output end, where the fourteenth input end is connected to the twelfth input end and the thirteenth output end, and the fourteenth output end is connected to the fourth input end and the seventh input end, respectively;
the negative voltage direct current-direct current circuit supplies power to the first-stage circuit; the first voltage and the negative voltage supply power for the second-stage circuit; the first voltage, the second voltage and the negative voltage supply power for a third-stage circuit; the third voltage and the negative voltage supply the fourth stage circuit.
2. The segmented power management circuit of claim 1, wherein the first stage circuit comprises a fast charge control circuit, the second stage circuit comprises a controllable charge control circuit, the third stage circuit comprises a hold charge control circuit, and the fourth stage circuit comprises a discharge control circuit.
3. The segmented power management circuit of claim 2, further comprising:
a drive circuit;
and the input end of the driving control circuit is used for receiving a control signal, and the output end of the driving control circuit is respectively connected with the input ends of the quick charging control circuit, the controllable charging control circuit, the charge maintaining control circuit and the discharging stage control circuit.
4. The segmented power management circuit of claim 3, further comprising:
a depletion mode GaN;
one end of the first resistor is connected with the grid electrode of the depletion type GaN;
the grid electrode of the first NMOS tube is connected with the output end of the rapid charging control circuit, the source electrode of the first NMOS tube is connected with the grid electrode of the depletion type GaN, and the drain electrode of the first NMOS tube is connected with a power supply of 0V;
a grid electrode of the second NMOS tube is connected with the output end of the controllable charging control circuit, a source electrode of the second NMOS tube is connected with the grid electrode of the depletion type GaN, and a drain electrode of the second NMOS tube is connected with the first voltage;
a grid electrode of the third NMOS tube is connected with the output end of the holding control circuit, a source electrode of the third NMOS tube is connected with the other end of the first resistor, and a drain electrode of the third NMOS tube is connected with a power supply of 0V;
a grid electrode of the fourth NMOS tube is connected with the output end of the discharge control circuit, a source electrode of the fourth NMOS tube is connected with the negative voltage, and a drain electrode of the fourth NMOS tube is connected with the grid electrode of the depletion type GaN;
and the grid electrode of the sixth NMOS tube is connected with the output end of the driving circuit, the source electrode of the sixth NMOS tube is connected with a power supply 0V, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the depletion type GaN.
5. The segmented power management circuit of claim 4,
the power supply of the rapid charging control circuit is connected with 0V, and is grounded with the negative voltage;
the power supply of the controllable charging control circuit is connected with the first voltage and is grounded with the negative voltage;
the power supply of the holding control circuit is connected with 0V, and the ground is connected with the second voltage;
the power supply of the discharge control circuit is connected with the third voltage and is grounded with the negative voltage
The power supply of the driving circuit is connected with the first voltage, and the ground is connected with the negative voltage.
6. The segmented power management circuit of claim 5,
the negative voltage is used for rapidly charging, controllably charging and turning off the grid electrode of the depletion type GaN;
the first voltage is used for controllably charging the grid electrode of the depletion type GaN and controlling the switch of a sixth NMOS tube;
the second voltage is used for keeping the voltage of the depletion type GaN grid at a starting voltage at the stage of receiving a turn-off signal after the depletion type GaN is charged;
the third voltage is used for turning off the depletion mode GaN grid electrode.
7. The segmented power management circuit of claim 6,
the range of the negative voltage comprises-14V to-20V;
the first voltage is 5V;
the second voltage is-5V;
the third voltage is 5V higher than the negative voltage.
8. A power up circuit comprising the segmented power management circuit of any of claims 1 to 7, further comprising:
the input end of the band-gap reference voltage source is connected with the first output end, and the output end of the band-gap reference voltage source is connected with the fifth input end;
a second not gate, an input terminal of the second not gate being connected to the sixth output terminal;
one input end of the fourth AND gate is connected with the output end of the second NOT gate, the other input end of the fourth AND gate is connected with an external control signal, and the output end of the fourth AND gate is connected with the second input end;
one input end of the negative voltage detection circuit is connected with the second output end, the other input end of the negative voltage detection circuit is connected with the output end of the second NOT gate, and the output end of the negative voltage detection circuit is respectively connected with the eighth input end and the thirteenth input end;
and one input end of the NAND gate is connected with the ninth output end, the other input end of the NAND gate is connected with the thirteenth output end, and the output of the NAND gate is an end signal.
9. A chip on which a segmented power management circuit as claimed in any one of claims 1 to 7 is provided.
10. The chip of claim 9, comprising a substrate, wherein the substrate is a P-type doped substrate, an N-well is disposed on the substrate, the ground potential of the N-well region is 0V, and the ground potential of the non-N-well region on the substrate is the negative voltage.
CN202110932015.1A 2021-08-13 2021-08-13 Segmented power supply management circuit, power-on circuit and chip Active CN113641207B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110149042A (en) * 2019-06-14 2019-08-20 电子科技大学 A kind of power tube gate driving circuit with drive part by part function
CN110504822A (en) * 2019-08-26 2019-11-26 电子科技大学 Upper power tube drive part by part control circuit suitable for half-bridge gate drive circuit
CN111354305A (en) * 2018-12-21 2020-06-30 三星显示有限公司 Display driver and method of driving the same
US10911045B1 (en) * 2020-04-03 2021-02-02 University Of Electronic Science And Technology Of China Segmented direct gate drive circuit of a depletion mode GaN power device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111354305A (en) * 2018-12-21 2020-06-30 三星显示有限公司 Display driver and method of driving the same
CN110149042A (en) * 2019-06-14 2019-08-20 电子科技大学 A kind of power tube gate driving circuit with drive part by part function
CN110504822A (en) * 2019-08-26 2019-11-26 电子科技大学 Upper power tube drive part by part control circuit suitable for half-bridge gate drive circuit
US10911045B1 (en) * 2020-04-03 2021-02-02 University Of Electronic Science And Technology Of China Segmented direct gate drive circuit of a depletion mode GaN power device

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Patentee before: INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES